Search results for "co-synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Motonori Doi, Rie Ohtsuki, Rie Hikima, Osamu Tanno, Shoji Tominaga	Synthesis of Facial Images with Foundation Make-Up.	CCIW	2009	DBLP DOI BibTeX RDF	Facial image synthesis, Make-up foundation, Kubelka-Munk theory, Texture synthesis, Color image, Multi-resolution analysis
23	Thomas Hurtut, Pierre-Edouard Landes, Joëlle Thollot, Yann Gousseau, R. Drouillhet, Jean-François Coeurjolly	Appearance-guided synthesis of element arrangements by example.	NPAR	2009	DBLP DOI BibTeX RDF	by-example synthesis, vector texture synthesis, NPR
23	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
23	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
23	Hansu Cho, Samar Abdi, Daniel Gajski	Interface synthesis for heterogeneous multi-core systems from transaction level models.	LCTES	2007	DBLP DOI BibTeX RDF	HW-SW co-design, universal bridge, channel, transaction level model, communication synthesis, interface synthesis
23	Rupal Patel, Michael Everett, Eldar Sadikov	Loudmouth: : modifying text-to-speech synthesis in noise.	ASSETS	2006	DBLP DOI BibTeX RDF	text-to-speech synthesis (TTS), speech synthesis, augmentative and alternative communication (AAC)
23	Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy	An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications
23	Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara	Strong self-testability for data paths high-level synthesis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
23	Heinz Mayer	Image-Based Texture Analysis for Realistic Image Synthesis.	SIBGRAPI	2000	DBLP DOI BibTeX RDF	image based texture analysis, digital image synthesis, intensity values, highlighting artifacts, image based measurement system, BRDF values, diffuse reflectance coefficient, compact description, measured surface properties, arbitrary shape, standard CCD camera, image texture, reflectance model, realistic image synthesis, light source, measurement system, surface reflectance, bidirectional reflectance distribution function
23	Jon Christensen, Joe Marks, J. Thomas Ngo	Automatic motion synthesis for 3D mass-spring models.	Vis. Comput.	1997	DBLP DOI BibTeX RDF	Animation, Stochastic optimization, Heuristic methods, Motion synthesis, Mass-spring models, Controller synthesis
23	Harry Hsieh, Alberto L. Sangiovanni-Vincentelli	Modeling micro-controller peripherals for high-level co-simulation and synthesis.	CODES	1997	DBLP DOI BibTeX RDF	micro-controllers, FSM synthesis, co-simulation, peripherals, co-synthesis
23	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
23	Christos A. Papachristou, Mikhail Baklashov	A test synthesis technique using redundant register transfers.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions
23	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid	On the Synthesis of MVL Functions Using Input and Output Phase Assignments.	ISMVL	1997	DBLP DOI BibTeX RDF	MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic
23	Pierre Flener, Kung-Kiu Lau, Mario Ornaghi	Correct-Schema-Guided Synthesis of Steadfast Programs.	ASE	1997	DBLP DOI BibTeX RDF	steadfast programs, semi-automated software development, schema correctness, structured program design principles, hierarchical program synthesis, syntactic representation, higher-order expressions, informal knowledge capture, program schema formalisation, open first-order logical theory, open logic program, logic programming, program synthesis, domain knowledge
23	Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara	An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
23	Harry Hengster, Rolf Drechsler, Bernd Becker 0001, Stefan Eckrich, Tonja Pfeiffer	AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	EXOR based synthesis, synthesis for testability, delay optimization
23	Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij	The MSP.RTL real-time scheduler synthesis tool.	RTSS	1996	DBLP DOI BibTeX RDF	MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic
23	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
23	Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee	Eliminating False Loops Caused by Sharing in Control Path.	ISSS	1996	DBLP DOI BibTeX RDF	false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
23	Juan Manuel Ramírez-Cortés, Guillermo Bolanos, David Báez-López	A Low-Cost Speech-Synthesis System for Translation of ASCII Text to Oral Language as a Vision Impaired Aid.	CBMS	1995	DBLP DOI BibTeX RDF	add-on boards, low-cost speech-synthesis system, ASCII text to oral language translation, vision impaired aid, syllables database, PC expansion slot, signal manipulation, speech acquisition, natural languages, extension, speech synthesis, language translation, microcomputer applications, Spanish language, handicapped aids
23	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers.	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
23	Alok Kumar, Anshul Kumar, M. Balakrishnan	Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs
23	Ramayya Kumar, Thomas Kropf, Klaus Schneider 0001	Formal synthesis of circuits with a simple handshake protocol.	VLSI Design	1995	DBLP DOI BibTeX RDF	formal circuit synthesis, preproven building blocks, higher-order temporal operators, parametrized data signals, sequentially composed modules, parallel module composition, protocols, high level synthesis, logic design, operator semantics, template, formal logic, correctness proofs, synchronous circuits, handshake protocol, HOL theorem prover
23	Vishwani D. Agrawal, Kwang-Ting Cheng	Finite state machine synthesis with embedded test function.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	VLSI, Computer-Aided Design, Test Generation, Logic Synthesis, Synthesis for Testability
23	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
23	Antoine Girard	Synthesis using approximately bisimilar abstractions: state-feedback controllers for safety specifications.	HSCC	2010	DBLP DOI BibTeX RDF	approximate bisimulation, abstraction, synthesis, safety, hybrid systems, switched systems
23	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
23	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran	Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	converter synthesis, protocol compatibility, System-on-chip, automatic design
23	Ehsan Miandji, M. H. Sargazi Moghadam, Faramarz F. Samavati, Mohammad Emadi	Real-time multi-band synthesis of ocean water with new iterative up-sampling technique.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	Wave synthesis, Image up-sampling, Real-time rendering, Programmable graphics hardware
23	Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
23	Yi Yang 0001, Yueting Zhuang, Dong Xu 0001, Yunhe Pan, Dacheng Tao, Stephen J. Maybank	Retrieval based interactive cartoon synthesis via unsupervised bi-distance metric learning.	ACM Multimedia	2009	DBLP DOI BibTeX RDF	cartoon clip synthesis, cartoon image, image retrieval
23	Jing Fan, Jian-wei Ren, Ying Tang 0004	Controllable texture synthesis for runtime simulation of large-scale vegetation.	VRCAI	2009	DBLP DOI BibTeX RDF	vegetation simulation, GPU, texture synthesis
23	Robert Wille, Rolf Drechsler	BDD-based synthesis of reversible logic for large functions.	DAC	2009	DBLP DOI BibTeX RDF	synthesis, decision diagrams, reversible logic, quantum logic
23	Anna Bernasconi 0001, Valentina Ciriani, Fabrizio Luccio, Linda Pagli	Synthesis of Autosymmetric Functions in a New Three-Level Form.	Theory Comput. Syst.	2008	DBLP DOI BibTeX RDF	Autosymmetry, EXOR factor, SOP form, ORAX form, Three-level synthesis, Logical design
23	Fei Su, Krishnendu Chakrabarty	High-level synthesis of digital microfluidic biochips.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	scheduling, system-on-chip, High-level synthesis, microfluidics, biochips
23	Henricus M. W. (Eric) Verbeek, A. Johannes Pretorius, Wil M. P. van der Aalst, Jarke J. van Wijk	Assessing State Spaces Using Petri-Net Synthesis and Attribute-Based Visualization.	Trans. Petri Nets Other Model. Concurr.	2008	DBLP DOI BibTeX RDF	Petri-net synthesis, visualization, attributes, state spaces
23	Daniel G. Aliaga, Carlos A. Vanegas, Bedrich Benes	Interactive example-based urban layout synthesis.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	content-aware image editing, texture and image synthesis, procedural modeling, example-based
23	Philippe Darondeau, Maciej Koutny, Marta Pietkiewicz-Koutny, Alexandre Yakovlev	Synthesis of Nets with Step Firing Policies.	Petri Nets	2008	DBLP DOI BibTeX RDF	step firing policy, step transition system, synthesis problem, Petri nets, regions
23	Farhad Arbab, Sun Meng	Synthesis of Connectors from Scenario-Based Interaction Specifications.	CBSE	2008	DBLP DOI BibTeX RDF	Scenario-based Specification, UML, Synthesis, Connector, Reo, Constraint Automata
23	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
23	Bernd J. Kröger, Peter Birkholz	Articulatory Synthesis of Speech and Singing: State of the Art and Suggestions for Future Research.	COST 2102 School (Vietri)	2008	DBLP DOI BibTeX RDF	singing, articulatory synthesis, vocal tract acoustics, movement control, speech acquisition, speech, articulation, human-human interaction
23	Hugo Flordal, Robi Malik, Martin Fabian, Knut Åkesson	Compositional Synthesis of Maximally Permissive Supervisors Using Supervision Equivalence.	Discret. Event Dyn. Syst.	2007	DBLP DOI BibTeX RDF	Controllability, Synthesis, Discrete event systems, Supervisory control, Model reduction, Finite state automata, Nonblocking
23	Ying Li, Jiaxin L. Fu, Nancy S. Pollard	Data-Driven Grasp Synthesis Using Shape Matching and Task-Based Pruning.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	Grasp synthesis, grasp quality, shape matching, hands
23	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Techniques for the synthesis of reversible Toffoli networks.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	reversible logic synthesis, quantum computing, circuit optimization
23	Xuexiang Xie, Feng Tian 0006, Hock Soon Seah	Feature Guided Texture Synthesis (FGTS) for artistic style transfer.	DIMEA	2007	DBLP DOI BibTeX RDF	artistic style transfer, perceptual similarity, non-photorealistic rendering, texture synthesis, texture transfer
23	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
23	Mohammad Mehdi Hassani, Reza Berangi	Improving the COWLS algorithm for hardware software co-synthesis of wireless client-server systems using preference vectors and peak power information.	CompSysTech	2007	DBLP DOI BibTeX RDF	embedded systems, client server systems, wireless systems, low power consumption, hardware-software co-synthesis
23	Joachim Becker, Stanis Trendelenburg, Fabian Henrici, Yiannos Manoli	Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm.	GECCO	2007	DBLP DOI BibTeX RDF	hardware realization, genetic algorithm, computer aided design, synthesis, evolvable hardware, microelectronics
23	Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade	Hand-in-hand verification of high-level synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSMD model, formal verification, high-level synthesis, equivalence checking
23	Chien-Chung Tseng, Jenn-Jier James Lien	Synthesis of Exaggerative Caricature with Inter and Intra Correlations.	ACCV (1)	2007	DBLP DOI BibTeX RDF	Exaggerative rate, Exaggerative caricature synthesis, Non-photorealistic rendering (NPR), Eigenspace
23	Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh	Postlayout optimization for synthesis of Domino circuits.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	optimization, synthesis, Domino logic
23	Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer	Combining module selection and resource sharing for efficient FPGA pipeline synthesis.	FPGA	2006	DBLP DOI BibTeX RDF	resource sharing, pipeline scheduling, module selection, data-path synthesis
23	Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke	Increasing hardware efficiency with multifunction loop accelerators.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware
23	Ai-Hsin Liu, Robert P. Dick	Automatic run-time extraction of communication graphs from multithreaded applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	communication, benchmarks, synthesis, multithread, task graph, run-time
23	Feng Dong 0005, Gordon Clapworthy	Volumetric texture synthesis for non-photorealistic volume rendering of medical data.	Vis. Comput.	2005	DBLP DOI BibTeX RDF	Volume rendering, Non-photorealistic rendering, Texture synthesis, Medical visualization
23	Vivek Kwatra, Irfan A. Essa, Aaron F. Bobick, Nipun Kwatra	Texture optimization for example-based synthesis.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	texture animation, image-based rendering, texture synthesis, flow visualization, energy minimization
23	Chia-Jui Hsu, Shuvra S. Bhattacharyya	Software Synthesis from the Dataflow Interchange Format.	SCOPES	2005	DBLP DOI BibTeX RDF	DIF, dataflow interchange format, software synthesis
23	Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.	SBCCI	2005	DBLP DOI BibTeX RDF	burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent
23	Cheng-Yuan Lin, Tzu-Ying Lin, Jyh-Shing Roger Jang	A corpus-based singing voice synthesis system for mandarin Chinese.	ACM Multimedia	2005	DBLP DOI BibTeX RDF	corpus design, singing voice synthesis, dynamic programming
23	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	performance modeling, circuit sizing, analog synthesis
23	Bin Wang 0021, Wenping Wang, Huaiping Yang, Jia-Guang Sun 0001	Efficient Example-Based Painting and Synthesis of 2D Directional Texture.	IEEE Trans. Vis. Comput. Graph.	2004	DBLP DOI BibTeX RDF	example-based painting, painting style, artistic filter, Gaussian pyramid, directional texture, simulation, image segmentation, texture synthesis, nonphotorealistic rendering, painting systems, Digital painting
23	Chang-Hsing Wu, Yueh-Yi Lai, Wen-Kai Tai	A hybrid-based texture synthesis approach.	Vis. Comput.	2004	DBLP DOI BibTeX RDF	Patch-based sampling, Image processing, Texture synthesis
23	Andrew Nealen, Marc Alexa	Fast and High Quality Overlap Repair for Patch-Based Texture Synthesis.	Computer Graphics International	2004	DBLP DOI BibTeX RDF	Patch-based Texture Synthesis, k-coherence search, Principal Component Analysis
23	Jiali Cui, Yunhong Wang, Junzhou Huang, Tieniu Tan, Zhenan Sun	An Iris Image Synthesis Method Based on PCA and Super-Resolution.	ICPR (4)	2004	DBLP DOI BibTeX RDF	iris image synthesis, PCA, Biometrics, super-resolution, iris recognition
23	Raimundo S. Barreto, Marília Neves, Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Eduardo Tavares, Ricardo Massa Ferreira Lima	A formal software synthesis approach for embedded hard real-time systems.	SBCCI	2004	DBLP DOI BibTeX RDF	embedded hard real-time systems, hardware/software codesign methodologies, software synthesis
23	Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
23	Haoxing Ren, David Zhigang Pan, David S. Kung 0001	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
23	Renqiu Huang, Ranga Vemuri	Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF	critical net, performance, placement, Behavioral synthesis, macro
23	Sebastián Uchitel, Robert Chatley, Jeff Kramer, Jeff Magee	System architecture: the context for scenario-based model synthesis.	SIGSOFT FSE	2004	DBLP DOI BibTeX RDF	architecture, synthesis, generalisation, MSCs
23	Hemangee K. Kapoor, Mark B. Josephs	Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.	DAC	2004	DBLP DOI BibTeX RDF	asynchronous logic synthesis, delay-insensitive decomposition
23	Raúl Monroy	Predicate Synthesis for Correcting Faulty Conjectures: The Proof Planning Paradigm.	Autom. Softw. Eng.	2003	DBLP DOI BibTeX RDF	faulty specifications, program synthesis/transformation, abduction, proof planning
23	Michael A. Riepe, Karem A. Sakallah	Transistor placement for noncomplementary digital VLSI cell synthesis.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Cell Synthesis, Euler graphs, noncomplementary circuits, sequence pair optimization, transistor chaining, transistor placement, digital circuits, benchmark circuits
23	Viktor K. Sabelfeld, Kai Kapp	Numeric Types in Formal Synthesis.	Ershov Memorial Conference	2003	DBLP DOI BibTeX RDF	correct hardware synthesis, formal specification, higher-order logic, theorem prover, arithmetic operations
23	Marc Boyer, Mihaela Sighireanu	Synthesis and Verification of Constraints in the PGM Protocol.	FME	2003	DBLP DOI BibTeX RDF	PGM protocol, real-time multicast protocol, finite and timed model-checking, parameterized verification, constraint synthesis
23	Éric Badouel, Benoît Caillaud, Philippe Darondeau	Distributing Finite Automata Through Petri Net Synthesis.	Formal Aspects Comput.	2002	DBLP DOI BibTeX RDF	General Petri nets, Distribution, Synthesis, Finite automata, Regions
23	Ashley Gadd, Sidney S. Fels	MetaMuse: a novel control metaphor for granular synthesis.	CHI Extended Abstracts	2002	DBLP DOI BibTeX RDF	prop-based interface, metaphors, computer music, granular synthesis
23	Ruchir Puri, David S. Kung 0001, Anthony D. Drumm	Fast and accurate wire delay estimation for physical synthesis of large ASICs.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	placement driven synthesis, wire delay, estimation, integrated circuit design
23	Geun Rae Cho, Tom Chen 0001	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.	ISQED	2002	DBLP DOI BibTeX RDF	Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
23	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
23	J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir	A Heuristic for Clock Selection in High-Level Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	clock selection, heuristics, high-level synthesis, design space exploration, graph structure
23	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
23	Trandafir Moisa, Dan Ontanu, Adrian-Horia Dediu	Speech Synthesis Using Neural Networks Trained by an Evolutionary Algorithm.	International Conference on Computational Science (2)	2001	DBLP DOI BibTeX RDF	Supervised Training, Neural Networks, Evolutionary Algorithms, Speech Synthesis
23	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha	Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	concurrent error detection, Behavioral synthesis, fault security, fault-tolerant microarchitectures
23	Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni	Hardware/software synthesis of formal specifications in codesign of embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	hardware and software synthesis, embedded system, codesign
23	Andrew Stone, Elias S. Manolakos	Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.	ASAP	2000	DBLP DOI BibTeX RDF	Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
23	Tammy Riklin-Raviv, Amnon Shashua	The Quotient Image: Class Based Recognition and Synthesis under Varying Illumination Conditions.	CVPR	1999	DBLP DOI BibTeX RDF	Class-Based, Recognition, Illumination, Image-Synthesis
23	Frank F. Hsu, Janak H. Patel	High-Level Controllability and Observability Analysis for Test Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controllability, observability, high-level test synthesis, behavioral modification
23	Frank Vahid, Thuy Dm Le, Yu-Chin Hsu	Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	system-level design, behavioral synthesis, functional partitioning
23	Unni Narayanan, C. L. Liu 0001	Low power logic synthesis for XOR based circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	vlsi cad logic synthesis, XOR logic, Fixed Polarity Reed Muller Forms, Huffman Algorithm, low power design
23	Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith	Application-driven synthesis of core-based systems.	ICCAD	1997	DBLP DOI BibTeX RDF	application-specific system-level synthesis, system modeling and performance evaluation, cache line coloring
23	Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	Trace driven logic synthesis - application to power minimization.	ICCAD	1997	DBLP DOI BibTeX RDF	Low Power, Logic Synthesis
23	X. Wendling, H. Chauvet, Lionel Revéret, Raphaël Rochet, Régis Leveugle	Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.	DFT	1997	DBLP DOI BibTeX RDF	RTL synthesis, dependable VLSI circuits, fault tolerance, fault detection, CAD tools
23	Jason Cong, Yuzheng Ding	Combinational logic synthesis for LUT based field programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
23	David R. Smith	Hardware Synthesis From Encapsulated Verilog Modules.	ASAP	1996	DBLP DOI BibTeX RDF	encapsulated Verilog modules, Verilog writing style, code complexity, automatic inference of control, low level simulation, computational complexity, logic design, inference mechanisms, hardware description languages, hardware synthesis, control points, clock cycle
23	Stephen Docy, Inki Hong, Miodrag Potkonjak	Throughput Optimization in Disk-Based Real-Time Application Specific Systems.	ISSS	1996	DBLP DOI BibTeX RDF	Massive Storage, Hard Real-Time, System-Level Synthesis
23	Mark D. Aagaard, Miriam Leeser	Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	weak division, theorem proving, logic synthesis, Software verification, hardware verification
23	Pai H. Chou, Ross B. Ortega, Gaetano Borriello	Interface co-synthesis techniques for embedded systems.	ICCAD	1995	DBLP DOI BibTeX RDF	design space exploration tools, glue logic, real-time systems, embedded systems, CAD, synthesis, computer interfaces, hardware/software interfaces, design cycle
23	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
23	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits