Search results for "transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Yehya H. Ghallab, Wael M. Badawy, Karan V. I. S. Kaler	A Novel PH Sensor Using Differential ISFET Current Mode Read-Out Circuit.	ICMENS	2003	DBLP DOI BibTeX RDF	Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits
12	Amit Agarwal 0001, Kaushik Roy 0001	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
12	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Automatic analog layout retargeting for new processes and device sizes.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
12	Jofre Pallares, Justo Sabadell, Francisco Serra-Graells	Modeling all-MOS log filters and its application to Sigma-Delta modulators.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Fernando Muñoz 0001, Antonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado, Meghraj Kachare, Bernardo Palomo Vázquez	Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Yasuaki Inoue, Saeko Kusanobu, Kiyotaka Yamamura, M. Ando	An effective initial solution algorithm for globally convergent homotopy methods.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
12	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
12	Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong, Xin Guo 0002, Michael I. Ferguson, Adrian Stoica	Experimental Results in Evolutionary Fault-Recovery for Field Programmable.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
12	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Chandramouli Gopalakrishnan, Srinivas Katkoori	Resource Allocation and Binding Approach for Low Leakage Power.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
12	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
12	Swarup Bhunia, Hai Li, Kaushik Roy 0001	A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
12	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark	Managing leakage for transient data: decay and quasi-static 4T memory cells.	ISLPED	2002	DBLP DOI BibTeX RDF	4T, decay, memory cell, quasi-static, transient data, leakage power
12	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
12	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
12	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
12	Adrian Stoica, Ricardo Salem Zebulum, Michael I. Ferguson, Didier Keymeulen, Vu Duong	Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
12	Kuo-Hsing Cheng, Shun-Wen Cheng	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant
12	Sergei P. Skorobogatov, Ross J. Anderson	Optical Fault Induction Attacks.	CHES	2002	DBLP DOI BibTeX RDF
12	Pradip Mandal, V. Visvanathan	CMOS op-amp sizing using a geometric programming formulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin	Delay and current estimation in a CMOS inverter with an RC load.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Kenneth L. Shepard, Dae-Jin Kim	Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
12	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
12	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Hanspeter Schmid	The current-feedback OTA.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
12	Huiting Chen, Frank Whiteside, Randall L. Geiger	Current mirror circuit with accurate mirror gain for low beta transistors.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
12	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang	A 1.25 GHz 32-bit tree-structured carry lookahead adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng	HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.	ISQED	2001	DBLP DOI BibTeX RDF
12	Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel	A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
12	Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann	Design Of Provably Correct Storage Arrays.	VLSI Design	2001	DBLP DOI BibTeX RDF
12	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins	Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Cecilia Metra, Michele Favalli, Bruno Riccò	Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults
12	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
12	Tirdad Sowlati, Sifen Luo	Bias boosting technique for a 1.9GHz class AB RF amplifier.	ISLPED	2000	DBLP DOI BibTeX RDF
12	Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano	LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator.	ISQED	2000	DBLP DOI BibTeX RDF
12	Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami	GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.	ISQED	2000	DBLP DOI BibTeX RDF	Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI
12	Kamran Eshraghian	Deep Submicron USLI Design Paradigm: Who is Writing the Future?	ISQED	2000	DBLP DOI BibTeX RDF
12	Alexander Chatzigeorgiou, Spiridon Nikolaidis 0001, Ioannis Tsoukalas	A modeling technique for CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao	Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries
12	Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang	An Analytical Delay Model for SRAM-Based FPGA Interconnections.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	Rung-Bin Lin, Jinq-Chang Chen	Low Power CMOS Off-Chip Drivers with Slew-rate Difference.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	D. Guillet, K. Mourgues, R. Rogel, H. Lhermite, Olivier Bonnaud	Student Realization in Cleanroom of Silicon-Germanium Thin Film Transistors.	MSE	1999	DBLP DOI BibTeX RDF
12	Serkan Askar, Maciej J. Ciesielski	Analytical approach to custom datapath design.	ICCAD	1999	DBLP DOI BibTeX RDF
12	Robert W. Brodersen	System-on-a-Chip VLSI - Is It Finally Really Here?	ARVLSI	1999	DBLP DOI BibTeX RDF
12	Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman	Logic Verification of Very Large Circuits Using Shark.	VLSI Design	1999	DBLP DOI BibTeX RDF
12	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu	JiffyTune: circuit optimization using time-domain sensitivities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
12	Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell	Testing for Floating Gates Defects in CMOS Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
12	Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz	Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.	DFT	1998	DBLP DOI BibTeX RDF	CMOS Defect Modeling, Defect Analysis
12	Gregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain	Full-Chip Verification Methods for DSM Power Distribution Systems.	DAC	1998	DBLP DOI BibTeX RDF	reliability, PowerPC, IR-drop, power distribution network
12	David Zhang 0001, Mohamed I. Elmasry	VLSI compressor design with applications to digital neural networks.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
12	Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos	Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes.	DFT	1997	DBLP DOI BibTeX RDF	SelfChecking circuits, totally selfchecking circuits, moutofn codes, fault tolerance
12	Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac	Unified complete MOSFET model for analysis of digital and analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Uwe Gläser, Heinrich Theodor Vierhaus	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Marco Saraniti, Achim Rein, Günther Zandler, Peter Vogl, Paolo Lugli	An efficient multigrid Poisson solver for device simulations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Narayan R. Aluru, Kincho H. Law, Robert W. Dutton	Simulation of the hydrodynamic device model on distributed memory parallel computers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	Fault macromodeling and a testing strategy for opamps.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults
12	Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins	A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	fault modeling, physical defects, gate oxide short
12	Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer	An integrated system for assigning signal flow directions to CMOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Timothy Kam, P. A. Subrahmanyam	Comparing layouts with HDL models: a formal verification technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Siyad C. Ma, Edward J. McCluskey	Open faults in BiCMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Elizabeth J. Brauer, Sung-Mo Kang	An algorithm for functional verification of digital ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Mitiko Miura-Mattausch	Analytical MOSFET model for quarter micron technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Eric A. Vittoz	Analog VLSI signal processing: Why, where, and how?	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
12	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	A comprehensive fault macromodel for opamps.	ICCAD	1994	DBLP DOI BibTeX RDF
12	Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac	Unified complete MOSFET model for analysis of digital and analog circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
12	Syed A. Aftab, M. A. Styblinski	A new efficient approach to statistical delay modeling of CMOS digital combinational circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
12	Mark G. Graham, John J. Paulos	Interpolation of MOSFET table data in width, length, and temperature.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Nils Hedenstierna, Kjell O. Jeppson	Comments on 'A module generator for optimized CMOS buffers'.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Denis Martin, Nicholas C. Rumin	Delay prediction from resistance-capacitance models of general MOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Michel Renovell, Gaston Cambon	Electrical analysis and modeling of floating-gate fault.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
12	J. H. Smith, Kenneth M. Steer, Timothy F. Miller, Stephen J. Fonash	Numerical modeling of two-dimensional device structures using Brandt's multilevel acceleration scheme: application to Poisson's equation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
12	Sreejit Chakravarty, S. S. Ravi	Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
12	David Marple, Michiel Smulders, Henk Hegen	Tailor: a layout system based on trapezoidal corner stitching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
12	Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham	Hierarchical multi-level fault simulation of large systems.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	multilevel simulation, testing, fault simulation, VLSI design
12	R. Burgess, C. Wouters	PARAGON: a new package for gate matrix layout synthesis.	EURO-DAC	1990	DBLP DOI BibTeX RDF	cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design
12	David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham	Derivation of signal flow for switch-level simulation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
12	Veronika Eisele, Bernhard Hoppe, Oliver Kiehl	Transmission gate delay models for circuit optimization.	EURO-DAC	1990	DBLP DOI BibTeX RDF
12	Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu	LiB: A Cell Layout Generator.	DAC	1990	DBLP DOI BibTeX RDF
12	Hal R. Yeager, Robert W. Dutton	Improvement in norm-reducing Newton methods for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
12	Charles J. Poirier	Excellerator: custom CMOS leaf cell layout generator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
12	Richard W. Linderman, Paul C. Rossbach, David M. Gallagher	Design and application of an optimizing XROM silicon compiler.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
12	Chung-Ping Wan, Bing J. Sheu	Temperature dependence modeling for MOS VLSI circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
12	Michael Rumsey, John Sackett	An ASIC Methodology for Mixed Analog-Digital Simulation.	DAC	1989	DBLP DOI BibTeX RDF
12	Patrick Odent, Luc J. M. Claesen, Hugo De Man	Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator.	DAC	1989	DBLP DOI BibTeX RDF
12	Genhong Ruan, Jirí Vlach, James A. Barby	Current-limited switch-level timing simulator for MOS logic networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
12	Shiuh-Wuu Lee, Robert C. Rennick	A compact IGFET model-ASIM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
12	Michael H. Arnold, Walter S. Scott	An Interactive Maze Router with Hints.	DAC	1988	DBLP BibTeX RDF
12	James J. Cherry	Pearl: A CMOS Timing Analyzer.	DAC	1988	DBLP BibTeX RDF
12	Ching-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni	A Rule-Based Circuit Representation for Automated CMOS Design and Verification.	DAC	1987	DBLP DOI BibTeX RDF
12	Peter Odryna, Kevin Nazareth, Carl Christensen	A workstation-mixed model circuit simulator.	DAC	1986	DBLP DOI BibTeX RDF
12	Randal E. Bryant, Michael Dd. Schuster	Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator.	DAC	1985	DBLP DOI BibTeX RDF
12	Ke Li, Surojit Sen	A Fast and Accurate GaN Power Transistor Model and Its Application for Electric Vehicle.	IEEE Trans. Veh. Technol.	2024	DBLP DOI BibTeX RDF
12	Seyed Mojtaba Sadati Faramarzi, Bin Luo, Jef Poortmans, Jan Genoe, Kris Myny	Thin-Film Transistor-Based Sensor Interface Circuits Enabling Distributed Local In-Module Solar Cell Temperature Monitoring.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF