Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
12 | Yehya H. Ghallab, Wael M. Badawy, Karan V. I. S. Kaler |
A Novel PH Sensor Using Differential ISFET Current Mode Read-Out Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2003 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2003), 20-23 July 2003, Banff, Alberta, Canada, pp. 255-, 2003, IEEE Computer Society, 0-7695-1947-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits |
12 | Amit Agarwal 0001, Kaushik Roy 0001 |
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 18-21, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
diode, low leakage cache, SRAM, gate leakage |
12 | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi |
Automatic analog layout retargeting for new processes and device sizes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 704-707, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Jofre Pallares, Justo Sabadell, Francisco Serra-Graells |
Modeling all-MOS log filters and its application to Sigma-Delta modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 117-120, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Fernando Muñoz 0001, Antonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado, Meghraj Kachare, Bernardo Palomo Vázquez |
Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 817-820, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Yasuaki Inoue, Saeko Kusanobu, Kiyotaka Yamamura, M. Ando |
An effective initial solution algorithm for globally convergent homotopy methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 196-199, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
Statistical modeling of gate-delay variation with consideration of intra-gate variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 513-516, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong, Xin Guo 0002, Michael I. Ferguson, Adrian Stoica |
Experimental Results in Evolutionary Fault-Recovery for Field Programmable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 192-198, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Rajiv V. Joshi, Kaushik Roy 0001 |
Design of Deep Sub-Micron CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 15-16, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Resource Allocation and Binding Approach for Low Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 297-302, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001 |
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 169-174, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
doping profiles, leakage, tunneling, threshold voltage |
12 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 806-823, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Swarup Bhunia, Hai Li, Kaushik Roy 0001 |
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 157-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Hiran Tennakoon, Carl Sechen |
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 395-402, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark |
Managing leakage for transient data: decay and quasi-static 4T memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 52-55, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
4T, decay, memory cell, quasi-static, transient data, leakage power |
12 | Bill Pontikakis, Mohamed Nekili |
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 101-104, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano |
A self-checking cell logic block for fault tolerant FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 477-480, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 275-280, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Adrian Stoica, Ricardo Salem Zebulum, Michael I. Ferguson, Didier Keymeulen, Vu Duong |
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 15-18 July 2002, Alexandria, VA, USA, pp. 67-74, 2002, IEEE Computer Society, 0-7695-1718-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Kuo-Hsing Cheng, Shun-Wen Cheng |
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 155-159, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant |
12 | Sergei P. Skorobogatov, Ross J. Anderson |
Optical Fault Induction Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 2-12, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Pradip Mandal, V. Visvanathan |
CMOS op-amp sizing using a geometric programming formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 22-38, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin |
Delay and current estimation in a CMOS inverter with an RC load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 80-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Kenneth L. Shepard, Dae-Jin Kim |
Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7), pp. 888-901, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Mike Sheng, Jonathan Rose |
Mixing buffers and pass transistors in FPGA routing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 75-84, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Paul Kartschoke, Stephen F. Geissler |
Timing Driven Wiring on an Advanced Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 408-413, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou |
A high-performance low-power static differential double edge-triggered flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 802-805, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Hanspeter Schmid |
The current-feedback OTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 655-658, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Huiting Chen, Frank Whiteside, Randall L. Geiger |
Current mirror circuit with accurate mirror gain for low beta transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 536-539, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis |
The circuit design of multiple-valued logic voltage-mode adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 162-165, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang |
A 1.25 GHz 32-bit tree-structured carry lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 80-83, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng |
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 307-312, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel |
A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 12-14 July 2001, Long Beach, CA, USA, pp. 172-175, 2001, IEEE Computer Society, 0-7695-1180-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann |
Design Of Provably Correct Storage Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 196-, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins |
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(6), pp. 717-723, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 560-574, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults |
12 | Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken |
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 73-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing |
12 | Tirdad Sowlati, Sifen Luo |
Bias boosting technique for a 1.9GHz class AB RF amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 284-288, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano |
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 129-136, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami |
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 73-80, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI |
12 | Kamran Eshraghian |
Deep Submicron USLI Design Paradigm: Who is Writing the Future? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 213-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Alexander Chatzigeorgiou, Spiridon Nikolaidis 0001, Ioannis Tsoukalas |
A modeling technique for CMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 557-575, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao |
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 25(5), pp. 619-632, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries |
12 | Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang |
An Analytical Delay Model for SRAM-Based FPGA Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 101-104, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Rung-Bin Lin, Jinq-Chang Chen |
Low Power CMOS Off-Chip Drivers with Slew-rate Difference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 169-172, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | D. Guillet, K. Mourgues, R. Rogel, H. Lhermite, Olivier Bonnaud |
Student Realization in Cleanroom of Silicon-Germanium Thin Film Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 69-70, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Serkan Askar, Maciej J. Ciesielski |
Analytical approach to custom datapath design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 98-101, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Robert W. Brodersen |
System-on-a-Chip VLSI - Is It Finally Really Here? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 154-, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman |
Logic Verification of Very Large Circuits Using Shark. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 310-317, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu |
JiffyTune: circuit optimization using time-domain sensitivities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12), pp. 1292-1309, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
12 | Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell |
Testing for Floating Gates Defects in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 228-236, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
12 | Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz |
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 84-92, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
CMOS Defect Modeling, Defect Analysis |
12 | Gregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain |
Full-Chip Verification Methods for DSM Power Distribution Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 744-749, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reliability, PowerPC, IR-drop, power distribution network |
12 | David Zhang 0001, Mohamed I. Elmasry |
VLSI compressor design with applications to digital neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 230-233, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
12 | Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos |
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 128-136, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SelfChecking circuits, totally selfchecking circuits, moutofn codes, fault tolerance |
12 | Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac |
Unified complete MOSFET model for analysis of digital and analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 1-7, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
12 | Uwe Gläser, Heinrich Theodor Vierhaus |
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 410-423, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
12 | Marco Saraniti, Achim Rein, Günther Zandler, Peter Vogl, Paolo Lugli |
An efficient multigrid Poisson solver for device simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 141-150, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
12 | Narayan R. Aluru, Kincho H. Law, Robert W. Dutton |
Simulation of the hydrodynamic device model on distributed memory parallel computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1029-1047, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
12 | Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001 |
Fault macromodeling and a testing strategy for opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 225-235, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults |
12 | Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins |
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 229-239, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault modeling, physical defects, gate oxide short |
12 | Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer |
An integrated system for assigning signal flow directions to CMOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1445-1458, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
12 | Timothy Kam, P. A. Subrahmanyam |
Comparing layouts with HDL models: a formal verification technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4), pp. 503-509, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
12 | Siyad C. Ma, Edward J. McCluskey |
Open faults in BiCMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 567-575, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
12 | Elizabeth J. Brauer, Sung-Mo Kang |
An algorithm for functional verification of digital ECL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1546-1556, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
12 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 625-637, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Mitiko Miura-Mattausch |
Analytical MOSFET model for quarter micron technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 610-615, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Eric A. Vittoz |
Analog VLSI signal processing: Why, where, and how? ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(1), pp. 27-44, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001 |
A comprehensive fault macromodel for opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 344-348, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac |
Unified complete MOSFET model for analysis of digital and analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 264-267, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Syed A. Aftab, M. A. Styblinski |
A new efficient approach to statistical delay modeling of CMOS digital combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 200-203, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Mark G. Graham, John J. Paulos |
Interpolation of MOSFET table data in width, length, and temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1880-1884, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
12 | Nils Hedenstierna, Kjell O. Jeppson |
Comments on 'A module generator for optimized CMOS buffers'. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 180-181, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
12 | Denis Martin, Nicholas C. Rumin |
Delay prediction from resistance-capacitance models of general MOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 997-1003, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
12 | Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj |
Switch-level timing simulation of bipolar ECL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 516-530, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
12 | Michel Renovell, Gaston Cambon |
Electrical analysis and modeling of floating-gate fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11), pp. 1450-1458, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
12 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 677-682, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
12 | J. H. Smith, Kenneth M. Steer, Timothy F. Miller, Stephen J. Fonash |
Numerical modeling of two-dimensional device structures using Brandt's multilevel acceleration scheme: application to Poisson's equation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6), pp. 822-824, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
12 | Sreejit Chakravarty, S. S. Ravi |
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 329-331, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
12 | David Marple, Michiel Smulders, Henk Hegen |
Tailor: a layout system based on trapezoidal corner stitching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1), pp. 66-90, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
12 | Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham |
Hierarchical multi-level fault simulation of large systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(2), pp. 139-149, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
multilevel simulation, testing, fault simulation, VLSI design |
12 | R. Burgess, C. Wouters |
PARAGON: a new package for gate matrix layout synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 129-134, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design |
12 | David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham |
Derivation of signal flow for switch-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 301-305, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
12 | Veronika Eisele, Bernhard Hoppe, Oliver Kiehl |
Transmission gate delay models for circuit optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 558-562, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
12 | Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu |
LiB: A Cell Layout Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 474-479, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
12 | Hal R. Yeager, Robert W. Dutton |
Improvement in norm-reducing Newton methods for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(5), pp. 538-546, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Charles J. Poirier |
Excellerator: custom CMOS leaf cell layout generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7), pp. 744-755, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Richard W. Linderman, Paul C. Rossbach, David M. Gallagher |
Design and application of an optimizing XROM silicon compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), pp. 1267-1275, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Chung-Ping Wan, Bing J. Sheu |
Temperature dependence modeling for MOS VLSI circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10), pp. 1065-1073, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Michael Rumsey, John Sackett |
An ASIC Methodology for Mixed Analog-Digital Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 618-621, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Patrick Odent, Luc J. M. Claesen, Hugo De Man |
Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 25-30, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
12 | Genhong Ruan, Jirí Vlach, James A. Barby |
Current-limited switch-level timing simulator for MOS logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6), pp. 659-667, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
12 | Shiuh-Wuu Lee, Robert C. Rennick |
A compact IGFET model-ASIM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 952-975, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
12 | Michael H. Arnold, Walter S. Scott |
An Interactive Maze Router with Hints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 672-676, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
12 | James J. Cherry |
Pearl: A CMOS Timing Analyzer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 148-153, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
12 | Ching-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni |
A Rule-Based Circuit Representation for Automated CMOS Design and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 786-792, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
12 | Peter Odryna, Kevin Nazareth, Carl Christensen |
A workstation-mixed model circuit simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 186-192, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
12 | Randal E. Bryant, Michael Dd. Schuster |
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 715-719, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
12 | Ke Li, Surojit Sen |
A Fast and Accurate GaN Power Transistor Model and Its Application for Electric Vehicle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 73(4), pp. 4541-4553, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Seyed Mojtaba Sadati Faramarzi, Bin Luo, Jef Poortmans, Jan Genoe, Kris Myny |
Thin-Film Transistor-Based Sensor Interface Circuits Enabling Distributed Local In-Module Solar Cell Temperature Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 307-315, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|