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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10002 occurrences of 3019 keywords
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Results
Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Irith Pomeranz, Sudhakar M. Reddy |
On test generation by input cube avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 522-527, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Bernhard Fechner, Andre Osterloh |
Transient Fault Detection in State-Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DepCoS-RELCOMEX ![In: 2007 International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX 2007), June 14-16, 2007, Szklarska Poreba, Poland, pp. 99-106, 2007, IEEE Computer Society, 0-7695-2850-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy 0001 |
Fine-Grained Redundancy in Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 317-321, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Ranjani Sridharan, Rabi N. Mahapatra |
Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 83-88, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Danhua Shao, Sarfraz Khurshid, Dewayne E. Perry |
Evaluation of Semantic Interference Detection in Parallel Changes: an Exploratory Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 23rd IEEE International Conference on Software Maintenance (ICSM 2007), October 2-5, 2007, Paris, France, pp. 74-83, 2007, IEEE Computer Society, 978-1-4244-1256-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | María Engracia Gómez, Nils Agne Nordbotten, José Flich, Pedro López 0001, Antonio Robles, José Duato, Tor Skeie, Olav Lysne |
A Routing Methodology for Achieving Fault Tolerance in Direct Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 400-415, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
bubble flow control, Fault tolerance, adaptive routing, virtual channels, direct networks |
19 | Robert Schaefer |
A critical programmer searches for professionalism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 31(4), pp. 1-17, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Soyoung Hwang, Yunju Baek |
Fault Tolerant Time Synchronization for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 480-493, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
A dynamic test compaction procedure for high-quality path delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 348-353, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Damien Masson, Serge Midonnet |
Fault tolerance with real-time Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Juan Li, Gong-You Tang, Hong-Wei Gao |
Fault Detection and Self-Restore Control for Linear Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (1) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 873-878, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Pan Zhongliang, Chen Ling, Liu Shouqiang, Guangzhao Zhang |
Neural Network Approach for Multiple Fault Test of Digital Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (3) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 24-29, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Wenjun Li, Yuanchun Li |
A Method of Abrupt Sensor Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (1) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 856-861, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Frank Olaf Sem-Jacobsen, Tor Skeie, Olav Lysne, José Duato |
Dynamic Fault Tolerance with Misrouting in Fat Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2006 International Conference on Parallel Processing (ICPP 2006), 14-18 August 2006, Columbus, Ohio, USA, pp. 33-44, 2006, IEEE Computer Society, 0-7695-2636-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Toshinori Sato, Akihiro Chiyonobu |
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 369-370, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Shiyi Xu |
A New Approach to Improving the Test Effectiveness in Software Testing Using Fault Collapsing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 73-80, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Software Testing, Mutation Testing, Testing Effectiveness, Fault Equivalence, Fault Dominance |
19 | N. Venkateswaran 0002, S. Balaji, V. Sridhar |
Fault tolerant bus architecture for deep submicron based processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(1), pp. 148-155, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
deep submicron technology, fault tolerance, interconnect, electromigration |
19 | Lee-Juan Fan, Chang-Biau Yang, Shyue-Horng Shiau |
Routing Algorithms on the Bus-Based Hypercube Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(4), pp. 335-348, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Multiple-bus network, fault tolerance, hypercube, routing algorithm, diameter |
19 | Jerker Hammarberg, Simin Nadjm-Tehrani |
Formal verification of fault tolerance in safety-critical reconfigurable modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(3), pp. 268-279, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fault tolerance, FPGA, Formal verification, Safety analysis, Esterel |
19 | Fred A. Bower, Sule Ozev, Daniel J. Sorin |
Autonomic Microprocessor Execution via Self-Repairing Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 2(4), pp. 297-310, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Logic design reliability and testing, microprocessors and microcomputers |
19 | Elizabeth Latronico, Philip Koopman |
Design Time Reliability Analysis of Distributed Fault Tolerance Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 486-495, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mohammad Tanvir Huda, Heinz W. Schmidt, Ian D. Peake |
An Agent Oriented Proactive Fault-Tolerant Framework for Grid Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
e-Science ![In: First International Conference on e-Science and Grid Technologies (e-Science 2005), 5-8 December 2005, Melbourne, Australia, pp. 304-311, 2005, IEEE Computer Society, 0-7695-2448-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy |
Fault Diagnosis and Fault Model Aliasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 206-211, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar 0001 |
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 88-93, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sandip Bapat, Vinodkrishnan Kulathumani, Anish Arora |
Analyzing the Yield of ExScal, a Large-Scale Wireless Sensor Network Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: 13th IEEE International Conference on Network Protocols (ICNP 2005), 6-9 November 2005, Boston, MA, USA, pp. 53-62, 2005, IEEE Computer Society, 0-7695-2437-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Paulo Sousa 0001, Nuno Ferreira Neves, Paulo Veríssimo |
Resilient State Machine Replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China, pp. 305-309, 2005, IEEE Computer Society, 0-7695-2492-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Reza Asgary, Karim Mohammadi |
Analog Fault Detection Using a Neuro Fuzzy Pattern Recognition Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (2) ![In: Artificial Neural Networks: Formal Models and Their Applications - ICANN 2005, 15th International Conference, Warsaw, Poland, September 11-15, 2005, Proceedings, Part II, pp. 893-898, 2005, Springer, 3-540-28755-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Ching-Tien Ho, Larry J. Stockmeyer |
A New Approach to Fault-Tolerant Wormhole Routing for Mesh-Connected Parallel Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(4), pp. 427-439, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance evaluation, parallel computing, wormhole routing, mesh networks, Fault-tolerant routing |
19 | Jan Lunze, Jochen Schröder |
Sensor and actuator fault diagnosis of systems with discrete inputs and outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part B ![In: IEEE Trans. Syst. Man Cybern. Part B 34(2), pp. 1096-1107, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Lars-Ola Damm, Lars Lundberg, Claes Wohlin |
Determining the Improvement Potential of a Software Development Organization Through Fault Analysis: A Method and a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSPI ![In: Software Process Improvement, 11th European Conference, EuroSPI 2004, Trondheim, Norway, November 10-12, 2004, Proceedings, pp. 138-149, 2004, Springer, 3-540-23725-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Nikhil Joshi, Kaijie Wu 0001, Ramesh Karri |
Concurrent Error Detection Schemes for Involution Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 400-412, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Involutional ciphers, KHAZAD, Fault Tolerance, Concurrent Error Detection (CED) |
19 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi, Nohpill Park |
Maximal diagnosis of interconnects of random access memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 52(4), pp. 423-434, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri |
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(4), pp. 492-505, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
parity codes, fault tolerance, fault detection, Advanced Encryption Standard, AES |
19 | João Durães, Henrique Madeira |
Definition of Software Fault Emulation Operators: A Field Data Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 105-114, 2003, IEEE Computer Society, 0-7695-1952-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Saravanan Padmanaban, Spyros Tragoudas |
Non-Enumerative Path Delay Fault Diagnosis . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10322-10327, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Yunzhan Gong, Wanli Xu, Xiaowei Li 0001 |
An Expression's Single Fault Model and the Testing Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 110-115, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Michael R. Lyu, Zubin Huang, Sam K. S. Sze, Xia Cai |
An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 14th International Symposium on Software Reliability Engineering (ISSRE 2003), 17-20 November 2003, Denver, CO, USA, pp. 119-132, 2003, IEEE Computer Society, 0-7695-2007-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
data flow coverage testing, empirical study, software fault tolerance, mutation testing |
19 | Vinícius P. Correia, Marcelo Lubaszewski, André Inácio Reis |
SIFU! - A Didactic Stuck-at Fault Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 93-94, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Pedro Yuste, Juan-Carlos Ruiz-Garcia, Lenin Lemus, Pedro J. Gil |
Non-intrusive Software-Implemented Fault Injection in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: Dependable Computing, First Latin-American Symposium, LADC 2003, Sao Paulo, Brazil, October 21-24, 2003, Proceedings, pp. 23-38, 2003, Springer, 3-540-20224-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray |
Low-Cost On-Line Fault Detection Using Control Flow Assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 137-143, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Allen P. Nikora, John C. Munson |
Understanding the Nature of Software Evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 19th International Conference on Software Maintenance (ICSM 2003), The Architecture of Existing Systems, 22-26 September 2003, Amsterdam, The Netherlands, pp. 83-, 2003, IEEE Computer Society, 0-7695-1905-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Der-Cheng Huang, Wen-Ben Jone |
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5), pp. 617-628, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 55-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure |
19 | Scott F. Kaplan, Lyle A. McGeoch, Megan F. Cole |
Adaptive caching for demand prepaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSP/ISMM ![In: Proceedings of The Workshop on Memory Systems Performance (MSP 2002), June 16, 2002 and The International Symposium on Memory Management (ISMM 2002), June 20-21, 2002, Berlin, Germany, pp. 221-232, 2002, ACM, 1-58113-539-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
block paging, prepaging, clustering, adaptive caching |
19 | Giuliano Antoniol, Lionel C. Briand, Massimiliano Di Penta, Yvan Labiche |
A Case Study Using the Round-Trip Strategy for State-Based Class Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 12-15 November 2002, Annapolis, MD, USA, pp. 269-279, 2002, IEEE Computer Society, 0-7695-1763-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Seung Ma, Yong Rae Kwon, Jeff Offutt |
Inter-Class Mutation Operators for Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 12-15 November 2002, Annapolis, MD, USA, pp. 352-366, 2002, IEEE Computer Society, 0-7695-1763-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Volkmar Sieh, Kerstin Buchacker |
UMLinux - A Versatile SWIFI Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-4, 4th European Dependable Computing Conference, Toulouse, France, October 23-25, 2002, Proceedings, pp. 159-171, 2002, Springer, 3-540-00012-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita |
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 83-89, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
Automatic generation and compaction of March tests for memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 845-857, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta 0001, Abhijit Chatterjee |
Path delay fault diagnosis in combinational circuits with implicitfault enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10), pp. 1226-1235, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
Fault Diagnosis for Linear Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(6), pp. 483-494, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
diagnosing evaluators, un-powered network, fault diagnosis, signal flow graph |
19 | Seo-Lim Park, Seung-Won Lee, In-Hwan Kim, Ki-Dong Chung |
Server Switching and Flow Control: Supporting Fault Tolerant Playout of Videos in a VoD System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, ICME 2001, August 22-25, 2001, Tokyo, Japan, 2001, IEEE Computer Society, 0-7695-1198-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Irith Pomeranz, Sudhakar M. Reddy |
On synchronizable circuits and their synchronizing sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9), pp. 1086-1092, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Jue Wu, Elizabeth M. Rudnick |
Bridge fault diagnosis using stuck-at fault simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4), pp. 489-495, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Jian Liu, Rafic Z. Makki, Ayman I. Kayssi |
Dynamic Power Supply Current Testing of CMOS SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 499-511, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
transient power supply current (i DDT), transient current sensor, disturb fault, CMOS SRAM |
19 | Ravishankar K. Iyer, Zbigniew Kalbarczyk, Mahesh Kalyanakrishnan |
Measurement-based Analysis of Networked System Availability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Performance Evaluation ![In: Performance Evaluation: Origins and Directions, pp. 161-199, 2000, Springer, 3-540-67193-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Laurence Goodby, Alex Orailoglu |
Test Quality and Fault Risk in Digital Filter Datapath BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 468-475, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Rostislav Caha, Petr Gregor |
Embedding Fibonacci Cubes into Hypercubes with Omega(2cn) Faulty Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2000, 25th International Symposium, MFCS 2000, Bratislava, Slovakia, August 28 - September 1, 2000, Proceedings, pp. 253-263, 2000, Springer, 3-540-67901-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Parag K. Lala, Alvernon Walker |
An On-Line Reconfigurable FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 275-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Hans Hansson, Christer Norström, Sasikumar Punnekkat |
Reliability Modelling of Time-Critical Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTRTFT ![In: Formal Techniques in Real-Time and Fault-Tolerant Systems, 6th International Symposium, FTRTFT 2000, Pune, India, September 20-22, 2000, Proceedings, pp. 94-105, 2000, Springer, 3-540-41055-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | László Kovács, Gábor Terstyánszky |
Boundary Region Sensitive Classification for the Counterpropagation Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (1) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 1, pp. 90-94, 2000, IEEE Computer Society, 0-7695-0619-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
neural networks, classification, fault diagnosis, uncertainty, learning algorithms |
19 | Timothy K. Tsai, Mei-Chen Hsueh, Hong Zhao, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
Stress-Based and Path-Based Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(11), pp. 1183-1201, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
stress-based, path-based, program flow, fault tolerance, dependability, Fault injection, workload |
19 | Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich |
Analog testing by characteristic observation inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1353-1368, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao |
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 25(5), pp. 619-632, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries |
19 | Ronald J. Hayne, Barry W. Johnson |
Behavioral Fault Modeling in a VHDL Synthesis Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 333-340, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Michel Cukier, Ramesh Chandra, David Henke, Jessica Pistole, William H. Sanders |
Fault Injection based on a Partial View of the Global State of a Distributed System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SRDS ![In: The Eighteenth Symposium on Reliable Distributed Systems, SRDS 1999, Lausanne, Switzerland, October 19-22, 1999, Proceedings, pp. 168-177, 1999, IEEE Computer Society, 0-7695-0290-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Adam A. Porter, Lawrence G. Votta |
Comparing Detection Methods For Software Requirements Inspections: A Replication Using Professional Subjects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Empir. Softw. Eng. ![In: Empir. Softw. Eng. 3(4), pp. 355-379, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
replication, inspection, controlled experiment |
19 | João Carreira, Henrique Madeira, João Gabriel Silva |
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 24(2), pp. 125-136, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
real time, Fault injection, dependability evaluation, RISC processors |
19 | Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee |
Functional Scan Chain Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 278-283, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion |
19 | Michael S. Hsiao, Srimat T. Chakradhar |
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 452-457, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Jian Liu, Rafic Z. Makki, Ayman I. Kayssi |
Dynamic Power Supply Current Testing of SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 348-353, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
A new framework for generating optimal March tests for memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 73-82, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Hyung Ki Lee, Dong Sam Ha |
HOPE: an efficient parallel fault simulator for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1048-1058, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
Functional test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 831-843, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Naotake Kamiura, Yutaka Hata, Kazuharu Yamato |
On Design of Fail-Safe Cellular Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 107-112, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fail-safe logic system, Binary Decision Diagram and switch cell, cellular array |
19 | Ghassan Al Hayek, Chantal Robach |
On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 337-342, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification |
19 | S. Crepaux-Motte, Mireille Jacomino, Rene David |
An algebraic method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 308-315, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method |
19 | Bethany Man-Yee Chan, Francis Y. L. Chin, Chung Keung Poon |
Optimal Simulation of Full Binary Trees on Faulty Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(3), pp. 269-286, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Cinzia Bernardeschi, Alessandro Fantechi, Luca Simoncini |
Formal Reasoning on Fault Coverage of Fault Tolerant Techniques: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-1, First European Dependable Computing Conference, Berlin, Germany, October 4-6, 1994, Proceedings, pp. 77-94, 1994, Springer, 3-540-58426-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana |
Faulty behavior of storage elements and its effects on sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 446-452, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Paris C. Kanellakis, Dimitrios Michailidis, Alexander A. Shvartsman |
Controlling Memory Access Concurrency in Efficient Fault-Tolerant Parallel Algorithms (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 7th International Workshop, WDAG '93, Lausanne, Switzerland, September 27-29, 1993, Proceedings, pp. 99-114, 1993, Springer, 3-540-57271-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Antonio Lioy |
Advanced Fault Collapsing (Logic Circuits Testing). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(1), pp. 64-71, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Michael Demjanenko, Shambhu J. Upadhyaya |
Yield enhancement of field programmable logic arrays by inherent component redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8), pp. 876-884, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Danny Dolev, Rüdiger Reischuk, H. Raymond Strong |
Early Stopping in Byzantine Agreement ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 37(4), pp. 720-741, October 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Charles H. Stapper |
Simulation of spatial fault distributions for integrated circuit yield estimations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), pp. 1314-1318, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | A. Jefferson Offutt |
The Coupling Effect: Fact or Fiction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symposium on Testing, Analysis, and Verification ![In: Proceedings of the ACM SIGSOFT '89 Third Symposium on Testing, Analysis, and Verification, TAV 1989, Key West, Florida, USA, December 13-15, 1989, pp. 131-140, 1989, ACM, 0-89791-342-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Irith Pomeranz, Sudhakar M. Reddy |
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 39-44, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnect open faults, test generation, bridging faults, static test compaction |
19 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 138-148, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect |
19 | M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor |
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 138-147, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults |
19 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 239-254, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults |
19 | Michael Nicolaidis |
Theory of Transparent BIST for RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(10), pp. 1141-1156, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RAM test algorithms, transparent BIST, BIST, signature analysis, pattern sensitive faults, coupling faults |
19 | Irith Pomeranz, Sudhakar M. Reddy |
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(1), pp. 20-32, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
partially detectable faults, synchronous sequential circuits, redundant faults, redundancy removal, synchronizing sequences, Fault removal |
19 | Daniel J. Kleitman, Frank Thomson Leighton, Yuan Ma |
On the Design of Reliable Boolean Circuits that Contain Partially Unreliable Gates ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 35th Annual Symposium on Foundations of Computer Science, Santa Fe, New Mexico, USA, 20-22 November 1994, pp. 332-346, 1994, IEEE Computer Society, 0-8186-6580-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
reliable Boolean circuits design, partially unreliable gates, gate failure, short-circuit model, von Neumann model, worst-case faults, post-test alterations, tight bound, random faults, fault-tolerant circuits |
19 | Rohit Kapur, M. Ray Mercer |
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1580-1588, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability |
19 | Thyagaraju R. Damarla |
Generalized Transforms for Multiple Valued Circuits and Their Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(9), pp. 1101-1109, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
generalised transforms, simple transforms, multiple value network, multiple valued circuits, spectral coefficients, VLSI, transforms, fault detection, upper bound, fault location, stuck at faults, many-valued logics, bridging faults, logic circuits, multiple valued functions, test patterns, test set generation, canonical representation, radix |
19 | Xiaoqing Wen, Kozo Kinoshita |
A Testable Design of Logic Circuits under Highly Observable Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(5), pp. 654-659, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
highly observable condition, fault tolerant computing, logic testing, integrated circuit testing, combinational circuit, stuck-at faults, logic circuits, integrated logic circuits, combinatorial circuits, stuck-open faults, testable design |
19 | T. Raju Damarla, Mark G. Karpovsky |
Fault Detection in Combinational Networks by Reed-Muller Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(6), pp. 788-797, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
single bridging faults, computational complexity, logic testing, test generation, fault detection, time complexity, upper bound, combinatorial circuits, combinational networks, test patterns, Reed-Muller transforms, multiple stuck-at-faults |
19 | Kang G. Shin, Parameswaran Ramanathan |
Transmission Delays in Hardware Clock Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1465-1467, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
hardware clock synchronization, malicious faults, delays, synchronisation, clocks, Byzantine faults, transmission delays, time overhead, clock signals |
19 | Israel Koren, Zahava Koren, Stephen Y. H. Su |
Analysis of a Class of Recovery Procedures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(8), pp. 703-712, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
program rollback, error recovery procedures, Checkpoint, intermittent faults, permanent faults, instruction retry, error latency |
19 | Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou |
Systematic t-Error Correcting/All Unidirectional Error Detecting Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(5), pp. 394-402, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
parity check codes, t-EC/AUED codes, error detection, error correction, transient faults, unidirectional errors, permanent faults, Concatenated codes, symmetric errors |
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