Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Vitit Kantabutra	Designing optimum carry-skip adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
16	Pak K. Chan, Martine D. F. Schlag	Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF
16	Akhilesh Tyagi	A reduced area scheme for carry-select adders.	ICCD	1990	DBLP DOI BibTeX RDF
16	Robert Michael Owens, Mary Jane Irwin	Implementing algorithms for convolution on arrays of adders.	ICASSP	1989	DBLP DOI BibTeX RDF
16	Silvio Turrini	Optimal group distribution in carry-skip adders.	IEEE Symposium on Computer Arithmetic	1989	DBLP DOI BibTeX RDF
16	Pak K. Chan, Martine D. F. Schlag	Analysis and design of CMOS Manchester adders with variable carry-skip.	IEEE Symposium on Computer Arithmetic	1989	DBLP DOI BibTeX RDF
16	Mary Jane Irwin, Robert Michael Owens	A comparison of two digit serial VLSI adders.	ICCD	1988	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Uwe Sparmann	Regular Structures and Testing: RCC-Adders.	AWOC	1988	DBLP DOI BibTeX RDF
16	Tack-Don Han, David A. Carlson	Fast area-efficient VLSI adders.	IEEE Symposium on Computer Arithmetic	1987	DBLP DOI BibTeX RDF
16	Tin-Fook Ngai, Mary Jane Irwin, Shishpal Rawat	Regular Area-Time Efficient Carry-Lookahead Adders.	J. Parallel Distributed Comput.	1986	DBLP DOI BibTeX RDF
16	Kazuo Iwano, Kenneth Steiglitz	Optimization of one-bit full adders embedded in regular structures.	IEEE Trans. Acoust. Speech Signal Process.	1986	DBLP DOI BibTeX RDF
16	Tin-Fook Ngai, Mary Jane Irwin	Regular, area-time efficient carry-lookahead adders.	IEEE Symposium on Computer Arithmetic	1985	DBLP DOI BibTeX RDF
16	Ging-Shung Yu, Saburo Muroga	Parallel multipliers with NOR gates based on G-minimum adders.	Int. J. Parallel Program.	1984	DBLP DOI BibTeX RDF
16	Akito Sakurai, Saburo Muroga	Parallel Binary Adders with a Minimum Number of Connections.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	ripple adder, Adder with a minimum number of connections, minimal adder, NOR gates, parallel adder, logic design
16	Richard P. Brent, H. T. Kung 0001	A Regular Layout for Parallel Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	area-time complexity, parallel addition, parallel polynomial evaluation, VLSI, models of computation, circuit design, Addition, combinational logic, prefix computation, carry lookahead
16	Bin Cheng	Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier		1982	RDF
16	Arnold Weinberger	High-Speed Programmable Logic Array Adders.	IBM J. Res. Dev.	1979	DBLP DOI BibTeX RDF
16	Arnold Weinberger	Parallel adders using standard plas.	IEEE Symposium on Computer Arithmetic	1978	DBLP DOI BibTeX RDF
16	Ging-Shung Yu	Search for Parallel Binary Adders With a Minimum Number of And/or Gates and Their Extension to High-Speed Parallel Multipliers		1978	RDF
16	Jean P. Chinal	The logic of modulo 2k + 1 adders.	IEEE Symposium on Computer Arithmetic	1975	DBLP DOI BibTeX RDF
16	Tso-Kai Liu, Keith R. Hohulin, Lih-Er Shiau, Saburo Muroga	Optimal One-Bit Full Adders With Different Types of Gates.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
16	Dhiraj K. Pradhan	Fault-Tolerant Carry-Save Adders.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
16	Tse Lin Wang, Chao-Kai Liu	Weight-Preserved Single-Error-Correcting Scheme for Binary Adders.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
16	Thammavarapu R. N. Rao	Error Correction in Adders using Systematic Subcodes.	IEEE Trans. Computers	1972	DBLP DOI BibTeX RDF
16	Anthony S. Wojcik, Gernot Metze	On the Cost of Base N Adders.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
16	Robert Orval Berg, Larry L. Kinney	Serial Adders with Overflow Correction.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
16	Charles W. Weller	A High-Speed Carry Circuit for Binary Adders.	IEEE Trans. Computers	1969	DBLP DOI BibTeX RDF
16	Stanislaw Majerski	On Determination of Optimal Distributions of Carry Skips in Adders.	IEEE Trans. Electron. Comput.	1967	DBLP DOI BibTeX RDF
16	Herbert H. Roth	Linear binary shift register circuits utilizing a minimum number of mod-2 adders.	IEEE Trans. Inf. Theory	1965	DBLP DOI BibTeX RDF
16	J. J. Amodei	High-Speed Adders and Comparators Using Transistors and Tunnel Dioes.	IEEE Trans. Electron. Comput.	1964	DBLP DOI BibTeX RDF
16	Jack Sklansky	Ultimate-Speed Adders.	IEEE Trans. Electron. Comput.	1963	DBLP DOI BibTeX RDF
16	David B. G. Edwards	High-Speed Transistorized Adders.	IRE Trans. Electron. Comput.	1961	DBLP DOI BibTeX RDF
16	Jack Sklansky	An Evaluation of Several Two-Summand Binary Adders.	IRE Trans. Electron. Comput.	1960	DBLP DOI BibTeX RDF
16	Meier M. Lehman, Naphtali Burla	A Note on the Simultaneous-Carry-Generation System for High-Speed Adders.	IRE Trans. Electron. Comput.	1960	DBLP DOI BibTeX RDF
15	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
15	Neil Burgess	The Flagged Prefix Adder and its Applications in Integer Arithmetic.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	prefix adders, absolute difference, end-around carry, computer arithmetic
15	Dhananjay S. Phatak, Tom Goff, Israel Koren	Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition
15	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
15	Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez	High Speed GaAs Subsystem Design using Feed Through Logic.	DATE	1999	DBLP DOI BibTeX RDF	GaAs fast arithmetic circuits, GaAs design methodologies, GaAs subsystem design, GaAs ripple-carry adders, GaAs magnitude comparators
15	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
15	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
15	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
15	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
15	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
15	Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
15	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
15	K. Vijayan Asari, C. Eswaran	An Optimization Technique for the Design of Multiple Valued PLA's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis
15	Jean Vuillemin	On Circuits and Numbers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers
15	Chien-In Henry Chen, Anup Kumar	Comments on "Area-Time Optimal Adder Design".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	VLSI parallel adder, optimal 32-bit fast carry generator, fast carry generator, BiCMOS drivers, optimal adder design, adders, carry logic, critical path delay
15	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
15	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
15	Dirk Timmermann, Helmut Hahn, Bedrich J. Hosticka	Low Latency Time CORDIC Algorithms.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	constant scale factor, redundant addition, latency time, computational complexity, parallel architecture, iterative methods, digital arithmetic, adders, number theory, CORDIC algorithms
15	Nhon T. Quach, Michael J. Flynn	High-Speed Addition in CMOS.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit
15	Robert Michael Owens, Mary Jane Irwin	Being Stingy with Multipliers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	VLSI signal processor, signal processing architectures, signal processing equipment, VLSI, interconnect, adders, multipliers, digital signal processing chips
15	Homayoon Sam, Arupratan Gupta	A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation
15	Belle W. Y. Wei, Clark D. Thompson	Area-Time Optimal Adder Design.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	area-time optimal adder design, VLSI parallel adder, component cells, static CMOS, floating-point processor, 66 bit, VLSI, dynamic programming, dynamic programming, logic design, digital arithmetic, adders, CMOS integrated circuits, modular design
15	Mike Paterson, Nicholas Pippenger, Uri Zwick	Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions	FOCS	1990	DBLP DOI BibTeX RDF	multiplication circuits, multiple addition, shallowest possible circuits, shortest possible formulas, occurrence matrix, shortest multiple carry-save addition formulas, delay matrix, multiple carry-save adders, multiplication, symmetric Boolean functions, carry-save addition
15	Robert W. Doran	Variants of an Improved Carry Look-Ahead Adder.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	look-ahead carry, adder, adders, variation, improved, carry look-ahead adder
15	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder
15	Sebastián Dormido 0001, M. A. Canto	An Upper Bound for the Synthesis of Generalized Parallel Counters.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel counter networks, Digital counters, multiple input adders, parallel counters, fast multipliers
15	K. Wayne Current	A High Data-Rate Digital Output Correlator Design.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Digital correlators, latched quaternary threshold logic full adders, multiple valued logic, threshold logic, parallel counters
15	K. Wayne Current, Douglas A. Mow	Implementing Parallel Counters with Four-Valued Threshold Logic.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	Four-valved logic full adders, multivalued logic, threshold logic, parallel counters
15	Dharma P. Agrawal	A Novel Technique for Computing Negabinary Squares.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	subtrahend, Base-2 or negabinary, negabinary adders, polarized addend, square-root, square, reduction technique
15	Hideaki Kobayashi, Hiroyoshi Ohara	A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Array logics, carry-shower counters, digital counters, multiple-input adders, parallel-counter networks, parallel counters, associative processors, fast multipliers
15	Paul W. Baker	Suggestion for a Fast Binary Sine/Cosine Generator.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	Cascaded carry-save adders, continued products, digital arithmetic, sines, cosines
15	Frank M. Brown	Weighted Realizations of Switching Functions.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	tally-coded representations, multiplexers, combinational logic, symmetric functions, Binary adders
9	Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
9	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
9	Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy 0001	Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
9	Xiao-dong Sun, Hong-Bin Zhang	A Fast Hole-filling Strategy of 3D Scanned Human Body.	CGIV	2009	DBLP DOI BibTeX RDF
9	Hun-sik Kang, Kwang-Eui Pyun, Sin-Chong Park	A hardware implementation of AGC and synchronization for OFDM-based WLAN.	ICHIT	2009	DBLP DOI BibTeX RDF	AGC, preamble, synchronization, OFDM, matched filter, phase estimation
9	Abdulah Abdulah Zadeh	High performance synchronized dual elliptic curve crypto-processor.	CCECE	2009	DBLP DOI BibTeX RDF
9	Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita	Polynomial datapath optimization using partitioning and compensation heuristics.	DAC	2009	DBLP DOI BibTeX RDF	modular HED, polynomial datapath, high-level synthesis
9	Mitchell J. Myjak, José G. Delgado-Frias	A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Youngmoon Choi, Earl E. Swartzlander Jr.	Speculative Carry Generation With Prefix Adder.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien	Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk	CHIPS: Custom Hardware Instruction Processor Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew	GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002	An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	number comparison, sign determination, overflow detection, VLSI, RNS, parity check
9	Rodney Van Meter, W. J. Munro, Kae Nemoto, Kohei M. Itoh	Arithmetic on a distributed-memory quantum multicomputer.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	quantum computer architecture, Quantum computing
9	Sabyasachi Das, Sunil P. Khatri	Resource sharing among mutually exclusive sum-of-product blocks for area reduction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF
9	Bijan Davvaz	Approximations in n -ary algebraic systems.	Soft Comput.	2008	DBLP DOI BibTeX RDF	Algebraic system, n-ary semigroup, Rough set, Fuzzy set, Upper approximation, Lower approximation
9	Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	data transition detection, CLA, pipeline, power-aware, ANT
9	Amit Pande, Joseph Zambreno	Design and analysis of efficient reconfigurable wavelet filters.	EIT	2008	DBLP DOI BibTeX RDF
9	Ruzica Jevtic, Carlos Carreras	Analytical High-Level Power Model for LUT-Based Components.	PATMOS	2008	DBLP DOI BibTeX RDF
9	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	A novel FPGA logic block for improved arithmetic performance.	FPGA	2008	DBLP DOI BibTeX RDF	6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
9	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.	DATE	2008	DBLP DOI BibTeX RDF
9	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Efficient synthesis of compressor trees on FPGAs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
9	Yuen-Hong Alvin Ho, Chi-Un Lei, Hing-Kit Kwan, Ngai Wong	Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications.	ASP-DAC	2008	DBLP DOI BibTeX RDF
9	Douglas L. Maskell, Achutavarrier Prasad Vinod, Graham S. Woods	Multiplierless multi-standard SDR channel filters.	MMSP	2008	DBLP DOI BibTeX RDF
9	Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola	On Evolutionary Synthesis of Linear Transforms in FPGA.	ICES	2008	DBLP DOI BibTeX RDF
9	Butler W. Lampson	Lazy and speculative execution in computer systems.	ICFP	2008	DBLP DOI BibTeX RDF	lazy evaluation
9	Hani H. Saleh, Earl E. Swartzlander Jr.	A floating-point fused dot-product unit.	ICCD	2008	DBLP DOI BibTeX RDF
9	Luigi Dadda, Alberto Nannarelli	A variant of a radix-10 combinational multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Chong-Yu Huang, Lien-Fei Chen, Yeong-Kang Lai	A high-speed 2-D transform architecture with unique kernel for multi-standard video applications.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Ya Jun Yu, Dong Shi, Yong Ching Lim	Subexpression encoded extrapolated impulse response FIR filter with perfect residual compensation.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Jang Woong Park, Hyoung Jin Yun, Myung Hoon Sunwoo, Pansoo Kim, Dae-Ig Chang	Efficient coarse frequency synchronizer using serial correlator for DVB-S2.	ISCAS	2008	DBLP DOI BibTeX RDF