Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Sivanarayana Mallela, Gerald M. Masson	Diagnosis Without Repair for Hybrid Fault Situations.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	diagnosability without repair, hybrid fault situation, fault diagnosis, PMC models, intermittent faults, permanent faults, Connection assignment
19	Dhiraj K. Pradhan	A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Coset codes, decoder logic, erasure decoding, mass memories, multiple errors, TSC checkers, error detection, error correction, transient faults, multiple faults, unidirectional errors, self-checking, shift register memories, read-only memories, random errors, two-rail checkers
19	Premachandran R. Menon, Stephen G. Chappell	Deductive Fault Simulation with Functional Blocks.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	fault lists, simulation, functional, faults, Deductive, functional faults, fault propagation
19	James E. Smith 0001	On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	undetectable faults, multiple redundancy, redundancy, Fault detection, multiple faults
19	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Enhancement of Clock Delay Faults Testing.	ETS	2011	DBLP DOI BibTeX RDF	Clock line, Test Generation, Delay faults
19	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.	IEEE Trans. Parallel Distributed Syst.	2010	DBLP DOI BibTeX RDF	fault tolerance, interconnection network, cache coherence, transient faults
19	Roberto Natella, Domenico Cotroneo	Emulation of Transient Software Faults for Dependability Assessment: A Case Study.	EDCC	2010	DBLP DOI BibTeX RDF	Dependability Assessment, Mandelbugs, Fault Tolerance, Software Faults, Software Fault Injection
19	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.	VLSI Design	2010	DBLP DOI BibTeX RDF	Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults
19	Lingfu Xie, Du Xu	The Two-Level-Turn-Model Fault-Tolerant Routing Scheme in Tori with Convex and Concave Faults.	ITNG	2009	DBLP DOI BibTeX RDF	two-level-turn-model, concave faults, fault-tolerant routing, Tori
19	Yu Huang 0005, Wu-Tung Cheng, Ruifeng Guo	Diagnose Multiple Stuck-at Scan Chain Faults.	ETS	2008	DBLP DOI BibTeX RDF	chain diagnosis, multiple faults, dynamic learning
19	Sun-Yuan Hsieh, Chia-Wei Lee	Hamiltonicity of Matching Composition Networks with Conditional Edge Faults.	TAMC	2008	DBLP DOI BibTeX RDF	Algorithmica aspect of network problems, conditional edge faults, matching composition networks, restricted hypercube-like networks, fault-tolerance, graph theory, multiprocessor systems, Hamiltonian cycles, Hamiltonicity
19	Sérgio Pinheiro dos Santos, José Alfredo F. Costa	A Comparison between Hybrid and Non-hybrid Classifiers in Diagnosis of Induction Motor Faults.	CSE	2008	DBLP DOI BibTeX RDF	Machine learning, Faults detection, Induction motors, Multi-classifiers systems
19	Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Bell	Locating where faults will be.	Richard Tapia Celebration of Diversity in Computing Conference	2005	DBLP DOI BibTeX RDF	software testing, prediction, empirical study, software faults, regression model, fault-prone
19	John P. Hayes, Ilia Polian, Bernd Becker 0001	Testing for Missing-Gate Faults in Reversible Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	missing gate faults, fault models, design for test, quantum circuits, Reversible circuits
19	Yih-Peng Hwang, David C. Rine	Algorithms to detect chained-inference faults in information distribution systems.	SAC	2001	DBLP DOI BibTeX RDF	CI systems, chained-inference rule faults, transistion-directed graph, distribution systems, fault detection, information
19	Chenggong Charles Fan, Jehoshua Bruck	Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	extra-stage, switch faults, stage masks, fault tolerance, Multistage Interconnection Networks (MIN)
19	Said Hamdioui, Ad J. van de Goor	Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port memories, single-port memories, address decoder faults, read-only ports, write-only ports, fault models, fault coverage, march tests
19	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
19	Seungjin Park, Jong-Hoon Youn, Bella Bose	Fault-Tolerant Wormhole Routing Algorithms in Meshes in the Presence of Concave Faults.	IPDPS	2000	DBLP DOI BibTeX RDF	concave faults, fault-tolerant, wormhole routing, mesh network, virtual channel
19	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	BIST, delay faults, scan design
19	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
19	Suresh Chalasani, Rajendra V. Boppana	Communication in Multicomputers with Nonconvex Faults.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	Solid faults, routing algorithms, deadlocks, wormhole routing, mesh networks, multicomputers
19	Jie Wu 0001, Eduardo B. Fernández, Yingquiu Luo	Embedding of binomial trees in hypercubes with link faults.	ICPP	1997	DBLP DOI BibTeX RDF	binomial trees embedding, variable roots, faulty links, n-level binomial tree, spanning binomial trees, fault tolerance property, reduction operations, binomial tree structure, performance, broadcasting, hypercubes, hypercube networks, n-cubes, link faults
19	Hagbae Kim, Kang G. Shin	Sequencing Tasks to Minimize the Effects of Near-Coincident Faults in TMR Controller Computers.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	TMR failure, common-cause and independent faults, random and effective sequencing of tasks, Task Interval (TI), task distance, conventional
19	Martine D. F. Schlag, F. Joel Ferguson	Detection of Multiple Faults in Two-Dimensional ILAs.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	testing, functional testing, multipliers, multiple faults, Iterative logic arrays
19	Irith Pomeranz, Sudhakar M. Reddy	On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis
19	Sreejit Chakravarty, Paul J. Thadikaran	Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	test generation, fault simulation, Bridging faults, IDDQ testing
19	Peter Wohl, John A. Waicukauski, Matthew Graf	Testing "untestable" faults in three-state circuits.	VTS	1996	DBLP DOI BibTeX RDF	three-state circuits, complex CMOS designs, nonconventional circuits, test generation techniques, circuit particularities, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, test coverage, multivalued logic circuits, computer testing, CPU time, test vector generation, untestable faults, automatic learning
19	Richard Cole 0001, Bruce M. Maggs, Ramesh K. Sitaraman	Routing on Butterfly Networks with Random Faults.	FOCS	1995	DBLP DOI BibTeX RDF	constant probability, reliability, fault tolerant computing, probability, packet switching, routing algorithm, hypercube networks, packet routing, butterfly networks, random faults
19	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
19	Shih-Yuang Su, Cheng-Wen Wu	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
19	Michael Harrington, Arun K. Somani	Synchronizing Hypercube Networks in the Presence of Faults.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypercube networks synchronisation, redundant results, fault tolerant hardware synchronization schemes, multistage synchronizers, Proteus parallel computer system, circuit switching communication network, reliability, fault tolerant computing, application specific integrated circuits, synchronisation, hypercube networks, distributed networks, phased locked loops, fault tolerant systems, Byzantine faults, synchronous programs, ASIC design
19	S. A. Ali, G. Robert Redinbo	Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	tight lower bounds, internal signal lines, fault diagnosis, logic testing, combinational circuits, combinational circuits, random testing, detection probabilities, single faults
19	Frank Thomson Leighton, Yuan Ma	Breaking the Theta(n log ^2 n) Barrier for Sorting with Faults (Extended Abstract)	FOCS	1993	DBLP DOI BibTeX RDF	sorting with faults, sorting circuit, PRAM algorithm, passive-fault-tolerant sorting circuit, reversal-fault-tolerant sorting network, fault-tolerant sorting algorithm, fault-tolerant, parallel algorithms, sorting network
19	Kostas N. Oikonomou	Abstractions of Finite-State Machines and Immediately-Detectable Output Faults.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	immediately-detectable output faults, nondeterministic machine, approximately optimal partition, computational complexity, data structures, fault tolerant computing, abstraction, NP-complete, finite-state machines, polynomial-time algorithm, finite automata, set partitioning
19	Hisao Tamaki	Efficient Self-Embedding of Butterfly Networks with Random Faults	FOCS	1992	DBLP DOI BibTeX RDF	level-preserving embedding, self-embedding, node-failure probability, congestion, dilation, butterfly networks, random faults
19	Sreejit Chakravarty, Harry B. Hunt III	On Computing Signal Probability and Detection Probability of Stuck-at Faults.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	pseudo gates, logic testing, built-in self test, combinational circuits, random testing, stuck-at faults, combinatorial circuits, testability analysis, detection probability, signal probability, pseudorandom testing, enumeration algorithm
19	Pinaki Mazumder, Janak H. Patel	Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	semiconductor random-access memories, design-for-testability approach, MOS integrated circuits, reliability, integrated circuit testing, linear complexity, MOS, random-access storage, integrated memory circuits, pattern-sensitive faults, design strategy, parallel testing
19	Jacob Savir, William H. McAnney	Random Pattern Testability of Delay Faults.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks
19	Kostas N. Oikonomou	Abstractions of Finite-State Machines Optimal with Respect to Single Undetectable Output Faults.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	undetectable output faults, optimal abstraction, Abstraction, finite-state machine, observer, branch-and-bound algorithm
19	Miron Abramovici, Prem R. Menon	A Practical Approach to Fault Simulation and Test Generation for Bridging Faults.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	test generation, fault detection, fault simulation, Bridging faults
19	Mark G. Karpovsky	Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	upper and lower bounds for number of tests, Asymptotically optimal tests, stuck-at and bridging faults, universal tests, fault detection
19	Teruhiko Yamada, Takashi Nanya	Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Asynchronous behavior, test generation, fault detection, fault location, bridging faults, combinational networks
19	Dong S. Suk, Sudhakar M. Reddy	A March Test for Functional Faults in Semiconductor Random Access Memories.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	random access memories (RAM's), lower bounds, Functional faults
19	Sharad C. Seth, K. Narayanaswamy	A Graph Model for Pattern-Sensitive Faults in Random Access Memories.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	single pattern-sensitive faults, Coloring algorithm, optimal transition write sequences, graph modeling, RAM testing
19	Pramod K. Varshney	On Analytical Modeling of Intermittent Faults in Digital Systems.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	fault detection algorithms, fault tolerant computing, Analytical models, digital systems, intermittent faults
19	Stephen Y. H. Su, Israel Koren, Yashwant K. Malaiya	A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	repetitive testing, Continuous-parameter Markov model, continuous testing, optimal testing experiments, fault detection, intermittent faults
19	Israel Koren, Zvi Kohavi	Diagnosis of Intermittent Faults in Combinational Networks.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	sequential decision tree, dynamic programming, fault diagnosis, Combinational networks, intermittent faults, weighting function
19	John F. Meyer, Robert J. Sundstrom	On-Line Diagnosis of Unrestricted Faults.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	inverse sequential machines, on-line diagnosis, reliable automata, unrestricted faults, fault diagnosis, Concurrent error detection
19	John P. Hayes	Detection of Pattern-Sensitive Faults in Random-Access Memories.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	fault detection, random-access memories, pattern-sensitive faults, Checking experiments
18	Jiahao Song, Xiao He 0001	Estimation of Periodically Occurring Faults for Dynamic Systems With Timing Misalignment Between Faults and Observations.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
18	Enze Zhang, Qingnan Huang, Zhongqing Wei, Xiangsuo Fan, Shan Su	H∞ Robust Fault-Tolerant Control of a Six-Rotor UAV Containing Sensor Faults and Actuator Non-Affine Faults.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Shuiqing Xu, Xinyang Chen, Feng Liu, Hai Wang 0004, Yi Chai, Wei Xing Zheng 0001, Hongtian Chen	A Novel Adaptive SMO-Based Simultaneous Diagnosis Method for IGBT Open-Circuit Faults and Current Sensor Incipient Faults of Inverters in PMSM Drives for Electric Vehicles.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
18	Qinghua Hou, Jiuxiang Dong	Enabling Reliable Cooperative Output Regulation in Directed Graphs: Fully Distributed Event-Triggered Protocols for Multiagent Systems With Actuator Faults and Communication Link Faults.	IEEE Syst. J.	2023	DBLP DOI BibTeX RDF
18	Navya Mohan, J. P. Anita	Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults.	Integr.	2022	DBLP DOI BibTeX RDF
18	Irith Pomeranz	Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
18	Irith Pomeranz	GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
18	Syed Sha Qutub, Florian Geissler, Yang Peng, Ralf Gräfe, Michael Paulitsch, Gereon Hinz, Alois C. Knoll	Hardware faults that matter: Understanding and Estimating the safety impact of hardware faults on object detection DNNs.	CoRR	2022	DBLP DOI BibTeX RDF
18	Syed Sha Qutub, Florian Geissler, Yang Peng, Ralf Gräfe, Michael Paulitsch, Gereon Hinz, Alois C. Knoll	Hardware Faults that Matter: Understanding and Estimating the Safety Impact of Hardware Faults on Object Detection DNNs.	SAFECOMP	2022	DBLP DOI BibTeX RDF
18	Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.	CoRR	2021	DBLP BibTeX RDF
18	Reut Asraf, Chen Rozenshtein, David Sarne	On the Effect of User Faults on her Perception of Agent's Faults in Collaborative Settings.	HAI	2021	DBLP DOI BibTeX RDF
18	Praikanok Lertwanitrot, Atthapol Ngaopitakkul	Discriminating Between Capacitor Bank Faults and External Faults for an Unbalanced Current Protection Relay Using DWT.	IEEE Access	2020	DBLP DOI BibTeX RDF
18	Tejun Zhou, Jiazheng Lu, Bo Li, Yanjun Tan	Fractal Analysis of Power Grid Faults and Cross Correlation for the Faults and Meteorological Factors.	IEEE Access	2020	DBLP DOI BibTeX RDF
18	Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.	IOLTS	2020	DBLP DOI BibTeX RDF
18	Claire McKay Bowen, Nathan DeBardeleben, Sean Blanchard, Christine M. Anderson-Cook	Do Solar Proton Events Reduce the Number of Faults in Supercomputers?: A Comparative Analysis of Faults During and without Solar Proton Events.	IRPS	2019	DBLP DOI BibTeX RDF
18	Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita	Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.	ISQED	2019	DBLP DOI BibTeX RDF
18	Irith Pomeranz	Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults.	ITC	2019	DBLP DOI BibTeX RDF
18	Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita	An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
18	Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy	Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.	ITC-Asia	2018	DBLP DOI BibTeX RDF
18	Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita	Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.	ISCAS	2017	DBLP DOI BibTeX RDF
18	Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee	Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults.	ASP-DAC	2016	DBLP DOI BibTeX RDF
18	Gordon Fraser 0001, Andrea Arcuri	1600 faults in 100 projects: automatically finding faults while achieving high coverage with EvoSuite.	Empir. Softw. Eng.	2015	DBLP DOI BibTeX RDF
18	Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus	Combining Correction of Delay Faults and Transient Faults.	DDECS	2015	DBLP DOI BibTeX RDF
18	Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee	Distinguishing dynamic bridging faults and transition delay faults.	ASICON	2015	DBLP DOI BibTeX RDF
18	Roberto Pietrantuono, Stefano Russo 0001, Kishor S. Trivedi	Emulating Environment-Dependent Software Faults.	COUFLESS@ICSE	2015	DBLP DOI BibTeX RDF
18	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults.	ISVLSI	2014	DBLP DOI BibTeX RDF
18	Irith Pomeranz	Substituting transition faults with path delay faults as a basic delay fault model.	DATE	2014	DBLP DOI BibTeX RDF
18	Cheng-Hung Wu, Kuen-Jong Lee	An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults.	ATS	2014	DBLP DOI BibTeX RDF
18	Lingming Zhang 0001, Lu Zhang 0023, Sarfraz Khurshid	Injecting mechanical faults to localize developer faults for evolving software.	OOPSLA	2013	DBLP DOI BibTeX RDF
18	Qi Zhang, Xiaodong Zhang 0009	A distributed detection scheme for process faults and sensor faults in a class of interconnected nonlinear uncertain systems.	CDC	2012	DBLP DOI BibTeX RDF
18	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	On Detecting Transition Faults in the Presence of Clock Delay Faults.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
18	Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi	Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
18	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
18	Syed Shariyar Murtaza, Nazim H. Madhavji, Mechelle Gittens, Zude Li	Diagnosing new faults using mutants and prior faults.	ICSE	2011	DBLP DOI BibTeX RDF
18	Yiwen Shi, Wan-Chan Hu, Jennifer Dworak	Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects.	VTS	2010	DBLP DOI BibTeX RDF
18	Ezra N. Hoch	Bridging the gap : Byzantine faults and self-stabilization (עם תקציר בעברית ושער נוסף: שילוב של שגיאות ביזנטיות עם התייצבות עצמית.; Byzantine faults and self-stabilization.).		2010	RDF
18	Ad J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars	New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
18	Piet Engelke	Resistive bridging faults - defect-oriented modeling and efficient testing (Resistive bridging faults - defektorientierte Modellierung und effizienter Test)		2009	RDF
18	Peter Fogh Odgaard, Jakob Stoustrup, Palle Andersen, Enrique Vidal	Accommodation of Repetitive Sensor Faults - Applied to Surface Faults on Compact Discs.	IEEE Trans. Control. Syst. Technol.	2008	DBLP DOI BibTeX RDF
18	Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Sudhakar M. Reddy	Using dummy bridging faults to define a reduced set of target faults.	ETS	2005	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Sudhakar M. Reddy	Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults.	DATE	2002	DBLP DOI BibTeX RDF
18	Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu	Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Sudhakar M. Reddy	Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	fault diagnosis, Circuit partitioning
18	Richard J. Cole, Bruce M. Maggs, Ramesh K. Sitaraman	Reconfiguring Arrays with Faults Part I: Worst-Case Faults.	SIAM J. Comput.	1997	DBLP DOI BibTeX RDF
18	Andrzej Krasniewski, Leszek B. Wronski	Tests for path delay faults vs. tests for gate delay faults: how different they are.	EURO-DAC	1994	DBLP DOI BibTeX RDF
18	Uwe Hübner, Wolfgang Meyer 0002, Heinrich Theodor Vierhaus	CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Sudhakar M. Reddy	Generalization of independent faults for transition faults.	VTS	1992	DBLP DOI BibTeX RDF
18	François Darlay	Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
18	Jaushin Lee, Janak H. Patel	ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults.	ITC	1991	DBLP DOI BibTeX RDF