Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Julia Lipman, Quentin F. Stout	A performance analysis of local synchronization.	SPAA	2006	DBLP DOI BibTeX RDF	geometric distribution, stochastic task times, performance analysis, synchronization, heavy-tailed distribution
16	Hai Li, Chen-Yong Cher, Kaushik Roy 0001, T. N. Vijaykumar	Combined circuit and architectural level variable supply-voltage scaling for low power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Jingzhao Ou, Viktor K. Prasanna	COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors.	FCCM	2005	DBLP DOI BibTeX RDF
16	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	Karl-Erwin Großpietsch, Tanya A. Silayeva	A Combined Safety/Security Approach for Co-Operative Distributed Systems.	IPDPS	2004	DBLP DOI BibTeX RDF
16	Gang Quan, Linwei Niu, Xiaobo Sharon Hu, Bren Mochocki	Fixed Priority Scheduling for Reducing Overall Energy on Variable Voltage Processors.	RTSS	2004	DBLP DOI BibTeX RDF
16	Yung-Yuan Chen, Kun-Feng Chen	Incorporating Signature-Monitoring Technique in VLIW Processors.	DFT	2004	DBLP DOI BibTeX RDF
16	Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton	Continual flow pipelines.	ASPLOS	2004	DBLP DOI BibTeX RDF	CFP, non-blocking, latency tolerance, instruction window
16	Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy	An evaluation of speculative instruction execution on simultaneous multithreaded processors.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading
16	Thin-Fong Tsuei, Wayne Yamamoto	Queuing Simulation Model for Multiprocessor Systems.	Computer	2003	DBLP DOI BibTeX RDF
16	Deependra Talla, Lizy Kurian John, Doug Burger	Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	bottlenecks in SIMD extensions, hardware address generation, low-overhead looping, superscalar general-purpose processors, performance evaluation, workload characterization, subword parallelism, Media processing, data reorganization
16	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
16	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Energy Estimation for Extensible Processors.	DATE	2003	DBLP DOI BibTeX RDF
16	Joshua J. Yi, David J. Lilja, Douglas M. Hawkins	A Statistically Rigorous Approach for Improving Simulation Methodology.	HPCA	2003	DBLP DOI BibTeX RDF
16	Francisco Rodríguez 0003, José Carlos Campelo, Juan José Serrano	A Memory Overhead valuation of the Interleaved Signature Instruction Stream.	DFT	2002	DBLP DOI BibTeX RDF
16	Michael J. Flynn, Albert A. Liddicoat	Technology Trends and Adaptive Computing.	FPL	2001	DBLP DOI BibTeX RDF
16	Marek Tudruj, Lukasz Masko	Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approach.	PPAM	2001	DBLP DOI BibTeX RDF
16	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
16	José Aguilar 0001, Marisela Hernández	Fault Tolerance Protocols for Parallel Programs Based on Tasks Replication.	MASCOTS	2000	DBLP DOI BibTeX RDF
16	Sathiamoorthy Manoharan, Kim See-Mu	A Hardware Scheme for Data Prefetching.	HPCN	2000	DBLP DOI BibTeX RDF
16	Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman	Distributed cooperation in the absence of communication (brief announcement).	PODC	2000	DBLP DOI BibTeX RDF
16	Klaus Herrmann 0002, Sören Moch, Jörg Hilgenstock, Peter Pirsch	Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.	DFT	2000	DBLP DOI BibTeX RDF
16	Enric Musoll	Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors.	MICRO	1999	DBLP DOI BibTeX RDF
16	Micah Adler, John W. Byers, Richard M. Karp	Scheduling Parallel Communication: The h-relation Problem.	MFCS	1995	DBLP DOI BibTeX RDF
16	Jörg Wilberg, Raul Camposano, Wolfgang Rosenstiel	Design flow for hardware/software cosynthesis of a video compression system.	CODES	1994	DBLP DOI BibTeX RDF
16	Bernard Lang, Christian Queinnec, José M. Piquer	Garbage Collecting the World.	POPL	1992	DBLP DOI BibTeX RDF
16	Amotz Bar-Noy, Danny Dolev, Daphne Koller, David Peleg	Fault-Tolerant Critical Section Management in Asynchronous Networks.	WDAG	1989	DBLP DOI BibTeX RDF
16	John F. Stockton	The MC68000 family and distributed processing.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
16	James D. Feldman, Louis C. Fulmer	RADCAP: an operational parallel processing facility.	AFIPS National Computer Conference	1974	DBLP DOI BibTeX RDF
16	Heon-Mo Koo, Prabhat Mishra 0001	Functional test generation using design and property decomposition techniques.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	design decomposition, property decomposition, Model checking, test generation, pipelined processor, functional validation
16	Feng Zhang 0015, Sarah Tasneem, Lester Lipsky, Steve Thompson	Analysis of round-robin variants: favoring newly arrived jobs.	SpringSim	2009	DBLP DOI BibTeX RDF	foreground-background (FB), last-come-first-served with preemptive resume (LCFSPR), processor sharing (PS), round-robin (RR), shortest remaining processing time (SRPT)
16	Turner Whitted, James T. Kajiya, Erik Ruf, Ray Bittner	Embedded function composition.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	display processor, representation, large display
16	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
16	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.	LCTES	2008	DBLP DOI BibTeX RDF	energy-delay, out-of-order embedded processor, resource resizing, performance, architecture
16	Ke Meng, Russ Joseph, Robert P. Dick, Li Shang	Multi-optimization power management for chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	cache resizing, voltage/frequency scaling, dynamic power management, chip multi-processor
16	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
16	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	ARISE Machines: Extending Processors with Hybrid Accelerators.	ARC	2008	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, custom unit, FPGA, coprocessor
16	John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols	Coherency Hub Design for Multi-Node Victoria Falls Server Systems.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency
16	Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng	The Blackford Northbridge Chipset for the Intel 5000.	IEEE Micro	2007	DBLP DOI BibTeX RDF	platform architecture, dual-processor system, northbridge chipset, I/O bridges, FB-DIMM memory technology, low-power design, shared memory
16	Rajani Pai, R. Govindarajan	FEADS: A Framework for Exploring the Application Design Space on Network Processors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance Evaluation, petri Nets, design space exploration, network processor, programming model, Cyclic scheduling
16	Saina Jalili, Ali Movaghar 0001, Maryam Sadrmousavi	An improved replacement algorithm in fault-tolerant meshes.	SCSC	2007	DBLP BibTeX RDF	fault tolerance, mesh, processor allocation, replacement
16	Matt T. Yourst	PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator.	ISPASS	2007	DBLP DOI BibTeX RDF	client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine
16	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
16	Kunal Agrawal, Yuxiong He, Charles E. Leiserson	Adaptive work stealing with parallelism feedback.	PPoPP	2007	DBLP DOI BibTeX RDF	multithreaded languages, parallelism feedback, trim analysis, parallel computation, job scheduling, multiprogramming, processor allocation, work stealing, adaptive scheduling, distributed scheduling, thread scheduling, adversary, space sharing, two-level scheduling
16	Alireza Hodjat, Ingrid Verbauwhede	Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures
16	Oliver Sinnen, Leonel Augusto Sousa, Frode Eika Sandnes	Toward a Realistic Task Scheduling Model.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	processor involvement, heterogeneous system model, Parallel processing, concurrent programming, scheduling and task partitioning
16	Luis Ceze, Karin Strauss, James Tuck 0001, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
16	Matthias Kühnemann, Thomas Rauber, Gudula Rünger	Optimizing MPI collective communication by orthogonal structures.	Clust. Comput.	2006	DBLP DOI BibTeX RDF	MPI communication operation, Orthogonal processor groups, Modeling of communication time, Parallel application
16	Hong Yue, Zhiying Wang 0003, Kui Dai	A Heterogeneous Embedded MPSoC for Multimedia Applications.	HPCC	2006	DBLP DOI BibTeX RDF	Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC
16	Abeer Hamdy, Ahmed Hussein, Reda A. Ammar	An Efficient Workload Allocation to Improve Scheduling Real-Time Tasks.	ISCC	2006	DBLP DOI BibTeX RDF	Workload allocation, Processing power, scheduling real-time tasks, Processor utilization
16	D. Doreen Hephzibah Miriam, T. Srinivasan 0001, R. Deepa 0001	An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors.	PARELEC	2006	DBLP DOI BibTeX RDF	Full subcube recognition, k-ary n-cube systems, isomorphic partitioning, processor allocation
16	Hyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti	Reducing idle mode power in software defined radio terminals.	ISLPED	2006	DBLP DOI BibTeX RDF	baseband processor, idle mode, wireless terminal, low power, SIMD, SDR, software defined radio
16	D. Doreen Hephzibah Miriam, T. Srinivasan 0001	A Fast and Efficient Isomorphic Task Allocation Scheme for K-Ary N-Cube Systems.	DIPES	2006	DBLP DOI BibTeX RDF	Full subcube recognition, k-ary n-cube systems, isomorphic partitioning, processor allocation
16	Chao Huang 0029, Gengbin Zheng, Laxmikant V. Kalé, Sameer Kumar 0001	Performance evaluation of adaptive MPI.	PPoPP	2006	DBLP DOI BibTeX RDF	processor virtualization, adaptivity, load balancing, MPI, communication optimization
16	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Shielding against design flaws with field repairable control logic.	DAC	2006	DBLP DOI BibTeX RDF	hardware patching, processor verification
16	Yunkai Zhou, Harish Sethu	On achieving fairness in the joint allocation of processing and bandwidth resources: principles and algorithms.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	max-min, resource allocation, fairness, processor sharing
16	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Throughput.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade off, processor architecture, SMT
16	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
16	Vaidyanathan Ramadurai, Sanjay Jinturkar, Mayan Moudgill, John Glossner	Implementation of H.264 decoder on Sandblaster DSP.	ICME	2005	DBLP DOI BibTeX RDF	H.264-AVC baseline profile decoder, Sandblaster digital signal processor, ANSI C, DSP, optimization technique, software implementation
16	Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour	Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	COTS processors, fault injection, performance monitoring, analytical evaluation, watchdog processor, error detection coverage
16	Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies	Feedback driven instruction-set extension.	LCTES	2004	DBLP DOI BibTeX RDF	simulator generation, encryption, network processor, codesign, instruction-set extensions, compiler generation
16	Lorenzo Verdoscia	CODACS Project: A Development Tool for Embedded System Prototyping.	ICESS	2004	DBLP DOI BibTeX RDF	Application Specific Processor (ASP), FPGA, embedded system, functional programming, dataflow computing
16	Slo-Li Chu	PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture.	ICPADS	2004	DBLP DOI BibTeX RDF	Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE
16	Binu K. Mathew, Al Davis, Michael A. Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
16	Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.	DAC	2004	DBLP DOI BibTeX RDF	16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density
16	Nathan Clark, Hongtao Zhong, Wilkin Tang, Scott A. Mahlke	Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	hardware customization, embedded system, instruction set, application-specific processor, dataflow graph
16	Woo-Cheol Kwon, Taewhan Kim	Optimal voltage allocation techniques for dynamically variable voltage processors.	DAC	2003	DBLP DOI BibTeX RDF	scheduling, low power design, variable voltage processor
16	Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan	Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing.	IPDPS	2002	DBLP DOI BibTeX RDF	reconfigurable media processor, recurring pattern analyzer, mobile multimedia processing, partition, dynamic reconfiguration, reconfigurable architectures, data flow graph, control flow graph, MPEG4, hardware software co-design, hardware software partitioning, routing architecture
16	Harald P. E. Vranken	Debug Facilities in the TriMedia CPU64 Architecture.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	application debug, VLIW processor, design-for-debug
16	Stefan Pees, Andreas Hoffmann 0002, Heinrich Meyr	Retargetable compiled simulation of embedded processors using a machine description language.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	HW/SW cosimulation, machine description languages, processor modeling and simulation, system-on-chip, instruction set simulators, compiled simulation, DSP processors
16	Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens	Register Organization for Media Processing.	HPCA	2000	DBLP DOI BibTeX RDF	register organization, register architecture, processor architecture, media processors
16	José-Lorenzo Cruz, Antonio González 0001, Mateo Valero, Nigel P. Topham	Multiple-banked register file architectures.	ISCA	2000	DBLP DOI BibTeX RDF	bypass logic, register file architecture, register file cache, dynamically-scheduled processor
16	Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim	Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Coherence controller, protocol processor, multiprocessor, shared memory
16	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP DOI BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
16	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
16	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
16	Yu-Kwong Kwok, Ishfaq Ahmad	Dynamic Critical-Path Scheduling: An Effective Technique for Allocating Task Graphs to Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	clustering, Algorithms, multiprocessors, processor allocation, task graphs, list scheduling, parallel scheduling
16	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
16	Ian Watson, Alasdair Rawsthorne	Decoupled pre-fetching for distributed shared memory.	HICSS (1)	1995	DBLP DOI BibTeX RDF	partial evaluation (compilers), distributed shared memory environment, decoupled pre-fetching, global view, remote memory copies, user annotations, compile-time analysis, run-time prediction, irregular access patterns, dual processor structure, partial program evaluation, data fetches, parallel architectures, parallel machine, shared memory systems, distributed memory systems, memory architecture
16	G. N. Srinivasa Prasanna, Anant Agarwal, Bruce R. Musicus	Hierarchical Compilation of Macro Dataflow Graphs for Multiprocessors with Local Memory.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	hierarchicalcompilation, macro dataflow graphs, macro operations, precedenceconstraints, multiple nested loops, partitioning phase, close-to-optimal run-times, prototype structure-driven compiler, Alewife multiprocessor, simulator, performance evaluation, performance, multiprocessing systems, program compilers, processor allocation, nested loops, local memory, SDC
16	Duc J. Vianney, James H. Thomas, Vicki Rabaza	The Gould NP1 system interconnecting.	ICS	1988	DBLP DOI BibTeX RDF	Gould NP1, dual-cpu, processor farm, inter-system bus link, multiprocessor
16	T. H. Myer, Ivan E. Sutherland	On the design of display processors.	Commun. ACM	1968	DBLP DOI BibTeX RDF	display channel, display generator, display processor design, display programming, graphic terminal, remote displays, computer graphics, graphics, displays, graphical interaction, display system
16	Wei Huang 0004, Karthick Rajamani, Mircea R. Stan, Kevin Skadron	Scaling with Design Constraints: Predicting the Future of Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	big chips, cooling solution, power, system architecture, processor architecture, temperature, technology scaling, area, design constraints, many-core processor
16	Wenbin Fang, Bingsheng He, Qiong Luo 0001, Naga K. Govindaraju	Mars: Accelerating MapReduce with Graphics Processors.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	parallel computing, MapReduce, multicore processor, graphics processor, many-core architecture
16	Moshe Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim M. Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal	Analyzing Parallel Programs with Pin.	Computer	2010	DBLP DOI BibTeX RDF	Software engineering, Operating systems, Computer architectures, Processor architectures, Computer systems organization, Multiple processor systems
16	Ismail Ababneh, Wail Mardini, Hilal Alawneh, Mohammad Hamed, Saad Bani-Mohammad	Effects of Allocation Request Shape Changes on Performance in 2D Mesh-Connected Multicomputers.	CIT	2010	DBLP DOI BibTeX RDF	contiguous processor allocation, processor fragmentation, turnaround time, interprocessor communication, system utilization, Mesh multicomputers
16	Juan Fang, Xiaocui Wang	A Prefetching Coordinate Algorithm Which Can Be Used in Multi-core Processors.	FCST	2010	DBLP DOI BibTeX RDF	prefetching cooordinator, multi-processor prefetching, prefetch, multi-core processor
16	Marcio Juliato, Catherine H. Gebotys	Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals.	ReConFig	2009	DBLP DOI BibTeX RDF	Processor Specialization, SHA-2, Cryptography, HMAC, HW/SW Partitioning, Co-Processor, Custom Instruction
16	Tilman Wolf, Russell Tessier	Design of a Secure Router System for Next-Generation Networks.	NSS	2009	DBLP DOI BibTeX RDF	processor monitor, network security, embedded processor, router design
16	Junjie Wu 0003, Xiaohui Pan, Guanghui Liu, Baida Zhang, Xuejun Yang	Parallel Data Reuse Theory for OpenMP Applications.	SNPD	2009	DBLP DOI BibTeX RDF	Intra-processor, Inter-processor, Parallel, Locality, Reuse, OpenMP
16	Yefim Dinitz, Shlomo Moran, Sergio Rajsbaum	Bit complexity of breaking and achieving symmetry in chains and rings.	J. ACM	2008	DBLP DOI BibTeX RDF	bit complexity, processor chain, processor ring, symmetric synchronous execution, Distributed computing, lower bounds, consensus, communication complexity, leader election, communication cost, message complexity, tight bound
16	Valentina Salapura, Robert Walkup, Alan Gara	Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene.	IEEE Micro	2006	DBLP DOI BibTeX RDF	application studies resulting in better multiple-processor systems, super (very large) computers, Blue Gene/L system, architecture, parallelism, parallelism, interprocessor communications, processor architectures, power optimization, computer systems organization, computer system implementation
16	Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, Christof Paar	Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.	ITCC (2)	2004	DBLP DOI BibTeX RDF	genus 2, parallelism, embedded processor, hardware architecture, hyperelliptic curve, co-processor
16	Johnson Kin, Munish Gupta, William H. Mangione-Smith	Filtering Memory References to Increase Energy Efficiency.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	energy-delay, low power, embedded processor, media processor, Filter cache
16	James H. Anderson, Philip Holman	Efficient pure-buffer algorithms for real-time systems.	RTCSA	2000	DBLP DOI BibTeX RDF	efficient pure-buffer algorithms, multiprocessor real-time systems, multi-writer read/write pure-buffers, overwritten data, client processes, handshaking mechanisms, concurrent read/write operations safety, quantum-scheduled systems, priority-scheduled systems, buffer word length, real-time systems, computational complexity, distributed algorithms, safety, multiprocessing systems, time complexity, processor scheduling, optimized algorithms, buffer storage, space complexity, wait-free algorithms, shared buffers, processor number
16	Moreno Coli, Paolo Palazzari	Load Balancing with Internode Precedence Relations: A New Method for Static Allocation of DAGs into Parallel Systems.	PDP	1996	DBLP DOI BibTeX RDF	internode precedence relations, static allocation, parallel execution times, performance, parallel algorithms, load balancing, parallel programming, parallel program, resource allocation, NP-complete, parallel machine, directed graphs, DAG, directed acyclic graphs, processor scheduling, software performance evaluation, parallel systems, execution time, processor allocation, mapping algorithms, computational load
16	Bülent Abali, Craig B. Stunkel	Time synchronization on SP1 and SP2 parallel systems.	IPPS	1995	DBLP DOI BibTeX RDF	SP2 parallel system, SP1 parallel system, experimental time utility, operating system clocks, node clocks, synchronous feature, parallel program performance measurement, parallel program tuning, parallel program tracing, parallel program debugging, parallel processes, interconnection network, multiprocessor interconnection networks, multiprocessor interconnection networks, parallel machines, parallel machines, synchronisation, synchronisation, processor scheduling, processor scheduling, software performance evaluation, software performance evaluation, program debugging, program debugging, clocks, clocks, operating systems (computers), operating systems (computers), time synchronization, gang scheduling, reduced instruction set computing, reduced instruction set computing
16	Lennart Lindh, Johan Stärner, John Furunäs	From single to multiprocessor real-time kernels in hardware.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	multiprocessor real-time kernels, single processor real-time kernels, improved performance, improved determinism, integrated deterministic CPU, deterministic multitasking real time kernel, high performance multitasking real time kernel, high performance standalone multitasking real time kernel, deterministic standalone multitasking real time kernel, heterogeneous multiprocessor real-time systems, homogeneous multiprocessor real-time systems, scheduling, performance evaluation, real-time systems, multiprocessing systems, hardware, reconfigurable architectures, processor scheduling, multiprogramming, operating system kernels, firmware
16	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
16	Yonatan Aumann, Zvi M. Kedem, Krishna V. Palem, Michael O. Rabin	Highly Efficient Asynchronous Execution of Large-Grained Parallel Programs	FOCS	1993	DBLP DOI BibTeX RDF	memory space overhead, highly efficient asynchronous execution, large-grained parallel programs, processor instructions, PRAM programs, n-processor asynchronous parallel system, granularity, synchronization mechanisms