Search results for "1149.1"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
95	Bill Eklow, Carl Barnhart, Mike Ricchetti, Terry Borroz	IEEE 1149.6 - A Practical Perspective.	ITC	2003	DBLP DOI BibTeX RDF
95	Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu	Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
82	Debashis Bhattacharya	Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller.	VTS	1999	DBLP DOI BibTeX RDF
82	Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu	Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	MTM Bus, Boundary Scan, Hierarchical Testing
77	Clayton Gibbs	Backplane Test Bus Applications For IEEE STD 1149.1.	ITC	2003	DBLP DOI BibTeX RDF
77	Bulent I. Dervisoglu, Mike Ricchetti, William Eklow	Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.	ITC	1998	DBLP DOI BibTeX RDF
63	Rakesh N. Joshi, Kenneth L. Williams, Lee Whetsel	Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices.	ITC	2003	DBLP DOI BibTeX RDF
63	Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani	A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic.	ITC	2003	DBLP DOI BibTeX RDF
59	Chouki Aktouf, Chantal Robach, A. Marinescu, Guy Mazaré	An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	routing test, IEEE 1149.1, built-in self-test, diagnosis, MIMD architectures
59	R. G. Bennetts, A. Osseyran	IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	device test, board test, 1149.1, boundary scan
59	Colin M. Maunder, Rodham E. Tulloss	An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	ANSI/IEEE Std 1149.1, loaded-board test, self-test, boundary scan, JTAG
54	Suzette Vandivier, Mark Wahl, Jeff Rearick	First IC Validation of IEEE Std. 1149.6.	ITC	2003	DBLP DOI BibTeX RDF	1149.6, test receiver
50	Bart Vermeulen, Tom Waayers, Sjaak Bakker	Multi-TAP Controller Architecture for Digital System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP
50	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
50	Don Sterba, Andy Halliday, Don McClean	ATPG and diagnostics for boards implementing boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	1149.1, ATPG, diagnostics, boundary scan, JTAG
50	Franc Novak, Anton Biasizzo	Security Extension for IEEE Std 1149.1.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	security, test, boundary-scan
50	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
50	Dilip K. Bhavsar	Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
50	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
50	Colin M. Maunder	A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
45	Francisco R. Fernandes, Ricardo J. Machado 0001, José M. Ferreira 0001, Manuel G. Gericota	Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports.	IOLTS	2012	DBLP DOI BibTeX RDF
45	Jose M. M. Ferreira, Manuel G. O. Gericota, Antonio M. Cardoso	An integrated framework to support remote IEEE 1149.1 / 1149.4 design for test experiments.	Int. J. Online Eng.	2006	DBLP BibTeX RDF
45	Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting	Decentralized BIST for 1149.1 and 1149.5 Based Interconnects.	ED&TC	1996	DBLP DOI BibTeX RDF
41	Saghir A. Shaikh	IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.	ITC	2004	DBLP DOI BibTeX RDF
41	Jeff Rearick, Sylvia Patterson, Krista Dorner	Integrating Boundary Scan into Multi-GHz I/O Circuitry.	ITC	2004	DBLP DOI BibTeX RDF
41	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
41	Stephen K. Sunter, Benoit Nadeau-Dostie	Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.	ITC	2002	DBLP DOI BibTeX RDF
36	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	An Embedded IDDQ Testing Architecture and Technique.	ISQED	2003	DBLP DOI BibTeX RDF	IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
36	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
36	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
36	Kuen-Jong Lee, Cheng-I Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
36	Hong Hao, Kanti Bhabuthmal	Clock controller design in SuperSPARC II microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
36	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
36	Subhasish Mitra, Edward J. McCluskey, Samy Makar	Design for Testability and Testing of IEEE 1149.1 Tap Controller.	VTS	2002	DBLP DOI BibTeX RDF
36	Dave Stang, Ramaswami Dandapani	An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.	ITC	2002	DBLP DOI BibTeX RDF
36	Bart Vermeulen, Tom Waayers, Sjaak Bakker	EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.	ITC	2002	DBLP DOI BibTeX RDF
36	Sungju Park, Taehyung Kim	A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects.	DATE	2000	DBLP DOI BibTeX RDF
36	Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
36	Gustavo R. Alves, José Manuel Martins Ferreira	From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1.	VTS	1999	DBLP DOI BibTeX RDF
36	Najmi T. Jarwala	Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	module test, design-for-testability, boundary-scan
36	Mick Tegethoff, Kenneth P. Parker	IEEE Std 1149.1: Where Are We? Where From Here?	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
27	Bill Eklow, Ben Bennetts	New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).	ETS	2006	DBLP DOI BibTeX RDF
27	Bradford G. Van Treuren, José M. Miranda	Embedded Boundary Scan.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
27	Tom Waayers	An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.	ITC	2003	DBLP DOI BibTeX RDF
27	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	ITC	2002	DBLP DOI BibTeX RDF
27	Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora	A Structured Graphical Tool for Analyzing Boundary Scan Violations.	ITC	2002	DBLP DOI BibTeX RDF
27	W. David Ballew, Lauren M. Streb	Board-level boundary scan: regaining observability with an additional IC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
27	Kenneth P. Parker, Stig Oresjo	A language for describing boundary scan devices.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	boundary scan testability, VHDL
27	Dilip K. Bhavsar	Testing Interconnections to Static RAMs.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
23	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang	Using a single input to support multiple scan chains.	ICCAD	1998	DBLP DOI BibTeX RDF	boundary scan (IEEE 1149.1) and test compaction, test generation, design for testability, scan based design
23	Sebastian Huhn 0001, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler	Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.	DATE	2017	DBLP DOI BibTeX RDF
23	André V. Fidalgo, Andre Couto, Manuel C. Felgueiras, Gustavo R. Alves	Low cost boundary scan controller for didactic applications (IEEE 1149.1).	exp.at	2015	DBLP DOI BibTeX RDF
23	Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi	An off-line MDSI interconnect BIST incorporated in BS 1149.1.	ETS	2014	DBLP DOI BibTeX RDF
23	Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi	BS 1149.1 extensions for an online interconnect fault detection and recovery.	ITC	2012	DBLP DOI BibTeX RDF
23	Reza Nourmandi-Pour, Nafiseh Mousavian, Ahmad Khadem-Zadeh	BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
23	Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume	Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.	3DIC	2011	DBLP DOI BibTeX RDF
23	Tsung-Yen Tsai, Gordon W. Roberts	Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus.	CICC	2011	DBLP DOI BibTeX RDF
23	Reza Nourmandi-Pour, Ahmad Khademzadeh, Amir Masoud Rahmani	An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
23	Christopher J. Clark	iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages.	VTS	2010	DBLP DOI BibTeX RDF
23	C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill	Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins.	ITC	2010	DBLP DOI BibTeX RDF
23	Dave Bonnett	IEEE 1149.1- The Internet of Test.	LATW	2001	DBLP BibTeX RDF
23	Bulent I. Dervisoglu	A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers.	DAC	2001	DBLP DOI BibTeX RDF
23	Steven F. Oakland	Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits.	ITC	2000	DBLP DOI BibTeX RDF
23	Stephen Harrison, Peter Collins, Greg Noeninckx	The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment.	ITC	2000	DBLP DOI BibTeX RDF
23	Farideh Golshan	Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor.	ITC	2000	DBLP DOI BibTeX RDF
23	Yuejian Wu, Paul Soong	Interconnect delay fault testing with IEEE 1149.1.	ITC	1999	DBLP DOI BibTeX RDF
23	Gustavo Ribeiro Alves	Projecto para teste e depuração com base nas arquitecturas 1149.1 e P1149.4		1999	RDF
23	Dilip Bhavsar	A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access.	VLSI Design	1998	DBLP DOI BibTeX RDF
23	Ken Posse	A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault diagnosis, Boundary-Scan, Multichip Module, MCM, interconnect testing, manufacturing defects
23	Lee Whetsel	An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores.	ITC	1997	DBLP DOI BibTeX RDF
23	Harbinder Singh, James Beausang, Girish Patankar	A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator.	ITC	1997	DBLP DOI BibTeX RDF
23	Robert J. Russell	A Method of Extending an 1149.1 Bus for Mixed-Signal Testing.	ITC	1996	DBLP DOI BibTeX RDF
23	Wuudiann Ke, Duy Le, Najmi T. Jarwala	A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus.	ITC	1995	DBLP DOI BibTeX RDF
23	Douglas W. Raymond, D. Eugene Wedge, Philip J. Stringer, Harold W. Ng, Suzanne T. Jennings, Craig T. Pynn, Winsor Soule Jr.	Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICs.	ITC	1995	DBLP DOI BibTeX RDF
23	Carol Pyron, William C. Bruce	Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family.	ITC	1995	DBLP DOI BibTeX RDF
23	Chouki Aktouf, Chantal Robach, A. Marinescu	A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1.	ITC	1995	DBLP DOI BibTeX RDF
23	David J. Cheek, Ramaswami Dandapani	Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures.	ITC	1995	DBLP DOI BibTeX RDF
23	John Andrews	Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test Programs.	ITC	1994	DBLP DOI BibTeX RDF
23	Lee Whetsel	An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures.	ITC	1994	DBLP DOI BibTeX RDF
23	Najmi T. Jarwala	Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules.	ITC	1994	DBLP DOI BibTeX RDF
23	Alfred L. Crouch, Rick Ramus, Colin M. Maunder	Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution.	ITC	1994	DBLP DOI BibTeX RDF
23	John Andrews	Using SCANTM Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test Bus.	ITC	1994	DBLP DOI BibTeX RDF
23	Robert Gage	1149.1 Scan Control Transport Levels.	ITC	1994	DBLP DOI BibTeX RDF
23	Lee Whetsel	An IEEE 1149.1 based voltmeter/oscilloscope in a chip.	VTS	1993	DBLP DOI BibTeX RDF
23	José Manuel Martins Ferreira, Manuel G. Gericota, José L. Ramalho, Gustavo R. Alves	BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution.	ITC	1993	DBLP DOI BibTeX RDF
23	Mick Tegethoff	IEEE 1149.1: How to Justify Implementation.	ITC	1993	DBLP BibTeX RDF
23	Christopher Poirier	IEEE P1149.5 to 1149.1 Data and Protocol Conversion.	ITC	1993	DBLP DOI BibTeX RDF
23	Wayne T. Daniel	IEEE 1149.1 Growing Pains.	ITC	1993	DBLP BibTeX RDF
23	Lee Whetsel	Hierarchically Accessing 1149.1 Applications in a System Environment.	ITC	1993	DBLP DOI BibTeX RDF
23	Mark Royals, Tassos Markas, Nick Kanopoulos	A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
23	Robert C. Zak Jr., Jeffrey V. Hill	An IEEE 1149.1 Compliant Testability Architecture with Internal Scan.	ICCD	1992	DBLP DOI BibTeX RDF
23	Lee Whetsel	A Proposed Method of Accessing 1149.1 in a Backplane Environment.	ITC	1992	DBLP DOI BibTeX RDF
23	John Andrews	IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic.	ITC	1992	DBLP DOI BibTeX RDF
23	Barry Caldwell, Tom Langford	Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study.	ITC	1992	DBLP DOI BibTeX RDF
23	William C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns	Implementing 1149.1 on CMOS Microprocessors.	ITC	1992	DBLP DOI BibTeX RDF
23	Wayne T. Daniel	Design Verification of a High Density Computer Using IEEE 1149.1.	ITC	1992	DBLP DOI BibTeX RDF
23	Steven F. Oakland	Combining IEEE Standard 1149.1 with reduced-pin-count component test.	VTS	1991	DBLP DOI BibTeX RDF
23	Robert Cortez, R. Dandapani, Mike Yeager	Issues of integrating the IEEE Std 1149.1 into a gate array.	VTS	1991	DBLP DOI BibTeX RDF
23	Lee Whetsel	An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip.	ITC	1991	DBLP DOI BibTeX RDF
23	William C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns	Implementing 1149.1 on CMOS Microprocessors.	ITC	1991	DBLP DOI BibTeX RDF