Search results for "ASIC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
112	Kun-Cheng Wu, Yu-Wen Tsai	Structured ASIC, evolution or revolution?	ISPD	2004	DBLP DOI BibTeX RDF	ASIC, structured ASIC
90	A. Richard Newton	Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel).	DAC	1998	DBLP DOI BibTeX RDF
74	Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng	A lithography-friendly structured ASIC design approach.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	ASIC, OPC, lithography
74	Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano	Structured/platform ASIC apprentices: which platform will survive your board room?	DAC	2005	DBLP DOI BibTeX RDF	programmable ASIC platforms, digital design
68	Ashutosh Chakraborty, Anurag Kumar 0002, David Z. Pan	RegPlace: a high quality open-source placement framework for structured ASICs.	DAC	2009	DBLP DOI BibTeX RDF	global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
59	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
59	Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind	Architecting ASIC libraries and flows in nanometer era.	DAC	2003	DBLP DOI BibTeX RDF	nanometer design, libraries, standard cell
59	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
59	R. Reed Taylor, Herman Schmit	Creating a power-aware structured ASIC.	ISLPED	2004	DBLP DOI BibTeX RDF	VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC
52	Raul Camposano	Will the ASIC survive?	SBCCI	2004	DBLP DOI BibTeX RDF
52	C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram	COST Circuit Optimization SysTem in ASIC Library Development Environment.	VLSI Design	1999	DBLP DOI BibTeX RDF
52	Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump	A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
52	Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak	Flexible ASIC: shared masking for multiple media processors.	DAC	2005	DBLP DOI BibTeX RDF	optimization, interconnect, ASIC
46	Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello	Software-friendly HW/SW co-simulation: an industrial case study.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
46	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
46	Srihari Varada, Vitalice K. Oduol, A. Shelat	Data Flow and Buffer Management in Multi-Channel Data Link Controller.	LCN	1999	DBLP DOI BibTeX RDF	TDM networks, Data flow management, ASIC, Buffer management
46	Kaushik De	Test methodology for embedded cores which protects intellectual property.	VTS	1997	DBLP DOI BibTeX RDF	core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
44	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou 0001	Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai	A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
44	Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright	Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.	ISQED	2003	DBLP DOI BibTeX RDF
44	Ranjit Yashwante, Bhalchandra Jahagirdar	IEEE 1394a_2000 Physical Layer ASIC.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
44	Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu	Buffer design and optimization for lut-based structured ASIC design styles.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	structured asic, interconnection, buffer insertion
44	P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar	A highly testable ASIC for telephone signaling.	VLSI Design	1995	DBLP DOI BibTeX RDF	telephone equipment, telecommunication signalling, highly testable ASIC, telephone signaling, online system diagnostic functions, integrated circuit testing, design for testability, fault simulation, application specific integrated circuits, integrated circuit design, functional simulation, digital integrated circuits, telephony
44	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
42	David G. Chinnery, Kurt Keutzer	Closing the power gap between ASIC and custom: an ASIC perspective.	DAC	2005	DBLP DOI BibTeX RDF	power, energy, custom, ASIC, comparison, standard cell
42	David G. Chinnery, Kurt Keutzer	Closing the gap between ASIC and custom: an ASIC perspective.	DAC	2000	DBLP DOI BibTeX RDF	custom, ASIC, comparison, clock frequency, clock speed
40	Asic Q. Chen, Ruian Shi, Xiang Gao, Ricardo Baptista, Rahul G. Krishnan	Structured Neural Networks for Density Estimation and Causal Inference.	CoRR	2023	DBLP DOI BibTeX RDF
40	Asic Q. Chen, Ruian Shi, Xiang Gao, Ricardo Baptista, Rahul G. Krishnan	Structured Neural Networks for Density Estimation and Causal Inference.	NeurIPS	2023	DBLP BibTeX RDF
40	Asic Chen, Arno Jacob-sen	Distributed ledgers and blockchain: concepts and applications.	CASCON	2018	DBLP BibTeX RDF
40	Emran Bajrami, Maida Asic, Emir Cogo, Dino Trnka, Novica Nosovic	Performance comparison of simulated annealing algorithm execution on GPU and CPU.	MIPRO	2012	DBLP BibTeX RDF
40	Branko Kaucic, Teja Asic	Improving introductory programming with Scratch?	MIPRO	2011	DBLP BibTeX RDF
40	Vera V. Kovacevic-Vujcic, Miroslav D. Asic	Stabilization of Interior-Point Methods for Linear Programming.	Comput. Optim. Appl.	1999	DBLP DOI BibTeX RDF
40	Miroslav D. Asic, Vera V. Kovacevic-Vujcic, Mirjana D. Radosavljevic-Nikolic	Asymptotic Behaviour of Karmarkar's Method for Linear Programming.	Math. Program.	1990	DBLP DOI BibTeX RDF
40	Steve Alpern, Miroslav D. Asic	The search value of a network.	Networks	1985	DBLP DOI BibTeX RDF
38	Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen	DSP system integration and prototyping with FPGAS.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
38	Steve Vinoski	RISE++: A Symbolic Environment for Scan-Based Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
38	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
38	Deepak D. Sherlekar	Design considerations for regular fabrics.	ISPD	2004	DBLP DOI BibTeX RDF	structured ASIC, regular fabric
36	Eric Chesters	Role of the verification team throughout the ASIC development life cycle.	DAC	2009	DBLP DOI BibTeX RDF	silicon validation, verification
36	Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall	Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC.	SoCC	2008	DBLP DOI BibTeX RDF
36	Dan Feng 0001, Lanxiang Chen, Lingfang Zeng, Zhongying Niu	FPGA/ASIC based Cryptographic Object Store System.	IAS	2007	DBLP DOI BibTeX RDF
36	Louis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries	Development of on board, highly flexible, Galileo signal generator ASIC.	DATE	2007	DBLP DOI BibTeX RDF
36	Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam	Equivalence Verification of FPGA and Structured ASIC Implementations.	FPL	2007	DBLP DOI BibTeX RDF
36	Zongxing Xie, Thiago Quirino, Mei-Ling Shyu, Shu-Ching Chen	ASIC: Supervised Multi-class Classification using Adaptive Selection of Information Components.	ICSC	2007	DBLP DOI BibTeX RDF
36	Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo	A methodology for FPGA to structured-ASIC synthesis and verification.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
36	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou 0001	Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.	DATE	2006	DBLP DOI BibTeX RDF
36	Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe 0001, Marios C. Papaefthymiou	A 225 MHz resonant clocked ASIC chip.	ISLPED	2003	DBLP DOI BibTeX RDF	adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator
36	Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli	Physical synthesis for ASIC datapath circuits.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
36	Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri	Improvement of ASIC Design Processes.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
36	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
36	Gyung-Hae Han, Hwa-Young Yi, Bum-Suk Go, Dong-Geun Lee, In-Haeng Cho, Dong-Il Oh	A new ASIC for washer controller.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
36	D. Craig Wilcox, Lyndon G. Pierson, Perry J. Robertson, Edward L. Witzke, Karl Gass	A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond.	CHES	1999	DBLP DOI BibTeX RDF
36	Stefan Sjöholm, Lennart Lindh	The need for Co-simulation in ASIC-verification.	EUROMICRO	1997	DBLP DOI BibTeX RDF
36	Igor Dantas dos Santos Miranda, Ana Isabela Araújo Cunha	ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.	SBCCI	2009	DBLP DOI BibTeX RDF	neural network arithmetic, neuroprocessor, ASIC
36	Andrew Chang 0001, William J. Dally	Explaining the gap between ASIC and custom power: a custom perspective.	DAC	2005	DBLP DOI BibTeX RDF	custom circuits, normalized metrics, low power, energy efficiency, ASIC, EDA, technology scaling
36	Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda	Design methodology and tools for NEC electronics' structured ASIC ISSP.	ISPD	2004	DBLP DOI BibTeX RDF	ISSP, placement, structured ASIC, regular fabric
36	Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger	An ASIC Implementation of the AES SBoxes.	CT-RSA	2002	DBLP DOI BibTeX RDF	standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
36	Arun K. Majumdar, Nirav Patel	Design of an ASIC for Straight Line Detection in an Image.	VLSI Design	2000	DBLP DOI BibTeX RDF	Hough Transform, CORDIC, ASIC Design
36	Tony Tsang	A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications.	VLSI Design	1998	DBLP DOI BibTeX RDF	circuit technique, VLSI, compiler, ASIC, deep sub-micron, ROM
36	Miodrag Potkonjak, Wayne H. Wolf	Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.	ICCAD	1995	DBLP DOI BibTeX RDF	allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
30	Herman Schmit, Amit Gupta, Radu Ciobanu	Placement challenges for structured ASICs.	ISPD	2008	DBLP DOI BibTeX RDF	field programmable gate arrays, placement, structured ASICs
30	Gin-Der Wu, Zhen-Wei Zhu	Chip Design of LPC-cepstrum for Speech Recognition.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
30	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
30	Steve Scott, Dennis Abts, John Kim, William J. Dally	The BlackWidow High-Radix Clos Network.	ISCA	2006	DBLP DOI BibTeX RDF
30	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
30	Lanxiang Chen, Dan Feng 0001, Lingfang Zeng, Yu Zhang	A Direction to Avoid Re-encryption in Cryptographic File Sharing.	NPC	2007	DBLP DOI BibTeX RDF	FPGA, access control, ASIC, cryptographic file system
30	Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy 0001	Synthesis of application-specific highly efficient multi-mode cores for embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system
30	Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer	Efficient AES Implementations on ASICs and FPGAs.	AES Conference	2004	DBLP DOI BibTeX RDF	FPGA, Advanced Encryption Standard (AES), ASIC
30	R. Reed Taylor, Herman Schmit	Enabling energy efficiency in via-patterned gate array devices.	DAC	2004	DBLP DOI BibTeX RDF	VPGA, optimization, low-power, power, voltage scaling, structured ASIC
30	David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee 0002, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder	Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited).	ISQED	2002	DBLP DOI BibTeX RDF	radiation tolerance, CCGA, reliability, DSP, ASIC, satellite communications, qualification
30	B. Suresh, Biswadeep Chaterjee, R. Harinath	Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability
30	Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu	Functional Verification of Large ASICs.	DAC	1998	DBLP DOI BibTeX RDF	ASIC verification, simulation, emulation
30	Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali	A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed
29	Yuqing Wu, Sofia Brenes, Tejas Totade, Shijin Joshua, Dhaval Damani, Michel Salim	ASIC: algebra-based structural index comparison.	CIKM	2009	DBLP DOI BibTeX RDF	XPath algebra, structural index
29	Kamil Erkan Kabak, Cathal Heavey, Vincent Corbett	Analysis of multiple process flows in an ASIC fab with a detailed photolithography area model.	WSC	2008	DBLP DOI BibTeX RDF
29	Huiju Cheng, Howard M. Heys	Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection.	ISCAS	2008	DBLP DOI BibTeX RDF
29	Adarsha Rao, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan	Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.	ASAP	2008	DBLP DOI BibTeX RDF
29	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
29	Katherine Compton, Scott Hauck	Automatic Design of Area-Efficient Configurable ASIC Cores.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	logic design and synthesis, Reconfigurable architecture
29	Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri	A Structured ASIC Design Approach Using Pass Transistor Logic.	ISCAS	2007	DBLP DOI BibTeX RDF
29	Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer	Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
29	Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch	Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.	ASP-DAC	2006	DBLP DOI BibTeX RDF
29	Wayne P. Burleson, Sheng Xu	Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.	MSE	2005	DBLP DOI BibTeX RDF
29	Hugo Hedberg, Joachim Neves Rodrigues, Fredrik Kristensen, Henrik Svensson, Matthias Kamuf, Viktor Öwall	Teaching Digital ASIC Design to Students with Heterogeneous Previous Knowledge.	MSE	2005	DBLP DOI BibTeX RDF
29	Qiu-Zhong Wu, Yi-He Sun	An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization.	ESTIMedia	2005	DBLP DOI BibTeX RDF
29	Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
29	T. S. Ganesh, T. S. B. Sudarshan	ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives.	ITCC (1)	2005	DBLP DOI BibTeX RDF
29	Ulrich Heinkel, Claus Mayer, Charles F. Webb, Hans Sahm, Werner Haas 0003, Stefan Gossens	An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs.	SAMOS	2004	DBLP DOI BibTeX RDF
29	Chul Kim, Mike Myung-Ok Lee, Byung-Lok Cho, Kamran Eshraghian	SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC.	DELTA	2004	DBLP DOI BibTeX RDF
29	Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou	Energy Recovering ASIC Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
29	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
29	Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada	Whither (or wither?) ASIC handoff?	DAC	2002	DBLP DOI BibTeX RDF
29	Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon	Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
29	Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto	Clock skew reduction in ASIC logic design: a methodology for clock tree management.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
29	Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens	A Parallel ASIC Architecture for Efficient Fractal Image Coding.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
29	Marc Campbell	Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications.	LCTES	1998	DBLP DOI BibTeX RDF
29	Ian Gibson, Chris Amies	Practical concurrent ASIC and system design and verification.	ED&TC	1997	DBLP DOI BibTeX RDF
29	Klaus D. Müller-Glaser, Jürgen Bortolazzi	An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules.	DAC	1989	DBLP DOI BibTeX RDF
29	Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung 0001, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni	Pushing ASIC performance in a power envelope.	DAC	2003	DBLP DOI BibTeX RDF	low-power, ASIC, high-performance, design optimization
29	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP