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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1444 occurrences of 813 keywords
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Results
Found 4301 publication records. Showing 4296 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
112 | Kun-Cheng Wu, Yu-Wen Tsai |
Structured ASIC, evolution or revolution? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 103-106, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ASIC, structured ASIC |
90 | A. Richard Newton |
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 501, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
74 | Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng |
A lithography-friendly structured ASIC design approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 315-320, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ASIC, OPC, lithography |
74 | Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano |
Structured/platform ASIC apprentices: which platform will survive your board room? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 887-888, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
programmable ASIC platforms, digital design |
68 | Ashutosh Chakraborty, Anurag Kumar 0002, David Z. Pan |
RegPlace: a high quality open-source placement framework for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 442-447, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
global placement, regular ASIC, FPGA, placement, legalization, structured ASIC |
59 | Ashutosh Chakraborty, David Z. Pan |
PASAP: power aware structured ASIC placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 395-400, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
structured ASICS, low power, placement, regular fabrics |
59 | Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind |
Architecting ASIC libraries and flows in nanometer era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 776-781, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nanometer design, libraries, standard cell |
59 | David Sheldon, Frank Vahid |
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 155-160, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC |
59 | R. Reed Taylor, Herman Schmit |
Creating a power-aware structured ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 74-77, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC |
52 | Raul Camposano |
Will the ASIC survive? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 5, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram |
COST Circuit Optimization SysTem in ASIC Library Development Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 460-463, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump |
A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(3), pp. 261-273, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
52 | Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak |
Flexible ASIC: shared masking for multiple media processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 909-914, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
optimization, interconnect, ASIC |
46 | Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello |
Software-friendly HW/SW co-simulation: an industrial case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 100-105, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan |
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 127-136, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC |
46 | Srihari Varada, Vitalice K. Oduol, A. Shelat |
Data Flow and Buffer Management in Multi-Channel Data Link Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 26th Conference on Local Computer Networks, Lowell, Massachusetts, USA, 17-20 October, 1999, pp. 132-141, 1999, IEEE Computer Society, 0-7695-0309-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
TDM networks, Data flow management, ASIC, Buffer management |
46 | Kaushik De |
Test methodology for embedded cores which protects intellectual property. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 2-9, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology |
44 | Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou 0001 |
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 447-455, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai |
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 280-285, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright |
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 405-409, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Ranjit Yashwante, Bhalchandra Jahagirdar |
IEEE 1394a_2000 Physical Layer ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 795-800, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu |
Buffer design and optimization for lut-based structured ASIC design styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 377-380, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
structured asic, interconnection, buffer insertion |
44 | P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar |
A highly testable ASIC for telephone signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 183-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
telephone equipment, telecommunication signalling, highly testable ASIC, telephone signaling, online system diagnostic functions, integrated circuit testing, design for testability, fault simulation, application specific integrated circuits, integrated circuit design, functional simulation, digital integrated circuits, telephony |
44 | Mark Genoe, Paul Vanoostende, Geert van Wauwe |
On the use of VHDL-based behavioral synthesis for telecom ASIC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 96-103, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities |
42 | David G. Chinnery, Kurt Keutzer |
Closing the power gap between ASIC and custom: an ASIC perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 275-280, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
power, energy, custom, ASIC, comparison, standard cell |
42 | David G. Chinnery, Kurt Keutzer |
Closing the gap between ASIC and custom: an ASIC perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 637-642, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
custom, ASIC, comparison, clock frequency, clock speed |
40 | Asic Q. Chen, Ruian Shi, Xiang Gao, Ricardo Baptista, Rahul G. Krishnan |
Structured Neural Networks for Density Estimation and Causal Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.02221, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
40 | Asic Q. Chen, Ruian Shi, Xiang Gao, Ricardo Baptista, Rahul G. Krishnan |
Structured Neural Networks for Density Estimation and Causal Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NeurIPS ![In: Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, NeurIPS 2023, New Orleans, LA, USA, December 10 - 16, 2023., 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
40 | Asic Chen, Arno Jacob-sen |
Distributed ledgers and blockchain: concepts and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 28th Annual International Conference on Computer Science and Software Engineering, CASCON 2018, Markham, Ontario, Canada, October 29-31, 2018., pp. 413-414, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
40 | Emran Bajrami, Maida Asic, Emir Cogo, Dino Trnka, Novica Nosovic |
Performance comparison of simulated annealing algorithm execution on GPU and CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: 2012 Proceedings of the 35th International Convention, MIPRO 2012, Opatija, Croatia, May 21-25, 2012, pp. 1785-1788, 2012, IEEE, 978-1-4673-2577-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
40 | Branko Kaucic, Teja Asic |
Improving introductory programming with Scratch? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: MIPRO, 2011 Proceedings of the 34th International Convention, Opatija, Croatia, 23-27 May, 2011, pp. 1095-1100, 2011, IEEE, 978-1-4577-0996-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Vera V. Kovacevic-Vujcic, Miroslav D. Asic |
Stabilization of Interior-Point Methods for Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Optim. Appl. ![In: Comput. Optim. Appl. 14(3), pp. 331-346, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Miroslav D. Asic, Vera V. Kovacevic-Vujcic, Mirjana D. Radosavljevic-Nikolic |
Asymptotic Behaviour of Karmarkar's Method for Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 46, pp. 173-190, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
40 | Steve Alpern, Miroslav D. Asic |
The search value of a network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks ![In: Networks 15(2), pp. 229-238, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
38 | Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen |
DSP system integration and prototyping with FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 6(2), pp. 155-172, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
38 | Steve Vinoski |
RISE++: A Symbolic Environment for Scan-Based Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(2), pp. 56-68, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
38 | Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
Understanding sources of inefficiency in general-purpose chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 37-47, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance |
38 | Deepak D. Sherlekar |
Design considerations for regular fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 97-102, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
structured ASIC, regular fabric |
36 | Eric Chesters |
Role of the verification team throughout the ASIC development life cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 216-219, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
silicon validation, verification |
36 | Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall |
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 55-58, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Dan Feng 0001, Lanxiang Chen, Lingfang Zeng, Zhongying Niu |
FPGA/ASIC based Cryptographic Object Store System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: Proceedings of the Third International Symposium on Information Assurance and Security, IAS 2007, August 29-31, 2007, Manchester, United Kingdom, pp. 267-272, 2007, IEEE Computer Society, 978-0-7695-2876-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Louis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries |
Development of on board, highly flexible, Galileo signal generator ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 679-683, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam |
Equivalence Verification of FPGA and Structured ASIC Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 423-428, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Zongxing Xie, Thiago Quirino, Mei-Ling Shyu, Shu-Ching Chen |
ASIC: Supervised Multi-class Classification using Adaptive Selection of Information Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSC ![In: Proceedings of the First IEEE International Conference on Semantic Computing (ICSC 2007), September 17-19, 2007, Irvine, California, USA, pp. 527-534, 2007, IEEE Computer Society, 0-7695-2997-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo |
A methodology for FPGA to structured-ASIC synthesis and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 64-69, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou 0001 |
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 618-623, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe 0001, Marios C. Papaefthymiou |
A 225 MHz resonant clocked ASIC chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 48-53, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator |
36 | Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli |
Physical synthesis for ASIC datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 365-368, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri |
Improvement of ASIC Design Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 105-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Mely Chen Chi, Shih-Hsu Huang |
A Reliable Clock Tree Design Methodology for ASIC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 269-274, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Clock tree design, Clock tree synthesis |
36 | Gyung-Hae Han, Hwa-Young Yi, Bum-Suk Go, Dong-Geun Lee, In-Haeng Cho, Dong-Il Oh |
A new ASIC for washer controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 485-488, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | D. Craig Wilcox, Lyndon G. Pierson, Perry J. Robertson, Edward L. Witzke, Karl Gass |
A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems, First International Workshop, CHES'99, Worcester, MA, USA, August 12-13, 1999, Proceedings, pp. 37-48, 1999, Springer, 3-540-66646-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Stefan Sjöholm, Lennart Lindh |
The need for Co-simulation in ASIC-verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 331-335, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Igor Dantas dos Santos Miranda, Ana Isabela Araújo Cunha |
ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
neural network arithmetic, neuroprocessor, ASIC |
36 | Andrew Chang 0001, William J. Dally |
Explaining the gap between ASIC and custom power: a custom perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 281-284, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
custom circuits, normalized metrics, low power, energy efficiency, ASIC, EDA, technology scaling |
36 | Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda |
Design methodology and tools for NEC electronics' structured ASIC ISSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 90-96, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ISSP, placement, structured ASIC, regular fabric |
36 | Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger |
An ASIC Implementation of the AES SBoxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2002, The Cryptographer's Track at the RSA Conference, 2002, San Jose, CA, USA, February 18-22, 2002, Proceedings, pp. 67-78, 2002, Springer, 3-540-43224-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic |
36 | Arun K. Majumdar, Nirav Patel |
Design of an ASIC for Straight Line Detection in an Image. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 128-133, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Hough Transform, CORDIC, ASIC Design |
36 | Tony Tsang |
A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 490-494, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
circuit technique, VLSI, compiler, ASIC, deep sub-micron, ROM |
36 | Miodrag Potkonjak, Wayne H. Wolf |
Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 446-451, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation |
30 | Herman Schmit, Amit Gupta, Radu Ciobanu |
Placement challenges for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 84-86, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
field programmable gate arrays, placement, structured ASICs |
30 | Gin-Der Wu, Zhen-Wei Zhu |
Chip Design of LPC-cepstrum for Speech Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 11-13 July 2007, Melbourne, Australia, pp. 43-47, 2007, IEEE Computer Society, 0-7695-2841-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Yan Zhang, Jussi Roivainen, Aarne Mämmelä |
Clock-Gating in FPGAs: A Novel and Comparative Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 584-590, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Steve Scott, Dennis Abts, John Kim, William J. Dally |
The BlackWidow High-Radix Clos Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 16-28, 2006, IEEE Computer Society, 0-7695-2608-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1436-1448, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems |
30 | Lanxiang Chen, Dan Feng 0001, Lingfang Zeng, Yu Zhang |
A Direction to Avoid Re-encryption in Cryptographic File Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings, pp. 375-383, 2007, Springer, 978-3-540-74783-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, access control, ASIC, cryptographic file system |
30 | Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy 0001 |
Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(1), pp. 168-188, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system |
30 | Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer |
Efficient AES Implementations on ASICs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AES Conference ![In: Advanced Encryption Standard - AES, 4th International Conference, AES 2004, Bonn, Germany, May 10-12, 2004, Revised Selected and Invited Papers, pp. 98-112, 2004, Springer, 3-540-26557-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Advanced Encryption Standard (AES), ASIC |
30 | R. Reed Taylor, Herman Schmit |
Enabling energy efficiency in via-patterned gate array devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 874-878, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VPGA, optimization, low-power, power, voltage scaling, structured ASIC |
30 | David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee 0002, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder |
Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 479-486, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
radiation tolerance, CCGA, reliability, DSP, ASIC, satellite communications, qualification |
30 | B. Suresh, Biswadeep Chaterjee, R. Harinath |
Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 512-517, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability |
30 | Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu |
Functional Verification of Large ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 650-655, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ASIC verification, simulation, emulation |
30 | Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali |
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 155-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed |
29 | Yuqing Wu, Sofia Brenes, Tejas Totade, Shijin Joshua, Dhaval Damani, Michel Salim |
ASIC: algebra-based structural index comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIKM ![In: Proceedings of the 18th ACM Conference on Information and Knowledge Management, CIKM 2009, Hong Kong, China, November 2-6, 2009, pp. 2111-2112, 2009, ACM, 978-1-60558-512-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
XPath algebra, structural index |
29 | Kamil Erkan Kabak, Cathal Heavey, Vincent Corbett |
Analysis of multiple process flows in an ASIC fab with a detailed photolithography area model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 2008 Winter Simulation Conference, Global Gateway to Discovery, WSC 2008, InterContinental Hotel, Miami, Florida, USA, December 7-10, 2008, pp. 2185-2193, 2008, WSC, 978-1-4244-2708-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Huiju Cheng, Howard M. Heys |
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2921-2924, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Adarsha Rao, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan |
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 287-292, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 276-285, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Katherine Compton, Scott Hauck |
Automatic Design of Area-Efficient Configurable ASIC Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(5), pp. 662-672, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic design and synthesis, Reconfigurable architecture |
29 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
A Structured ASIC Design Approach Using Pass Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1787-1790, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer |
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 234-238, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch |
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 176-181, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Wayne P. Burleson, Sheng Xu |
Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 3-4, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Hugo Hedberg, Joachim Neves Rodrigues, Fredrik Kristensen, Henrik Svensson, Matthias Kamuf, Viktor Öwall |
Teaching Digital ASIC Design to Students with Heterogeneous Previous Knowledge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 15-16, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Qiu-Zhong Wu, Yi-He Sun |
An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 67-72, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe |
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5621-5624, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | T. S. Ganesh, T. S. B. Sudarshan |
ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 580-585, 2005, IEEE Computer Society, 0-7695-2315-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ulrich Heinkel, Claus Mayer, Charles F. Webb, Hans Sahm, Werner Haas 0003, Stefan Gossens |
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 98-107, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Chul Kim, Mike Myung-Ok Lee, Byung-Lok Cho, Kamran Eshraghian |
SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 251-254, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou |
Energy Recovering ASIC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 133-138, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Nikhil Jayakumar, Sunil P. Khatri |
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 128-133, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
standby current, leakage current, standard cells, MTCMOS |
29 | Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada |
Whither (or wither?) ASIC handoff? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 317-318, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon |
Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 263-266, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto |
Clock skew reduction in ASIC logic design: a methodology for clock tree management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4), pp. 344-356, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens |
A Parallel ASIC Architecture for Efficient Fractal Image Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(2), pp. 97-113, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Marc Campbell |
Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, Montreal, Canada, June 1998, Proceedings, pp. 261, 1998, Springer, 3-540-65075-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Ian Gibson, Chris Amies |
Practical concurrent ASIC and system design and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 532-536, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Klaus D. Müller-Glaser, Jürgen Bortolazzi |
An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 472-477, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung 0001, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni |
Pushing ASIC performance in a power envelope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 788-793, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power, ASIC, high-performance, design optimization |
29 | Kurt Keutzer, Sharad Malik, A. Richard Newton |
From ASIC to ASIP: The Next Design Discontinuity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 84-90, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP |
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