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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 41568 occurrences of 12452 keywords
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Results
Found 61775 publication records. Showing 61772 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Jian Liu, Rafic Z. Makki |
Power supply current detectability of SRAM defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 367-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect |
69 | Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001 |
An approach to dynamic power consumption current testing of CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 95-100, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current |
63 | Radu Muresan, Catherine H. Gebotys |
Instantaneous current modeling in a complex VLIW processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 415-451, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model |
60 | Bartomeu Alorda, Vincent Canals, Jaume Segura 0001 |
A Two-Level Power-Grid Model for Transient Current Testing Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 543-552, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
current based testing, off-chip current monitors, built-in current monitors, power grid modeling, transient current |
60 | Cheng-Ping Wang, Chin-Long Wey |
Test Generation Of Analog Switched-Current Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 276-281, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults |
55 | Bartomeu Alorda, Jaume Segura 0001 |
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 178-182, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Current based testing, off-chip current monitors, built-in current monitors, power grid modeling, transient current |
55 | Keith A. Bartels, Jay L. Fisher |
Multifrequency eddy current image processing techniques for nondestructive evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 486-489, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
eddy current testing, nondestructive evaluation, multifrequency eddy current image processing, materials evaluation, eddy current images, image formation physics, eddy current testing, complex valued images, SNR maximization, four-frequency processing, algorithm, image sequences, image sequence, signal-to-noise ratio, experimental data |
52 | Yolanda Lechuga, Román Mozuelos, Miguel Angel Allende, Mar Martínez, Salvador Bracho |
Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 583-598, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
transient current test, fault detection, built-in current sensor, supply current monitoring |
49 | Jan Jerabek, Kamil Vrba |
RF Pure Current-Mode Filters using Current Mirrors and Inverters. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
PWC ![In: Personal Wireless Communications, The 12th IFIP International Conference on Personal Wireless Communications (PWC 2007), Prague, Czech Republic, September 2007, pp. 545-556, 2007, Springer, 978-0-387-74158-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pure current mode, current mirror, current inverter, CMI, GCMI, frequency filter |
47 | Bartomeu Alorda, Sebastià A. Bota, Jaume Segura 0001 |
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 177-182, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Current based testing, built-in current monitors, high-speed measurements, transient current |
47 | Shyang-Tai Su, Rafic Z. Makki |
Testing of static random access memories by monitoring dynamic power supply current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 265-278, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Current-testable design, dynamic current monitors, dynamic power supply current, pattern sensitivity, fault modeling |
44 | Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee |
Built-in current sensor designs based on the bulk-driven technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 384-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement |
43 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 27-36, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits |
43 | Jason P. Hurst, Adit D. Singh |
A differential built-in current sensor design for high speed IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 419-423, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices |
40 | Shangquan Liang, Minglun Gao, Yong-Sheng Yin, Honghui Deng |
A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 111-114, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell |
39 | Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija |
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 724-732, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Norbert Herencsar, Kamil Vrba |
Tunable Current-Mode Multifunction Filter Using Universal Current Conveyors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 1-6, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
tunable filter, multifunction filter, Universal Current Conveyor, simulation model UCC, current-mode circuit |
39 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 145-150, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Current Based Diagnosis, Current Signatures, I_DDQ, Very Low Voltage, CMOS, Bridging Defect |
38 | Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho |
Iddt testing of continuous-time filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 101-107, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits |
38 | Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija |
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10), pp. 3038-3049, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic |
CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998, pp. 349-352, 1998, IEEE, 0-7803-5008-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | K. Wayne Current |
Current-mode CMOS multiple-valued logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(2), pp. 95-107, February 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
38 | K. Wayne Current |
Multiple Valued Logic: Current-Mode CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 23rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1993, Sacramento, California, USA, May 24-27, 1993, Proceedings, pp. 176-181, 1993, IEEE Computer Society, 0-8186-3350-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
38 | K. Wayne Current |
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 22nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1992, Sendai, Japan, May 27-29, 1992, Proceedings, pp. 229-234, 1992, IEEE Computer Society, 0-8186-2680-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
38 | K. Wayne Current, M. E. Hurlston |
A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 21st International Symposium on Multiple-Valued Logic, ISMVL 1991, Victoria, BC, Canada, May 26-29, 1991, pp. 196-202, 1991, IEEE Computer Society, 0-8186-2145-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
38 | Yongjian Brandon Guo, K. Wayne Current |
Voltage Comparator Circuits for Multiple-Valued CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 67-75, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
voltage comparator, MVL, low-power, CMOS |
38 | Yehya H. Ghallab, Wael M. Badawy |
A Novel pH Sensor Current Mode Read-Out Circuit Using Operational Floating Current Conveyor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2004 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2004), 25-27 August 2004, Banff, Alberta, Canada, pp. 262-265, 2004, IEEE Computer Society, 0-7695-2189-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits |
37 | Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley |
Dynamic current modeling at the instruction level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 95-100, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
current and power measurement in a processor, dynamic instruction-level current model |
37 | Suwon Lee, Sung-Hun Lim |
Operational Characteristics of Intelligent Dual-Reactor with Current Controlled Inverter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part I, pp. 459-464, 2005, Springer, 3-540-28894-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-reactor, current controlled inverter, fault current, reactive power |
37 | Jian Liu, Rafic Z. Makki, Ayman I. Kayssi |
Dynamic Power Supply Current Testing of CMOS SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 499-511, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
transient power supply current (i DDT), transient current sensor, disturb fault, CMOS SRAM |
36 | Ivo Lattenberg, Kamil Vrba |
Low Input-Impedance Current-Mirror for High-Speed Data Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN ![In: Sixth International Conference on Networking (ICN 2007), 22-28 April 2007, Sainte-Luce, Martinique, France, pp. 72, 2007, IEEE Computer Society, 978-0-7695-2805-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
current mirror, signal processing, current mode |
36 | Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern 0001, Jaume Segura 0001, Miquel Roca 0001, Eugenio García |
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(5), pp. 597-603, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
oscillation test, analog test, Built-In Current Sensor, current test |
34 | Jan Jerabek, Kamil Vrba |
Novel Universal Filter Using Only Two Current Active Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 285-289, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
current follower, MCMI, pure current mode, universal filter, frequency filter |
34 | Chun-Lung Hsu |
Control and Observation Structure for Analog Circuits with Current Test Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 39-44, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
current store cell (CSC), controllability, observability, analog circuit, current-mode |
34 | Jens Lienig, Goeran Jerke, Thorsten Adler |
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 372-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design |
33 | David Kubánek, Kamil Vrba |
Second-Order State-Variable Filter with Current Operational Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 57-61, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Current operational amplifier, Current mode, Active filter |
33 | Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz |
Leakage current reduction by new technique in standby mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 158-161, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
subthreshold current, low power, leakage current, digital integrated circuits, static power |
33 | Yehya H. Ghallab, Wael M. Badawy, Karan V. I. S. Kaler |
A Novel PH Sensor Using Differential ISFET Current Mode Read-Out Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2003 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2003), 20-23 July 2003, Banff, Alberta, Canada, pp. 255-, 2003, IEEE Computer Society, 0-7695-1947-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits |
33 | Alvernon Walker, Algernon P. Henry, Parag K. Lala |
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 272-280, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current |
33 | Claude Thibeault |
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 80-87, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current |
32 | Goonmeet Bajaj, Sean Current, Daniel Schmidt, Bortik Bandyopadhyay, Christopher W. Myers, Srinivasan Parthasarathy 0001 |
Knowledge Gaps: A Challenge for Agent-Based Automatic Task Completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Top. Cogn. Sci. ![In: Top. Cogn. Sci. 14(4), pp. 780-799, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
32 | Sean Current, Yuntian He, Saket Gurukar, Srinivasan Parthasarathy 0001 |
FairMod: Fair Link Prediction and Recommendation via Graph Modification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2201.11596, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
32 | Sean Current, Yuntian He, Saket Gurukar, Srinivasan Parthasarathy 0001 |
FairEGM: Fair Link Prediction and Recommendation via Emulated Graph Modification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EAAMO ![In: Equity and Access in Algorithms, Mechanisms, and Optimization, EAAMO 2022, Arlington, VA, USA, October 6-9, 2022, pp. 3:1-3:14, 2022, ACM, 978-1-4503-9477-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
32 | Adrienne C. Kinney, Sean Current, Joceline Lega |
Aedes-AI: Neural Network Models of Mosquito Abundance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.10771, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
32 | Adrienne C. Kinney, Sean Current, Joceline Lega |
Aedes-AI: Neural network models of mosquito abundance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLoS Comput. Biol. ![In: PLoS Comput. Biol. 17(11), 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Luís Santos 0001, João Manuel Coutinho-Rodrigues, John R. Current |
An improved heuristic for the capacitated arc routing problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 36(9), pp. 2632-2637, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | M.-G. Yoon, John R. Current |
The hub location and network design problem with fixed and variable arc costs: formulation and dual-based solution heuristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Oper. Res. Soc. ![In: J. Oper. Res. Soc. 59(1), pp. 80-89, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews |
A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 1(2), pp. 105-115, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Akio Imai, Etsuko Nishimura, John R. Current |
A Lagrangian relaxation-based heuristic for the vehicle routing with full container load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. J. Oper. Res. ![In: Eur. J. Oper. Res. 176(1), pp. 87-105, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews |
A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2005 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2005), 24-27 July 2005, Banff, Alberta, Canada, pp. 153-158, 2005, IEEE Computer Society, 0-7695-2398-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Yongjian Brandon Guo, K. Wayne Current |
Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Multiple Valued Log. Soft Comput. ![In: J. Multiple Valued Log. Soft Comput. 10(3), pp. 225-260, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
32 | James W. George, Charles S. Revelle, John R. Current |
The Maximum Utilization Subtree Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 110(1-4), pp. 133-151, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Horst A. Eiselt, John R. Current |
Special issue on location analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 29(6), 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current |
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 460-463, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija |
Partitioned Branch Condition Resolution Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000, pp. 35-40, 2000, IEEE Computer Society, 0-7695-0843-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
32 | Dan Olson, K. Wayne Current |
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 371-376, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
MVL Hardware, Ternary Addition, MVL Structure, SUS-LOC |
32 | K. Wayne Current |
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 377-381, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
quaternary, memory, circuit, latch |
32 | João Manuel Coutinho-Rodrigues, João C. N. Clímaco, John R. Current |
An interactive bi-objective shortest path approach: searching for unsupported nondominated solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 26(8), pp. 789-798, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Charles A. Weber, John R. Current, Anand Desai |
Non-cooperative negotiation strategies for vendor selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. J. Oper. Res. ![In: Eur. J. Oper. Res. 108(1), pp. 208-223, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | John R. Current, Samuel Ratick, Charles S. Revelle |
Dynamic facility location when the total number of facilities is uncertain: A decision analysis approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. J. Oper. Res. ![In: Eur. J. Oper. Res. 110(3), pp. 597-609, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current |
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997, Monterey, California, USA, August 18-20, 1997, pp. 323-327, 1997, ACM, 0-89791-903-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic |
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 86-91, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | James F. Parker, K. Wayne Current, Stephen H. Lewis |
A CMOS continuous-time NTSC-to-color-difference decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(12), pp. 1524-1532, December 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current |
Memory Circuits for Multiple-Valued Logic Voltage Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 52-57, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits |
32 | John R. Current, Hasan Pirkul, Erik Rolland |
Efficient Algorithms for Solving the Shortest Covering Path Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Transp. Sci. ![In: Transp. Sci. 28(4), pp. 317-327, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Wei-Shang Chu, K. Wayne Current |
Quaternary Multiplier Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 24th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1994, Boston, Massachusetts, USA, May 25-27, 1994, Proceedings, pp. 15-18, 1994, IEEE Computer Society, 0-8186-5650-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, James F. Parker, Wes Hardaker |
Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2090-2093, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
32 | Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi |
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 2(4), pp. 347-360, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
32 | Hasan Pirkul, John R. Current, Vaidyanathan Nagarajan |
The Hierarchical Network Design Problem: A New Formulation and Solution Procedures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Transp. Sci. ![In: Transp. Sci. 25(3), pp. 175-182, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
32 | J. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu |
A new VLSI architecture for real-time control of robot manipulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: Proceedings of the 1991 IEEE International Conference on Robotics and Automation, Sacramento, CA, USA, 9-11 April 1991, pp. 1828-1835, 1991, IEEE Computer Society, 0-8186-2163-X. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
32 | John R. Current, Charles S. Revelle, Jared L. Cohon |
An interactive approach to identify the best compromise solution for two objective shortest path problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 17(2), pp. 187-198, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi |
An evaluation of Radon transform computations using DSP chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 3(2), pp. 63-74, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh |
A VLSI architecture for two-dimensional Radon transform computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1990 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '90, Albuquerque, New Mexico, USA, April 3-6, 1990, pp. 933-936, 1990, IEEE. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current |
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 168-173, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | John R. Current, David A. Schilling |
The Covering Salesman Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Transp. Sci. ![In: Transp. Sci. 23(3), pp. 208-213, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain 0002 |
An architecture for region boundary extraction in raster scan images suitable for VLSI implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 2(4), pp. 193-214, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain 0002, K. Wayne Current, Paul J. Hurst |
A Radon transform computer for multidimensional signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '89, Glasgow, Scotland, May 23-26, 1989, pp. 1457-1459, 1989, IEEE. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | John R. Current |
The Design of a Hierarchical Transportation Network with Transshipment Facilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Transp. Sci. ![In: Transp. Sci. 22(4), pp. 270-277, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | J. R. Parkhurst, K. Wayne Current, Anil K. Jain 0002, J. E. Grishaw |
A unified DCT/IDCT architecture for VLSI implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '88, New York, New York, USA, April 11-14, 1988, pp. 1993-1996, 1988, IEEE. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | James L. Mangin, K. Wayne Current |
Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(2), pp. 157-161, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
32 | John R. Current |
Discrete computational structures, second edition, By Robert R. Korfhage, Academic Press, Inc., Orlando, FI, 1984, 360 pp. Price $35.00. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks ![In: Networks 16(4), pp. 444-445, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
32 | Stephen B. Haley, K. Wayne Current |
Response change in linearized circuits and systems: Computational algorithms and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 73(1), pp. 5-24, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
32 | Jared L. Cohon, Charles S. Revelle, John R. Current, Thomas Eagles, Russell C. Eberhart, Richard L. Church |
Application of a multiobjective facility location model to power plant siting in a six-state region of the U.S. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 7(1-2), pp. 107-123, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current |
High Density Integrated Computing Circuitry with Multiple Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(2), pp. 191-195, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current |
A High Data-Rate Digital Output Correlator Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(5), pp. 403-405, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
Digital correlators, latched quaternary threshold logic full adders, multiple valued logic, threshold logic, parallel counters |
32 | K. Wayne Current |
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(5), pp. 400-403, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
quaternary threshold logic full adders, Multiple-valued logic, threshold logic, parallel counters |
32 | K. Wayne Current, Douglas A. Mow |
Implementing Parallel Counters with Four-Valued Threshold Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(3), pp. 200-204, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
Four-valved logic full adders, multivalued logic, threshold logic, parallel counters |
32 | K. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh |
A high data rate, low power all-digital correlation circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '79, Washington, D. C., USA, April 2-4, 1979, pp. 859-862, 1979, IEEE. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Douglas A. Mow |
Parallel counter design using four-valued threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '78, Tulsa, Oklahoma, USA, April 10-12, 1978, pp. 796-799, 1978, IEEE. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
32 | K. Wayne Current, Douglas A. Mow |
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 187, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
32 | K. Wayne Current, Douglas A. Mow |
Four-valued threshold logic full adder circuit implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 95-100, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
31 | Genival Mariano de Araujo, Heider Marconi G. Madureira, José Camargo da Costa |
Design and characterization of a 0.35 micron CMOS voltage-to-current converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage-to-current converter, system on chip, current reference |
31 | David Kubánek, Kamil Vrba |
Second-Order Multifunction Filters with Current Operational Amplifiers. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
PWC ![In: Personal Wireless Communications, The 12th IFIP International Conference on Personal Wireless Communications (PWC 2007), Prague, Czech Republic, September 2007, pp. 578-584, 2007, Springer, 978-0-387-74158-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
current operational amplifier, current mode, active filter |
31 | Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil |
Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 227-234, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
supply current test, I DD, I DDX monitor, analog test, structural test, mixed-signal test, current monitor |
31 | Rodrigo Picos, Miquel Roca 0001, Eugeni Isern 0001, Jaume Segura 0001, Eugenio García-Moreno |
Experimental Results on BIC Sensors for Transient Current Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 235-241, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
transient current testing, i(t), defect detection, built-in current sensor |
31 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos |
A Compact Built-In Current Sensor for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 95-99, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring |
31 | Maneesha Dalmia, André Ivanov, Sassan Tabatabaei |
Power supply current monitoring techniques for testing PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 366-371, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs |
31 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan |
New MVL-PLA Structures Based on Current-Mode CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 98-103, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic |
31 | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 118-123, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices |
31 | Eckhard Grass, Simon Jones |
Asynchronous circuits based on multiple localised current-sensing completion detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 170-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS |
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