Search results for "Current"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
96	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
69	Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
63	Radu Muresan, Catherine H. Gebotys	Instantaneous current modeling in a complex VLIW processor core.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model
60	Bartomeu Alorda, Vincent Canals, Jaume Segura 0001	A Two-Level Power-Grid Model for Transient Current Testing Evaluation.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	current based testing, off-chip current monitors, built-in current monitors, power grid modeling, transient current
60	Cheng-Ping Wang, Chin-Long Wey	Test Generation Of Analog Switched-Current Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults
55	Bartomeu Alorda, Jaume Segura 0001	An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing.	IOLTS	2003	DBLP DOI BibTeX RDF	Current based testing, off-chip current monitors, built-in current monitors, power grid modeling, transient current
55	Keith A. Bartels, Jay L. Fisher	Multifrequency eddy current image processing techniques for nondestructive evaluation.	ICIP	1995	DBLP DOI BibTeX RDF	eddy current testing, nondestructive evaluation, multifrequency eddy current image processing, materials evaluation, eddy current images, image formation physics, eddy current testing, complex valued images, SNR maximization, four-frequency processing, algorithm, image sequences, image sequence, signal-to-noise ratio, experimental data
52	Yolanda Lechuga, Román Mozuelos, Miguel Angel Allende, Mar Martínez, Salvador Bracho	Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	transient current test, fault detection, built-in current sensor, supply current monitoring
49	Jan Jerabek, Kamil Vrba	RF Pure Current-Mode Filters using Current Mirrors and Inverters. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	pure current mode, current mirror, current inverter, CMI, GCMI, frequency filter
47	Bartomeu Alorda, Sebastià A. Bota, Jaume Segura 0001	A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF	Current based testing, built-in current monitors, high-speed measurements, transient current
47	Shyang-Tai Su, Rafic Z. Makki	Testing of static random access memories by monitoring dynamic power supply current.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Current-testable design, dynamic current monitors, dynamic power supply current, pattern sensitivity, fault modeling
44	Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee	Built-in current sensor designs based on the bulk-driven technique.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement
43	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
43	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
40	Shangquan Liang, Minglun Gao, Yong-Sheng Yin, Honghui Deng	A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications.	DELTA	2008	DBLP DOI BibTeX RDF	segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell
39	Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija	A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.	PATMOS	2005	DBLP DOI BibTeX RDF
39	Norbert Herencsar, Kamil Vrba	Tunable Current-Mode Multifunction Filter Using Universal Current Conveyors.	ICONS	2008	DBLP DOI BibTeX RDF	tunable filter, multifunction filter, Universal Current Conveyor, simulation model UCC, current-mode circuit
39	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.	VTS	2007	DBLP DOI BibTeX RDF	Current Based Diagnosis, Current Signatures, I_DDQ, Very Low Voltage, CMOS, Bridging Defect
38	Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho	Iddt testing of continuous-time filters.	VTS	1995	DBLP DOI BibTeX RDF	continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits
38	Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija	Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
38	Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic	CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor.	ICECS	1998	DBLP DOI BibTeX RDF
38	K. Wayne Current	Current-mode CMOS multiple-valued logic circuits.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
38	K. Wayne Current	Multiple Valued Logic: Current-Mode CMOS Circuits.	ISMVL	1993	DBLP DOI BibTeX RDF
38	K. Wayne Current	A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit.	ISMVL	1992	DBLP DOI BibTeX RDF
38	K. Wayne Current, M. E. Hurlston	A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit.	ISMVL	1991	DBLP DOI BibTeX RDF
38	Yongjian Brandon Guo, K. Wayne Current	Voltage Comparator Circuits for Multiple-Valued CMOS Logic.	ISMVL	2002	DBLP DOI BibTeX RDF	voltage comparator, MVL, low-power, CMOS
38	Yehya H. Ghallab, Wael M. Badawy	A Novel pH Sensor Current Mode Read-Out Circuit Using Operational Floating Current Conveyor.	ICMENS	2004	DBLP DOI BibTeX RDF	Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits
37	Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley	Dynamic current modeling at the instruction level.	ISLPED	2006	DBLP DOI BibTeX RDF	current and power measurement in a processor, dynamic instruction-level current model
37	Suwon Lee, Sung-Hun Lim	Operational Characteristics of Intelligent Dual-Reactor with Current Controlled Inverter.	KES (1)	2005	DBLP DOI BibTeX RDF	dual-reactor, current controlled inverter, fault current, reactive power
37	Jian Liu, Rafic Z. Makki, Ayman I. Kayssi	Dynamic Power Supply Current Testing of CMOS SRAMs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	transient power supply current (i DDT), transient current sensor, disturb fault, CMOS SRAM
36	Ivo Lattenberg, Kamil Vrba	Low Input-Impedance Current-Mirror for High-Speed Data Communication.	ICN	2007	DBLP DOI BibTeX RDF	current mirror, signal processing, current mode
36	Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern 0001, Jaume Segura 0001, Miquel Roca 0001, Eugenio García	A BICS for CMOS OpAmps by Monitoring the Supply Current Peak.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	oscillation test, analog test, Built-In Current Sensor, current test
34	Jan Jerabek, Kamil Vrba	Novel Universal Filter Using Only Two Current Active Elements.	ICONS	2008	DBLP DOI BibTeX RDF	current follower, MCMI, pure current mode, universal filter, frequency filter
34	Chun-Lung Hsu	Control and Observation Structure for Analog Circuits with Current Test Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	current store cell (CSC), controllability, observability, analog circuit, current-mode
34	Jens Lienig, Goeran Jerke, Thorsten Adler	Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design
33	David Kubánek, Kamil Vrba	Second-Order State-Variable Filter with Current Operational Amplifiers.	ICONS	2008	DBLP DOI BibTeX RDF	Current operational amplifier, Current mode, Active filter
33	Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
33	Yehya H. Ghallab, Wael M. Badawy, Karan V. I. S. Kaler	A Novel PH Sensor Using Differential ISFET Current Mode Read-Out Circuit.	ICMENS	2003	DBLP DOI BibTeX RDF	Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits
33	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
33	Claude Thibeault	A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures.	VTS	1997	DBLP DOI BibTeX RDF	IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current
32	Goonmeet Bajaj, Sean Current, Daniel Schmidt, Bortik Bandyopadhyay, Christopher W. Myers, Srinivasan Parthasarathy 0001	Knowledge Gaps: A Challenge for Agent-Based Automatic Task Completion.	Top. Cogn. Sci.	2022	DBLP DOI BibTeX RDF
32	Sean Current, Yuntian He, Saket Gurukar, Srinivasan Parthasarathy 0001	FairMod: Fair Link Prediction and Recommendation via Graph Modification.	CoRR	2022	DBLP BibTeX RDF
32	Sean Current, Yuntian He, Saket Gurukar, Srinivasan Parthasarathy 0001	FairEGM: Fair Link Prediction and Recommendation via Emulated Graph Modification.	EAAMO	2022	DBLP DOI BibTeX RDF
32	Adrienne C. Kinney, Sean Current, Joceline Lega	Aedes-AI: Neural Network Models of Mosquito Abundance.	CoRR	2021	DBLP BibTeX RDF
32	Adrienne C. Kinney, Sean Current, Joceline Lega	Aedes-AI: Neural network models of mosquito abundance.	PLoS Comput. Biol.	2021	DBLP DOI BibTeX RDF
32	Luís Santos 0001, João Manuel Coutinho-Rodrigues, John R. Current	An improved heuristic for the capacitated arc routing problem.	Comput. Oper. Res.	2009	DBLP DOI BibTeX RDF
32	M.-G. Yoon, John R. Current	The hub location and network design problem with fixed and variable arc costs: formulation and dual-based solution heuristic.	J. Oper. Res. Soc.	2008	DBLP DOI BibTeX RDF
32	K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews	A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.	IEEE Trans. Biomed. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Akio Imai, Etsuko Nishimura, John R. Current	A Lagrangian relaxation-based heuristic for the vehicle routing with full container load.	Eur. J. Oper. Res.	2007	DBLP DOI BibTeX RDF
32	K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews	A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor.	ICMENS	2005	DBLP DOI BibTeX RDF
32	Yongjian Brandon Guo, K. Wayne Current	Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic.	J. Multiple Valued Log. Soft Comput.	2004	DBLP BibTeX RDF
32	James W. George, Charles S. Revelle, John R. Current	The Maximum Utilization Subtree Problem.	Ann. Oper. Res.	2002	DBLP DOI BibTeX RDF
32	Horst A. Eiselt, John R. Current	Special issue on location analysis.	Comput. Oper. Res.	2002	DBLP DOI BibTeX RDF
32	Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current	Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
32	Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija	Partitioned Branch Condition Resolution Logic.	SBCCI	2000	DBLP BibTeX RDF
32	Dan Olson, K. Wayne Current	Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts.	ISMVL	2000	DBLP DOI BibTeX RDF	MVL Hardware, Ternary Addition, MVL Structure, SUS-LOC
32	K. Wayne Current	Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.	ISMVL	2000	DBLP DOI BibTeX RDF	quaternary, memory, circuit, latch
32	João Manuel Coutinho-Rodrigues, João C. N. Clímaco, John R. Current	An interactive bi-objective shortest path approach: searching for unsupported nondominated solutions.	Comput. Oper. Res.	1999	DBLP DOI BibTeX RDF
32	Charles A. Weber, John R. Current, Anand Desai	Non-cooperative negotiation strategies for vendor selection.	Eur. J. Oper. Res.	1998	DBLP DOI BibTeX RDF
32	John R. Current, Samuel Ratick, Charles S. Revelle	Dynamic facility location when the total number of facilities is uncertain: A decision analysis approach.	Eur. J. Oper. Res.	1998	DBLP DOI BibTeX RDF
32	Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current	Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.	ISLPED	1997	DBLP DOI BibTeX RDF
32	K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic	Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.	ISMVL	1996	DBLP DOI BibTeX RDF
32	James F. Parker, K. Wayne Current, Stephen H. Lewis	A CMOS continuous-time NTSC-to-color-difference decoder.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
32	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals.	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
32	John R. Current, Hasan Pirkul, Erik Rolland	Efficient Algorithms for Solving the Shortest Covering Path Problem.	Transp. Sci.	1994	DBLP DOI BibTeX RDF
32	Wei-Shang Chu, K. Wayne Current	Quaternary Multiplier Circuit.	ISMVL	1994	DBLP DOI BibTeX RDF
32	K. Wayne Current, James F. Parker, Wes Hardaker	Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs.	ISCAS	1993	DBLP BibTeX RDF
32	Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi	High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture.	IEEE Trans. Circuits Syst. Video Technol.	1992	DBLP DOI BibTeX RDF
32	Hasan Pirkul, John R. Current, Vaidyanathan Nagarajan	The Hierarchical Network Design Problem: A New Formulation and Solution Procedures.	Transp. Sci.	1991	DBLP DOI BibTeX RDF
32	J. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu	A new VLSI architecture for real-time control of robot manipulators.	ICRA	1991	DBLP DOI BibTeX RDF
32	John R. Current, Charles S. Revelle, Jared L. Cohon	An interactive approach to identify the best compromise solution for two objective shortest path problems.	Comput. Oper. Res.	1990	DBLP DOI BibTeX RDF
32	K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi	An evaluation of Radon transform computations using DSP chips.	Mach. Vis. Appl.	1990	DBLP DOI BibTeX RDF
32	Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh	A VLSI architecture for two-dimensional Radon transform computations.	ICASSP	1990	DBLP DOI BibTeX RDF
32	K. Wayne Current	A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.	ISMVL	1990	DBLP DOI BibTeX RDF
32	John R. Current, David A. Schilling	The Covering Salesman Problem.	Transp. Sci.	1989	DBLP DOI BibTeX RDF
32	James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain 0002	An architecture for region boundary extraction in raster scan images suitable for VLSI implementation.	Mach. Vis. Appl.	1989	DBLP DOI BibTeX RDF
32	Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain 0002, K. Wayne Current, Paul J. Hurst	A Radon transform computer for multidimensional signal processing.	ICASSP	1989	DBLP DOI BibTeX RDF
32	John R. Current	The Design of a Hierarchical Transportation Network with Transshipment Facilities.	Transp. Sci.	1988	DBLP DOI BibTeX RDF
32	J. R. Parkhurst, K. Wayne Current, Anil K. Jain 0002, J. E. Grishaw	A unified DCT/IDCT architecture for VLSI implementation.	ICASSP	1988	DBLP DOI BibTeX RDF
32	James L. Mangin, K. Wayne Current	Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF
32	John R. Current	Discrete computational structures, second edition, By Robert R. Korfhage, Academic Press, Inc., Orlando, FI, 1984, 360 pp. Price $35.00.	Networks	1986	DBLP DOI BibTeX RDF
32	Stephen B. Haley, K. Wayne Current	Response change in linearized circuits and systems: Computational algorithms and applications.	Proc. IEEE	1985	DBLP DOI BibTeX RDF
32	Jared L. Cohon, Charles S. Revelle, John R. Current, Thomas Eagles, Russell C. Eberhart, Richard L. Church	Application of a multiobjective facility location model to power plant siting in a six-state region of the U.S.	Comput. Oper. Res.	1980	DBLP DOI BibTeX RDF
32	K. Wayne Current	High Density Integrated Computing Circuitry with Multiple Valued Logic.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF
32	K. Wayne Current	A High Data-Rate Digital Output Correlator Design.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Digital correlators, latched quaternary threshold logic full adders, multiple valued logic, threshold logic, parallel counters
32	K. Wayne Current	Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	quaternary threshold logic full adders, Multiple-valued logic, threshold logic, parallel counters
32	K. Wayne Current, Douglas A. Mow	Implementing Parallel Counters with Four-Valued Threshold Logic.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	Four-valved logic full adders, multivalued logic, threshold logic, parallel counters
32	K. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh	A high data rate, low power all-digital correlation circuit design.	ICASSP	1979	DBLP DOI BibTeX RDF
32	K. Wayne Current, Douglas A. Mow	Parallel counter design using four-valued threshold logic.	ICASSP	1978	DBLP DOI BibTeX RDF
32	K. Wayne Current, Douglas A. Mow	Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits.	MVL	1978	DBLP BibTeX RDF
32	K. Wayne Current, Douglas A. Mow	Four-valued threshold logic full adder circuit implementations.	MVL	1978	DBLP BibTeX RDF
31	Genival Mariano de Araujo, Heider Marconi G. Madureira, José Camargo da Costa	Design and characterization of a 0.35 micron CMOS voltage-to-current converter.	SBCCI	2009	DBLP DOI BibTeX RDF	voltage-to-current converter, system on chip, current reference
31	David Kubánek, Kamil Vrba	Second-Order Multifunction Filters with Current Operational Amplifiers. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	current operational amplifier, current mode, active filter
31	Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil	Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	supply current test, I DD, I DDX monitor, analog test, structural test, mixed-signal test, current monitor
31	Rodrigo Picos, Miquel Roca 0001, Eugeni Isern 0001, Jaume Segura 0001, Eugenio García-Moreno	Experimental Results on BIC Sensors for Transient Current Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	transient current testing, i(t), defect detection, built-in current sensor
31	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos	A Compact Built-In Current Sensor for IDDQ Testing.	IOLTW	2000	DBLP DOI BibTeX RDF	Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring
31	Maneesha Dalmia, André Ivanov, Sassan Tabatabaei	Power supply current monitoring techniques for testing PLLs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs
31	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
31	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
31	Eckhard Grass, Simon Jones	Asynchronous circuits based on multiple localised current-sensing completion detection.	ASYNC	1995	DBLP DOI BibTeX RDF	dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS