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1994-1998 (19) 1999-2001 (16) 2002-2003 (21) 2004-2005 (26) 2006 (19) 2007 (21) 2008 (22) 2009-2010 (25) 2011-2013 (20) 2014-2015 (23) 2016-2018 (19) 2019-2021 (16) 2022 (2)
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article(70) inproceedings(177) phdthesis(2)
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Found 249 publication records. Showing 249 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
123Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev Design and Analysis of Dual-Rail Circuits for Security Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
113Karthik Baddam, Mark Zwolinski Divided Backend Duplication Methodology for Balanced Dual Rail Routing. Search on Bibsonomy CHES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Dual Rail Routing, Dual Rail FPGA Implementation, Differential Power Analysis
96Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev Improving the Security of Dual-Rail Circuits. Search on Bibsonomy CHES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
86Zhimin Chen, Yujie Zhou Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
86Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
85Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
73Akira Mochizuki, Takahiro Hanyu Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. Search on Bibsonomy ISMVL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
73Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. Search on Bibsonomy ISMVL The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
72Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti Three-Phase Dual-Rail Pre-charge Logic. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF dual-rail logic, SABL, security, DPA
72Thomas Popp, Stefan Mangard Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis
70Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. Search on Bibsonomy ISMVL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61David W. Lloyd, Jim D. Garside A Practical Comparison of Asynchronous Design Styles. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
59Alin Razafindraibe, Michel Robert, Philippe Maurine Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
59Alin Razafindraibe, Michel Robert, Philippe Maurine Improvement of dual rail logic as a countermeasure against DPA. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
59Ethiopia Nigussie, Juha Plosila, Jouni Isoaho Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
59Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine A Method to Design Compact Dual-rail Asynchronous Primitives. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
59Geun Rae Cho, Tom Chen 0001 Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
59Byung-Soo Choi, Dong-Ik Lee Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
58G. Enrique Fernandez, R. Sridhar Dual rail static CMOS architecture for wave pipelining. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
56Gensoh Matsubara, Nobuhiro Ide A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF floating point, division, square root, self-timed
56Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin Power Balanced Gates Insensitive to Routing Capacitance Mismatch. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
56Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald Delay Insensitive Encoding and Power Analysis: A Balancing Act. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
55Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani A Practical DPA Countermeasure with BDD Architecture. Search on Bibsonomy CARDIS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure
47Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47Montek Singh, Steven M. Nowick The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang A new robust handshake for asymmetric asynchronous micro-pipelines. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu A Robust Handshake for Asynchronous System. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Montek Singh, Steven M. Nowick High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
45Fu-Wei Chen, Yi-Yu Liu Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Akira Mochizuki, Masatomo Miura, Takahiro Hanyu High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. Search on Bibsonomy ISMVL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Koji Ohashi, Mineo Kaneko Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF high-level synthesis, asynchronous circuit, datapath, register binding
45Patrick Schaumont, Kris Tiri Masking and Dual-Rail Logic Don't Add Up. Search on Bibsonomy CHES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Alin Razafindraibe, Michel Robert, Philippe Maurine Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin Security evaluation of dual rail logic against DPA attacks. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Daisuke Suzuki, Minoru Saeki Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Li Ding 0002, Pinaki Mazumder, N. Srinivas A dual-rail static edge-triggered latch. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
44Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. Search on Bibsonomy SSIRI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Power Constant Logic, WDDL, Positive Dual-Rail with Precharge Logic, FPGA, Side-Channel Attacks
44Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
42Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin Physical Design of FPGA Interconnect to Prevent Information Leakage. Search on Bibsonomy ARC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
42Charbel J. Akl, Magdy A. Bayoumi Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF circuit family, low-power, high-speed
42Daniele Rossi 0001, S. Cavallotti, Cecilia Metra Error Correcting Codes for Crosstalk Effect Minimization. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Rajat Subhra Chakraborty, Swarup Bhunia A study of asynchronous design methodology for robust CMOS-nano hybrid system design. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
41Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure
41Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor Security Evaluation of Asynchronous Circuits. Search on Bibsonomy CHES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis
41J. Yeandel, D. Thulborn, Simon Jones An on-line testable UART implemented using IFIS. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF data communication equipment, online testable UART, IFIS methodology, complex integrated circuit, FPGA technology, dual-rail coding, failure detection, handshaking protocol
41Eckhard Grass, Simon Jones Asynchronous circuits based on multiple localised current-sensing completion detection. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
41H. Dhanesha, K. Falakshahi, Mark Horowitz Array-of-arrays architecture for parallel floating point multiplication. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
40Geun Rae Cho, Tom Chen 0001 On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng A semi-custom memory design for an asynchronous 8051 microcontroller. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Jae-Hee Won, Kiyoung Choi Low power self-timed Radix-2 division (poster session). Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RSD, radix-2 division, low power, self-timed
38Mark E. Dean, David L. Dill, Mark Horowitz Self-timed logic using Current-Sensing Completion Detection (CSCD). Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
33Eric Menendez, Ken Mai A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style. Search on Bibsonomy HOST The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya A zero-time-overhead asynchronous four-phase controller. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Jason Waddle, David A. Wagner 0001 Fault Attacks on Dual-Rail Encoded Systems. Search on Bibsonomy ACSAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
28Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu A dual-rail/single-rail hybrid system using null convention logic circuits. Search on Bibsonomy Microelectron. J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
28Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
28Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra Power Consumption of Fault Tolerant Busses. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky Asynchronous balanced gates tolerant to interconnect variability. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Orna Grumberg, Assaf Schuster, Avi Yadgar 3-Valued Circuit SAT for STE with Automatic Refinement. Search on Bibsonomy ATVA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani Power Analysis Attacks on MDPL and DRSL Implementations. Search on Bibsonomy ICISC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop
28Ethiopia Nigussie, Juha Plosila, Jouni Isoaho Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Myeong-Hoon Oh, Dong-Soo Har A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Frederic Worm, Paolo Ienne, Patrick Thiran Soft self-synchronising codes for self-calibrating communication. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28T. Felicijan, Stephen B. Furber An asynchronous ternary logic signaling system. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
28Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane Fault Injection Resilience. Search on Bibsonomy FDTC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Fault Injection Attack (FIA), symmetric block encryption, Fault Injection Resilience (FIR), Differential Fault Analysis (DFA), Dual-rail with Precharge Logic (DPL), Side-Channel Attack (SCA), Denial of Service (DoS)
27Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu DPL on Stratix II FPGA: What to Expect?. Search on Bibsonomy ReConFig The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Dual-rail with Precharge Logic (DPL), Wave Dynamic Differential Logic (WDDL), Field Programmable Gates Array (FPGA), Differential Power Analysis (DPA), Commercial Off-The-Shelf (COTS), Side-Channel Analysis (SCA)
27Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Parallel vs. serial on-chip communication. Search on Bibsonomy SLIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
27Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Asynchronous Circuit Design, Single Track, Dual-Rail, Fast Forwarding
27Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards. Search on Bibsonomy IEEE Trans. Dependable Secur. Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF differential logic, dual rail logic, chip-cards, cryptography, differential power analysis, DPA, power analysis
27Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard Evaluation of the Masked Logic Style MDPL on a Prototype Chip. Search on Bibsonomy CHES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF DPA-Resistant Logic Styles, Masked Logic, Dual-Rail Precharge Logic, Early Propagation Effect, Improved MDPL, Prototype Chip
27Benedikt Gierlichs DPA-Resistance Without Routing Constraints? Search on Bibsonomy CHES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP
27Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan A New Control Circuit for Asynchronous Micropipelines. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF zero-overhead, dual-rail coding, Asynchronous design, micropipeline
27Daniel H. Linder, James C. Harden Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs
24Amitava Mitra, William F. McLaughlin, Steven M. Nowick Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev Delay/Phase Regeneration Circuits. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Gin Yee, Carl Sechen Clock-delayed domino for dynamic circuit design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Luis A. Plana, Steven M. Nowick Architectural optimization for low-power nonpipelined asynchronous systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
22Jean Pierre T. Habimana, Francis Sabado, Jia Di Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation. Search on Bibsonomy ISCAS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. Search on Bibsonomy Microelectron. J. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
22Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Search on Bibsonomy Int. J. Reconfigurable Comput. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
17Farzad Niknia, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
17Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
17David Drahi, Demid V. Sychev, Khurram K. Pirov, Ekaterina A. Sazhina, Valeriy A. Novikov, Ian A. Walmsley, A. I. Lvovsky 0001 Entangled resource for interfacing single- and dual-rail optical qubits. Search on Bibsonomy Quantum The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
17Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi 0001, Taejoong Song, Jongwook Kye 5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. Search on Bibsonomy VLSI Circuits The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
17Yongjie Lu, Weifeng He A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor. Search on Bibsonomy ASICON The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
17Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
17Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. Search on Bibsonomy IEEE Access The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
17Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez 0002, Antonio J. Acosta 0001 Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
17Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. Search on Bibsonomy MWSCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
17Xiaosen Liu, Harish K. Krishnamurthy, Claudia P. Barrera, Jing Han, Rajasekhara M. Narayana Bhatla, Scott Chiu, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. Search on Bibsonomy VLSI Circuits The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
17Kurt M. English A highly parallel automated SFQ circuit design and margin optimization tool applied to a dual rail logic single flux quanta cell library. Search on Bibsonomy 2020   RDF
17M. Suresh, A. K. Panda, J. Sudhakar Low power aware standard cells using dual rail multi threshold null convention logic methodology. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
17Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
17Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang 0096, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. Search on Bibsonomy AsianHOST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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