Search results for "LI-BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
107	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Allocation Techniques for Reducing BIST Area Overhead of Data Paths.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF
105	Nilanjan Mukherjee, Ramesh Karri	Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
93	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
84	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik	On improving test quality of scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
82	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
81	Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell	TI-BIST: a temperature independent analog BIST for switched-capacitor filters.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST
78	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for faults in system backplanes.	ICCAD	1997	DBLP DOI BibTeX RDF	BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration
78	Nur A. Touba	Obtaining High Fault Coverage with Circular BIST Via State Skipping.	VTS	1997	DBLP DOI BibTeX RDF	Circular BIST, Circular Self-Test Path, Conflict Matrix, Column Covering, Built-In Self-Test (BIST), Linear Feedback Shift Register, Pseudo-Random Testing, Digital Testing
78	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.	DFT	2004	DBLP DOI BibTeX RDF
76	Seongmoon Wang	A BIST TPG for Low Power Dissipation and High Fault Coverage.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
76	Saman Adham, Sanjay Gupta	DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
75	Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi	Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.	VTS	1997	DBLP DOI BibTeX RDF	digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
75	Khaled Saab 0001, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski	Frequency-based BIST for analog circuit testin.	VTS	1995	DBLP DOI BibTeX RDF	waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits
75	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
70	Scott Davidson 0001	BIST the hard way.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	N-detection, scan BIST, built-in self-test, logic, IC, mixed-signal BIST
70	Kamran Zarrineh, Shambhu J. Upadhyaya	On Programmable Memory Built-In Self Test Architectures.	DATE	1999	DBLP DOI BibTeX RDF
68	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail	An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
68	Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song	A Cost Effective BIST Second-Order Sigma-Delta-Modulator.	DDECS	2008	DBLP DOI BibTeX RDF
68	Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir	A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.	DATE	2008	DBLP DOI BibTeX RDF
68	Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara	BIST Pretest of ICs: Risks and Benefits.	VTS	2006	DBLP DOI BibTeX RDF
68	Vishal Suthar, Shantanu Dutt	Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.	VTS	2006	DBLP DOI BibTeX RDF
68	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudo-Functional Scan-based BIST for Delay Fault.	VTS	2005	DBLP DOI BibTeX RDF
68	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
68	Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai	BRAINS: A BIST Compiler for Embedded Memories.	DFT	2000	DBLP DOI BibTeX RDF
68	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Low Power/Energy BIST Scheme for Datapaths.	VTS	2000	DBLP DOI BibTeX RDF
68	Yervant Zorian, Hakim Bederr	An Effective Multi-Chip BIST Scheme.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, DFT, MCM testing
67	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Luz Balado, Joan Figueras	On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	low-power, BIST, RTL, test quality, defects-based test
65	Ioannis Voyiatzis, Constantin Halatsis	A Low-Cost Concurrent BIST Scheme for Increased Dependability.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	input vector monitoring concurrent BIST, Built-in self test, concurrent testing
64	André Ivanov, Barry K. Tsuji, Yervant Zorian	Programmable BIST Space Compactors.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	BIST methodologies, BIST space compaction, parity tree, BIST compaction, genetic algorithms, Testing, Built-In Self-Test (BIST), design for testability
62	Shivakumar Swaminathan, Krishnendu Chakrabarty	On Using Twisted-Ring Counters for Test Set Embedding in BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
62	Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich	Application of Deterministic Logic BIST on Industrial Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	industrial applications, scan-based BIST, logic BIST
62	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
62	Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee	Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
62	Hassan Ihs, Christian Dufaza	Test synthesis for DC test of switched-capacitors circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
60	Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter	BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study.	ITC	2003	DBLP DOI BibTeX RDF
60	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	VTS	2002	DBLP DOI BibTeX RDF
60	Ching-Hong Tsai, Cheng-Wen Wu	Processor-programmable memory BIST for bus-connected embedded memories.	ASP-DAC	2001	DBLP DOI BibTeX RDF
60	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
60	Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams	BIST hardware synthesis for RTL data paths based on testcompatibility classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
60	Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian	A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	built-in self-test, embedded cores, EDA tools
60	Juin-Ming Lu, Cheng-Wen Wu	Cost and Benefit Models for Logic and Memory BIST.	DATE	2000	DBLP DOI BibTeX RDF
60	Xiaowei Li 0001, Paul Y. S. Cheung	High-Level BIST Synthesis for Delay Testing.	DFT	1998	DBLP DOI BibTeX RDF
60	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
60	Karim Arabi, Bozena Kaminska, Janusz Rzeszut	BIST for D/A and A/D Converters.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
60	Charles E. Stroud	An Automated BIST Approach for General Sequential Logic Synthesis.	DAC	1988	DBLP BibTeX RDF
59	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	BIST insertion, wiring area, simulated annealing, test synthesis
59	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
59	Miron Abramovici, Charles E. Stroud, John Marty Emmert	Online BIST and BIST-based diagnosis of FPGA logic blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
57	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	BIST, datapath, high level test synthesis
57	Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki	Cost/Quality Trade-off in Synthesis for BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	DFT reuse, BIST, synthesis for testability, testability analysis
57	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
57	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
57	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
57	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
54	Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich	Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	store and generate schemes, BIST, test data compression, deterministic BIST
54	Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich	A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	store and generate schemes, BIST, deterministic BIST
54	Xiaodong Zhang 0010, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST.	IOLTW	2000	DBLP DOI BibTeX RDF	Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
54	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices.	VTS	2004	DBLP DOI BibTeX RDF
54	Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung	At-Speed Interconnect Test and Diagnosis of External Memories on a System.	ITC	2004	DBLP DOI BibTeX RDF
54	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi	A new approach to built-in self-testable datapath synthesis based on integer linear programming.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
53	Ioannis Voyiatzis	An Accumulator-Based Compaction Scheme For Online BIST of RAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
53	Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar	Hybrid BIST Optimization Using Reseeding and Test Set Compaction.	DSD	2007	DBLP DOI BibTeX RDF
53	Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar	Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems.	SIES	2007	DBLP DOI BibTeX RDF
53	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
53	Andrew B. Kahng, Sherief Reda	New and improved BIST diagnosis methods from combinatorial Group testing theory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
53	Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato	Effective Post-BIST Fault Diagnosis for Multiple Faults.	DFT	2006	DBLP DOI BibTeX RDF
53	Biplab K. Sikdar, Samir Roy, Debesh K. Das	A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, reachability, degree-of-freedom
53	Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt	On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).	IOLTS	2005	DBLP DOI BibTeX RDF
53	Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu	BIST Based Fault Diagnosis Using Ambiguous Test Set.	DFT	2003	DBLP DOI BibTeX RDF
53	Nur A. Touba	Circular BIST with state skipping.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
53	Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert	On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.	IOLTW	2001	DBLP DOI BibTeX RDF
53	Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.	ISQED	2001	DBLP DOI BibTeX RDF
53	Kamran Zarrineh, Shambhu J. Upadhyaya	Programmable Memory BIST and a New Synthesis Framework.	FTCS	1999	DBLP DOI BibTeX RDF
53	Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau	Lessons Learned from Practical Applications of BIST/B-S Technology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
53	Andrzej Krasniewski	Design of Dependable Hardware: What BIST is most Efficient?	EDCC	1996	DBLP DOI BibTeX RDF
53	Chien-In Henry Chen, Joel T. Yuen	Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
51	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory
51	Ramesh Karri, Nilanjan Mukherjee	Versatile BIST: an integrated approach to on-line/off-line BIST.	ITC	1998	DBLP DOI BibTeX RDF
50	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
50	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
50	Lei Li 0036, Zhanglei Wang, Krishnendu Chakrabarty	Scan-BIST based on cluster analysis and the encoding of repeating sequences.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	clustering test data volume, Built-in self-test (BIST), test compression
50	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
50	Dong Xiang, Ming-Jing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Test signal, random testability, weighted random testing, scan-based BIST
50	Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski	Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.	SBCCI	2004	DBLP DOI BibTeX RDF	system-on-chip, BIST, power aware, mixed-signal test
50	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
50	Samir Roy, Biplab K. Sikdar	Power Conscious BIST Design for Sequential Circuits Using ghost-FSM.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Ghost-FSM, power conscious BIST, built-in self-test, multi-objective genetic algorithm, state assignment
50	Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das	Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	FSM synthesis, emitability, BIST, reachability, degree of freedom
50	Eduardo J. Peralías, Adoración Rueda, José Luis Huertas	New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters
50	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
50	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
50	Seongwon Kim, Mani Soma, Dilip Risbud	An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops.	VTS	2000	DBLP DOI BibTeX RDF	Defect-oriented testing, Built-In Self-Test (BIST), Design for Testability, PLL, Self-Checking Circuits
50	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
50	Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker 0001	On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.	VTS	1997	DBLP DOI BibTeX RDF	input probability, weighted random pattern generation (WRPG), genetic algorithm, Build in self test (BIST)
50	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
50	Hans-Joachim Wunderlich, Gundolf Kiefer	Bit-flipping BIST.	ICCAD	1996	DBLP DOI BibTeX RDF	mixed-model BIST
50	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
50	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
50	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
50	O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis	Zero aliasing ROM BIST.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	error cancellation, error masking, ROM BIST, Aliasing, signature analysis