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Found 1860 publication records. Showing 1843 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
115Seongmoon Wang Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
107Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer Allocation Techniques for Reducing BIST Area Overhead of Data Paths. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
105Nilanjan Mukherjee, Ramesh Karri Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
93Krishna Sekar, Sujit Dey LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF LI-BIST, crosstalk test, BIST, SoC test, low-power test
84Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik On improving test quality of scan-based BIST. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
82Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
81Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST
78Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for faults in system backplanes. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration
78Nur A. Touba Obtaining High Fault Coverage with Circular BIST Via State Skipping. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Circular BIST, Circular Self-Test Path, Conflict Matrix, Column Covering, Built-In Self-Test (BIST), Linear Feedback Shift Register, Pseudo-Random Testing, Digital Testing
78Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
76Seongmoon Wang A BIST TPG for Low Power Dissipation and High Fault Coverage. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
76Saman Adham, Sanjay Gupta DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
75Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
75Khaled Saab 0001, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski Frequency-based BIST for analog circuit testin. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits
75Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis An efficient comparative concurrent Built-In Self-Test technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
70Scott Davidson 0001 BIST the hard way. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF N-detection, scan BIST, built-in self-test, logic, IC, mixed-signal BIST
70Kamran Zarrineh, Shambhu J. Upadhyaya On Programmable Memory Built-In Self Test Architectures. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
68Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
68Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song A Cost Effective BIST Second-Order Sigma-Delta-Modulator. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
68Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
68Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara BIST Pretest of ICs: Risks and Benefits. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
68Vishal Suthar, Shantanu Dutt Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
68Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng Pseudo-Functional Scan-based BIST for Delay Fault. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
68Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
68Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai BRAINS: A BIST Compiler for Embedded Memories. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
68Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian Low Power/Energy BIST Scheme for Datapaths. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
68Yervant Zorian, Hakim Bederr An Effective Multi-Chip BIST Scheme. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF built-in self-test, DFT, MCM testing
67Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Luz Balado, Joan Figueras On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF low-power, BIST, RTL, test quality, defects-based test
65Ioannis Voyiatzis, Constantin Halatsis A Low-Cost Concurrent BIST Scheme for Increased Dependability. Search on Bibsonomy IEEE Trans. Dependable Secur. Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF input vector monitoring concurrent BIST, Built-in self test, concurrent testing
64André Ivanov, Barry K. Tsuji, Yervant Zorian Programmable BIST Space Compactors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF BIST methodologies, BIST space compaction, parity tree, BIST compaction, genetic algorithms, Testing, Built-In Self-Test (BIST), design for testability
62Shivakumar Swaminathan, Krishnendu Chakrabarty On Using Twisted-Ring Counters for Test Set Embedding in BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
62Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich Application of Deterministic Logic BIST on Industrial Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF industrial applications, scan-based BIST, logic BIST
62Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch An adjacency-based test pattern generator for low power BIST design. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
62Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
62Hassan Ihs, Christian Dufaza Test synthesis for DC test of switched-capacitors circuits. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
60Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Krishna Sekar, Sujit Dey LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Ching-Hong Tsai, Cheng-Wen Wu Processor-programmable memory BIST for bus-connected embedded memories. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
60Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
60Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams BIST hardware synthesis for RTL data paths based on testcompatibility classes. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
60Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF built-in self-test, embedded cores, EDA tools
60Juin-Ming Lu, Cheng-Wen Wu Cost and Benefit Models for Logic and Memory BIST. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
60Xiaowei Li 0001, Paul Y. S. Cheung High-Level BIST Synthesis for Delay Testing. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
60Alex Orailoglu Microarchitectural synthesis for rapid BIST testing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
60Karim Arabi, Bozena Kaminska, Janusz Rzeszut BIST for D/A and A/D Converters. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
60Charles E. Stroud An Automated BIST Approach for General Sequential Logic Synthesis. Search on Bibsonomy DAC The full citation details ... 1988 DBLP  BibTeX  RDF
59Abdil Rashid Mohamed, Zebo Peng, Petru Eles A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF BIST insertion, wiring area, simulated annealing, test synthesis
59Mehdi Ehsanian, Bozena Kaminska, Karim Arabi A new digital test approach for analog-to-digital converter testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
59Miron Abramovici, Charles E. Stroud, John Marty Emmert Online BIST and BIST-based diagnosis of FPGA logic blocks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF BIST, datapath, high level test synthesis
57Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki Cost/Quality Trade-off in Synthesis for BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF DFT reuse, BIST, synthesis for testability, testability analysis
57Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
57Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for SRAM cluster interconnect testing at board level. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
57Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos Low Power BIST for Wallace Tree-Based Fast Multipliers. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Testing, Low Power, BIST, Multipliers, Wallace Trees
57Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An effective BIST scheme for carry-save and carry-propagate array multipliers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
54Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF store and generate schemes, BIST, test data compression, deterministic BIST
54Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF store and generate schemes, BIST, deterministic BIST
54Xiaodong Zhang 0010, Kaushik Roy 0001 Power Reduction in Test-Per-Scan BIST. Search on Bibsonomy IOLTW The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
54Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung At-Speed Interconnect Test and Diagnosis of External Memories on a System. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi A new approach to built-in self-testable datapath synthesis based on integer linear programming. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
53Ioannis Voyiatzis An Accumulator-Based Compaction Scheme For Online BIST of RAMs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
53Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar Hybrid BIST Optimization Using Reseeding and Test Set Compaction. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. Search on Bibsonomy SIES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Andrew B. Kahng, Sherief Reda New and improved BIST diagnosis methods from combinatorial Group testing theory. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
53Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato Effective Post-BIST Fault Diagnosis for Multiple Faults. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
53Biplab K. Sikdar, Samir Roy, Debesh K. Das A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF emitability, FSM state encoding, reachability, degree-of-freedom
53Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
53Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu BIST Based Fault Diagnosis Using Ambiguous Test Set. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
53Nur A. Touba Circular BIST with state skipping. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
53Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. Search on Bibsonomy IOLTW The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
53Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
53Kamran Zarrineh, Shambhu J. Upadhyaya Programmable Memory BIST and a New Synthesis Framework. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
53Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau Lessons Learned from Practical Applications of BIST/B-S Technology. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
53Andrzej Krasniewski Design of Dependable Hardware: What BIST is most Efficient? Search on Bibsonomy EDCC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
53Chien-In Henry Chen, Joel T. Yuen Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
51Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory
51Ramesh Karri, Nilanjan Mukherjee Versatile BIST: an integrated approach to on-line/off-line BIST. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
50Dong Xiang, Mingjing Chen, Jia-Guang Sun Scan BIST with biased scan test signals. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF random testability, test signal, biased random testing, scan-based BIST
50Dong Xiang, Mingjing Chen, Hideo Fujiwara Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Random testability, scan enable signal, weighted random testing, scan-based BIST
50Lei Li 0036, Zhanglei Wang, Krishnendu Chakrabarty Scan-BIST based on cluster analysis and the encoding of repeating sequences. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF clustering test data volume, Built-in self-test (BIST), test compression
50Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF BIST, delay faults, look-up table
50Dong Xiang, Ming-Jing Chen, Hideo Fujiwara Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Test signal, random testability, weighted random testing, scan-based BIST
50Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-chip, BIST, power aware, mixed-signal test
50Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan Multimode scan: Test per clock BIST for IP cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF SoC, BIST, scan, digital testing
50Samir Roy, Biplab K. Sikdar Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Ghost-FSM, power conscious BIST, built-in self-test, multi-objective genetic algorithm, state assignment
50Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FSM synthesis, emitability, BIST, reachability, degree of freedom
50Eduardo J. Peralías, Adoración Rueda, José Luis Huertas New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters
50Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for Combinational Cluster Interconnect Testing at Board Level. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
50Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara Single-control testability of RTL data paths for BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
50Seongwon Kim, Mani Soma, Dilip Risbud An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Defect-oriented testing, Built-In Self-Test (BIST), Design for Testability, PLL, Self-Checking Circuits
50Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF BIST Design, Test, Low-power Design, Energy Consumption
50Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker 0001 On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF input probability, weighted random pattern generation (WRPG), genetic algorithm, Build in self test (BIST)
50Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
50Hans-Joachim Wunderlich, Gundolf Kiefer Bit-flipping BIST. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mixed-model BIST
50Roberto Bevacqua, Luca Guerrazzi, Franco Fummi SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
50Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
50Imtiaz P. Shaik, Michael L. Bushnell Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
50O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis Zero aliasing ROM BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF error cancellation, error masking, ROM BIST, Aliasing, signature analysis
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