Search results for "SOI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Liqiong Wei, Rongtian Zhang, Kaushik Roy 0001, Zhanping Chen, David B. Janes	Vertically integrated SOI circuits for low-power and high-performance applications.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
105	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
83	D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel	SOI Transistor Model for Fast Transient Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF
83	Pin Su, Samel K. H. Fung, Weidong Liu 0002, Chenming Hu	Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD.	ISQED	2002	DBLP DOI BibTeX RDF
81	Takafumi Matsumaru, Yuichi Ito, Wataru Saitou	The step-on interface (SOI) on a mobile platform: basic functions.	HRI	2010	DBLP DOI BibTeX RDF	friendly-amusing mobile (fam) function, range scanner, step-on interface (soi), human-robot interaction, projector
72	Emrah Acar, Peter Feldmann	Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA).	ISCAS	2006	DBLP DOI BibTeX RDF
72	Rouwaida Kanj, Elyse Rosenbaum	Critical evaluation of SOI design guidelines.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
69	Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.	ISQED	2008	DBLP DOI BibTeX RDF	PD/SOI, dopant fluctuation, sense amplifier, Variation
69	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	FD/SOI, low-power, stability, SRAM
60	Michael Fulde, Doris Schmitt-Landsiedel, Gerhard Knoblinger	Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
60	Miriam Adlerstein Marwick, Andreas G. Andreou	Retinomorphic system design in three dimensional SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
60	Olivier Thomas, Amara Amara	Ultra low voltage design considerations of SOI SRAM memory cells.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
60	Mohammad R. Hoque, T. Ahmad, Todd R. McNutt, H. Alan Mantooth, Mohammad M. Mojarradi	Design technique of an on-chip, high-voltage charge pump in SOI.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
60	Anurag Chaudhry, M. Jagadesh Kumar	Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies.	VLSI Design	2004	DBLP DOI BibTeX RDF
60	Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
60	Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn	Design of an Embedded Fully-Depleted SOI SRAM.	MTDT	2001	DBLP DOI BibTeX RDF
58	Ruchir Puri, Ching-Te Chuang	SOI Digital Circuits: Design Issues.	VLSI Design	2000	DBLP DOI BibTeX RDF	Design, Digital Circuits, SOI
58	Yongduek Seo, Hyunjung Lee, Sang Wook Lee	Outlier Removal by Convex Optimization for L-Infinity Approaches.	PSIVT	2009	DBLP DOI BibTeX RDF
58	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
57	Riichiro Takemura, Kiyoo Itoh 0001, Tomonori Sekiguchi	A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers.	ISLPED	2006	DBLP DOI BibTeX RDF	FD-SOI, dynamic-VT sense amplifier, low-voltage RAM, twin-cell DRAM
57	Eric W. MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
55	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
55	R. Dean Adams, Phil Shephard III	Silicon-on-Insulator Technology Impacts on SRAM Testing.	VTS	2000	DBLP DOI BibTeX RDF	Fault modeling and simulation, Silicon On Insulator (SOI), Memory testing
54	John P. Denton, Sang Woo Pae, Gerold W. Neudeck	Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	SOI MOSFET, selective epitaxial growth, silicon, silicon on insulator, thin film SOI, three dimensional circuits
48	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
48	Asha Balijepalli, Joseph Ervin, Yu Cao 0001, Trevor Thornton	Compact Modeling of a PD SOI MESFET for Wide Temperature Designs.	ISQED	2007	DBLP DOI BibTeX RDF
48	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
48	Mini Nanua, David T. Blaauw, Chanhee Oh	Leakage Current Modeling in PD SOI Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
48	Nele V. T. D'Halleweyn, James Benson, William Redman-White, Ketan Mistry, M. Swanenberg	MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
48	Rajiv V. Joshi, K. Kroell, Ching-Te Chuang	A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.	VLSI Design	2004	DBLP DOI BibTeX RDF
48	Erik Säll, Mark Vesterbacka	Design of a Comparator in CMOS SOI.	IWSOC	2004	DBLP DOI BibTeX RDF
48	Ertan Zencir, Numan Sadi Dogan, Ercument Arvas, Mohammed Ketel	A low-power low-noise amplifier in 0.35µm SOI CMOS technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
48	Geun Rae Cho, Tom Chen 0001	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic.	ISQED	2003	DBLP DOI BibTeX RDF
48	Koushik K. Das, Richard B. Brown	Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology.	VLSI Design	2003	DBLP DOI BibTeX RDF
48	Eric W. MacDonald, Nur A. Touba	Very Low Voltage Testing of SOI Integrated Circuits.	VTS	2002	DBLP DOI BibTeX RDF
48	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
48	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.	VLSI Design	2000	DBLP DOI BibTeX RDF
48	Sani R. Nassif, Tuyen V. Nguyen	SOI technology and tools (abstract).	ICCAD	1999	DBLP BibTeX RDF
48	Gwo-Chung Tai, Can E. Korman, Isaak D. Mayergoyz	A parallel-in-time method for the transient simulation of SOI devices with drain current overshoots.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
46	Takafumi Matsumaru, Yuichi Ito, Wataru Saitou	The step-on interface (SOI) on a mobile platform: rehabilitation of the physically challenged.	HRI	2010	DBLP DOI BibTeX RDF	friendly-amusing mobile (fam) function, physically challenged, step-on interface (soi), human-robot interaction, rehabilitation
46	Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner	A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	RF circuit, SOI CMOS, frequency divider, low power, CML
46	Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner	A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.	ISLPED	2003	DBLP DOI BibTeX RDF	SOI CMOS, high resistivity substrate, phase NoiseFOM, low power, VCO, RF design
46	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
41	Amara Amara, Bastien Giraud, Olivier Thomas	An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.	DELTA	2010	DBLP DOI BibTeX RDF	SRAM cell, Planar Double-Gate (DG), Fully Depleted SOI (FD-SOI), read and write tradeoffs, Ultra Low Voltage (ULV)
37	Gautam Kumar Singh, Santosh Kumar Panigrahi	A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating.	ISQED	2007	DBLP DOI BibTeX RDF
37	Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.	ISQED	2007	DBLP DOI BibTeX RDF
37	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
37	Eric W. MacDonald, Nur A. Touba	Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
37	Fatemeh Aezinia, Behjat Forouzandeh	A Novel Low Power NOR gate in SOI CMOS Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
37	Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez	Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.	VLSI Design	2005	DBLP DOI BibTeX RDF
37	Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara	Modeling subthreshold SOI logic for static timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
37	Ertan Zencir, Ahmet Tekin, Numan Sadi Dogan, Ercument Arvas	A low-power DC-7-GHz SOI CMOS distributed amplifier.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
37	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
37	Koushik K. Das, Richard B. Brown	Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS.	ISVLSI	2003	DBLP DOI BibTeX RDF
37	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Stephane Adriaensen, Denis Flandre	Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.	SBCCI	2003	DBLP DOI BibTeX RDF
37	Najeeb-ud-Din Hakim, V. Ramgopal Rao, J. Vasi	Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications.	VLSI Design	2003	DBLP DOI BibTeX RDF
37	Geun Rae Cho, Tom Chen 0001	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.	VLSI Design	2003	DBLP DOI BibTeX RDF
37	Koichi Nose, Takayasu Sakurai	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.	ISLPED	2002	DBLP DOI BibTeX RDF
37	Rouwaida Kanj, Elyse Rosenbaum	A critical look at design guidelines for SOI logic gates.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
37	Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine	Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.	ISQED	2002	DBLP DOI BibTeX RDF
37	Kenneth L. Shepard, Dae-Jin Kim	Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
37	Kenneth L. Shepard	CAD Issues for CMOS VLSI Design in SOI.	ISQED	2001	DBLP DOI BibTeX RDF
37	Kenneth L. Shepard, Dae-Jin Kim	Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis.	ICCAD	1999	DBLP DOI BibTeX RDF
37	J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak	SOI Implementation of a 64-Bit Adder.	ICCD	1999	DBLP DOI BibTeX RDF
35	Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar	A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications.	VLSI Design	2010	DBLP DOI BibTeX RDF	LDMOS, breakdown voltage, on-resistance, transconductance, SOI
35	Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown	New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	VLSI, high-performance, leakage-power, circuits, SOI
35	Fernando Silveira, Denis Flandre	A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
35	Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin	A high speed and low power SOL inverter using active body-bias.	ISLPED	1998	DBLP DOI BibTeX RDF
34	Joseph Nayfach-Battilana, Jose Renau	SOI, interconnect, package, and mainboard thermal characterization.	ISLPED	2009	DBLP DOI BibTeX RDF	SOI modeling, package modeling, thermal modeling, interconnect modeling
33	Diego Soi, Alessandro Sanna, Davide Maiorca, Giorgio Giacinto	Enhancing android malware detection explainability through function call graph APIs.	J. Inf. Secur. Appl.	2024	DBLP DOI BibTeX RDF
33	Soi Ahn, Hyeon-Su Kim, Jae-Young Byon, Hancheol Lim	Improving Dust Aerosol Optical Depth (DAOD) Retrieval from the GEOKOMPSAT-2A (GK-2A) Satellite for Daytime and Nighttime Monitoring.	Sensors	2024	DBLP DOI BibTeX RDF
33	Soi Jeon, Hoang Tien Nguyen, Dae-Hyun Choi	Safety-Integrated Online Deep Reinforcement Learning for Mobile Energy Storage System Scheduling and Volt/VAR Control in Power Distribution Networks.	IEEE Access	2023	DBLP DOI BibTeX RDF
33	Diego Soi, Davide Maiorca, Giorgio Giacinto, Harel Berger	Can you See me? On the Visibility of NOPs against Android Malware Detectors.	CoRR	2023	DBLP DOI BibTeX RDF
33	Shashank Soi, Sushil Kumar Singh 0002, Rajendra Singh, Ashok Kumar	C-Band Iris Coupled Cavity Bandpass Filter.	SPCOM	2022	DBLP DOI BibTeX RDF
33	Soi Ahn, Sung-Rae Chung, Hyun-Jong Oh, Chu-Yong Chung	Composite Aerosol Optical Depth Mapping over Northeast Asia from GEO-LEO Satellite Observations.	Remote. Sens.	2021	DBLP DOI BibTeX RDF
33	Mehtab Singh, Sahil Nazir Pottoo, Suvidhi, Vivek Soi, Amit Grover, Moustafa H. Aly	A high-speed radio over free space optics transmission link under dust environment conditions employing hybrid wavelength- and mode-division multiplexing.	Wirel. Networks	2021	DBLP DOI BibTeX RDF
33	Soi Jeon, Dae-Hyun Choi	Optimal Energy Management Framework for Truck-Mounted Mobile Charging Stations Considering Power Distribution System Operating Conditions.	Sensors	2021	DBLP DOI BibTeX RDF
33	Soi Ahn, Joon-Bum Jee, Kyu-Tae Lee, Hyun-Jong Oh	Enhanced Accuracy of Airborne Volcanic Ash Detection Using the GEOKOMPSAT-2A Satellite.	Sensors	2021	DBLP DOI BibTeX RDF
33	Rupanshu Soi, Michael Bauer 0001, Sean Treichler, Manolis Papadakis, Wonchan Lee, Patrick S. McCormick, Alex Aiken, Elliott Slaughter	Index launches: scalable, flexible representation of parallel task groups.	SC	2021	DBLP DOI BibTeX RDF
33	Rupanshu Soi, Nischay Ram Mamidi, Elliott Slaughter, Kumar Prasun, Anil Nemili, S. M. Deshpande	An Implicitly Parallel Meshfree Solver in Regent.	PAW-ATM@SC	2020	DBLP DOI BibTeX RDF
33	Meng Meng, Soi Hoi Lam, Shoujie Li, Yiik Diew Wong	Public transit coordination under different strategies between operators.	MT-ITS	2015	DBLP DOI BibTeX RDF
33	Stefano Soi, Florian Daniel, Fabio Casati	Conceptual Development of Custom, Domain-Specific Mashup Platforms.	ACM Trans. Web	2014	DBLP DOI BibTeX RDF
33	Stefano Soi, Florian Daniel, Fabio Casati	Conceptual Design of Sound, Custom Composition Languages.	Web Services Foundations	2014	DBLP DOI BibTeX RDF
33	Stefano Soi	Domain Specific Mashup Platforms as a Service.		2013	RDF
33	Hendrik Gebhardt, Martin Gaedke, Florian Daniel, Stefano Soi, Fabio Casati, Carlos Angel Iglesias, Scott Wilson	From Mashups to Telco Mashups: A Survey.	IEEE Internet Comput.	2012	DBLP DOI BibTeX RDF
33	Florian Daniel, Stefano Soi, Stefano Tranquillini, Fabio Casati, Chang Heng, Li Yan	Distributed orchestration of user interfaces.	Inf. Syst.	2012	DBLP DOI BibTeX RDF
33	Fabio Casati, Florian Daniel, Antonella De Angeli, Muhammad Imran 0002, Stefano Soi, Chritopher R. Wilkinson, Maurizio Marchese	Developing Mashup Tools for End-Users: On the Importance of the Application Domain.	Int. J. Next Gener. Comput.	2012	DBLP BibTeX RDF
33	Muhammad Imran 0002, Felix Kling, Stefano Soi, Florian Daniel, Fabio Casati, Maurizio Marchese	ResEval mash: a mashup tool for advanced research evaluation.	WWW (Companion Volume)	2012	DBLP DOI BibTeX RDF
33	Florian Daniel, Muhammad Imran 0002, Felix Kling, Stefano Soi, Fabio Casati, Maurizio Marchese	Developing domain-specific mashup tools for end users.	WWW (Companion Volume)	2012	DBLP DOI BibTeX RDF
33	Muhammad Imran 0002, Stefano Soi, Felix Kling, Florian Daniel, Fabio Casati, Maurizio Marchese	On the Systematic Development of Domain-Specific Mashup Tools for End Users.	ICWE	2012	DBLP DOI BibTeX RDF
33	Johannes Tulusan, Lito Soi, Johannes Paefgen, Marc Brogle, Thorsten Staake	Eco-efficient feedback technologies: Which eco-feedback types prefer drivers most?	WOWMOM	2011	DBLP DOI BibTeX RDF
33	Scott Wilson, Florian Daniel, Uwe Jugel, Stefano Soi	Orchestrated User Interface Mashups Using W3C Widgets.	ICWE Workshops	2011	DBLP DOI BibTeX RDF
33	Florian Daniel, Stefano Soi, Fabio Casati	Distributed User Interface Orchestration: On the Composition of Multi-User (Search) Applications.	SeCO Workshop	2010	DBLP DOI BibTeX RDF
33	Florian Daniel, Stefano Soi, Stefano Tranquillini, Fabio Casati, Heng Chang, Yan Li	MarcoFlow: Modeling, Deploying, and Running Distributed User Interface Orchestrations.	BPM (Demos)	2010	DBLP BibTeX RDF
33	Florian Daniel, Stefano Soi, Stefano Tranquillini, Fabio Casati, Chang Heng, Li Yan	From People to Services to UI: Distributed Orchestration of User Interfaces.	BPM	2010	DBLP DOI BibTeX RDF
33	Soi Luong, Samuel Chong	Personalised Ambient Intelligence in Buildings Via Context-Aware Agents.	ICISO	2010	DBLP BibTeX RDF
33	Stefano Soi, Marcos Báez	Domain-Specific Mashups: From All to All You Need.	ICWE Workshops	2010	DBLP DOI BibTeX RDF
33	Shane T. Jensen, Sameer Soi, Li-San Wang	A Bayesian approach to efficient differential allocation for resampling-based significance testing.	BMC Bioinform.	2009	DBLP DOI BibTeX RDF
33	Florian Daniel, Fabio Casati, Stefano Soi, Jonny Fox, David Zancarli, Ming-Chien Shan	Hosted Universal Integration on the Web: The mashArt Platform.	ICSOC/ServiceWave	2009	DBLP DOI BibTeX RDF	Hosted Universal Integration, Services Composition, Mashups
33	Florian Daniel, Stefano Soi, Fabio Casati	From Mashup Technologies to Universal Integration: Search Computing the Imperative Way.	SeCO Workshop	2009	DBLP DOI BibTeX RDF