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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 298 occurrences of 245 keywords
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Results
Found 615 publication records. Showing 615 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
53 | Yin Chan, Sun-Yuan Kung |
Bit Level Block Matching Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 214-, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bit level systolic array, video signal processing architecture, pipeline, block matching |
47 | Panagiotis Manolios, Sudarshan K. Srinivasan |
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Autom. Reason. ![In: J. Autom. Reason. 37(1-2), pp. 93-116, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipelined machines, bit-level, verification, refinement, automated reasoning, ACL2 |
46 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 29-32, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
45 | Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong |
Bit-level optimization for high-level synthesis and FPGA-based acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 59-68, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bit-level optimization, fpga, high-level synthesis |
42 | Florent de Dinechin |
Libraries of schedule-free operators in Alpha. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 239-, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
schedule-free operators, digital circuits synthesis, bit-level, binary implementation, bit-level dependency analysis, bit-parallel array, parallelism, digital circuits, arithmetic operators, affine recurrence equations, matrix-vector product |
36 | Radhika S. Grover, Weijia Shang, Qiang Li |
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 422-431, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Ranjan Chaudhuri |
Teaching bit-level algorithm analysis to the undergraduates in computer science. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGCSE Bull. ![In: ACM SIGCSE Bull. 36(2), pp. 62-63, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bit-level, bit-size, algorithms, complexity, run-time |
33 | Jae-Jin Lee, Gi-Yong Song |
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 249, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Markus Wedler, Dominik Stoffel, Wolfgang Kunz |
Normalization at the arithmetic bit level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 457-462, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
arithmetic bit level normalization, SAT, property checking |
30 | Jing Jiang 0010, Krishna R. Narayanan |
Algebraic Soft-Decision Decoding of Reed-Solomon Codes Using Bit-Level Soft Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(9), pp. 3907-3928, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | A. Neslin Ismailoglu, Murat Askar |
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3259-3262, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001 |
BAT: The Bit-Level Analysis Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 19th International Conference, CAV 2007, Berlin, Germany, July 3-7, 2007, Proceedings, pp. 303-306, 2007, Springer, 978-3-540-73367-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Eirik Rosnes, Øyvind Ytrehus |
On the Design of Bit-Interleaved Turbo-Coded Modulation With Low Error Floors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(9), pp. 1563-1573, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed |
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 195-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations |
27 | Peter Kollig, Bashir M. Al-Hashimi |
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999, pp. 227-234, 1999, ACM, 1-58113-088-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
bit-level pipelined, circuit latency, FPGA, recursive algorithms |
26 | David Wentzlaff, Anant Agarwal |
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 289-290, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 215-223, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
25 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. |
Bit-level arithmetic optimization for carry-save additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 14-19, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 486-491, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
23 | John Patrick McGregor, Ruby B. Lee |
Architectural techniques for accelerating subword permutations with repetitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 325-335, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
22 | Per Gustafsson, Konstantinos Sagonas |
Applications, Implementation and Performance Evaluation of Bit Stream Programming in Erlang. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADL ![In: Practical Aspects of Declarative Languages, 9th International Symposium, PADL 2007, Nice, France, January 14-15, 2007., pp. 94-108, 2007, Springer, 978-3-540-69608-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Yuan Yang, Junfeng Hu, Hailin Zhang |
Bit-Level Deterministic Sequential Monte Carlo Method for MIMO Wireless Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 3622-3626, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Takashi Ajiro, Kensei Tsuchida |
A Bit-Level Concurrent Visual Programming Language (A-BITS) and a Base Computation Model (APC) for Its Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VL/HCC ![In: 2005 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC 2005), 21-24 September 2005, Dallas, TX, USA, pp. 269-271, 2005, IEEE Computer Society, 0-7695-2443-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ján Glasa |
On Bit-Level Systolic Arrays for Least-Squares Digital Contour Smoothing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part IV, pp. 18-25, 2004, Springer, 3-540-22129-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani |
A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 19th International Conference, CAV 2007, Berlin, Germany, July 3-7, 2007, Proceedings, pp. 547-560, 2007, Springer, 978-3-540-73367-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Hyeong-Gun Joo, Dong-Joon Shin, Song-Nam Hong |
Adaptive Bit-Reliability Mapping for LDPCCoded High-Order Modulation Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 1539-1543, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz |
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 398-403, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny |
Bit-Level systolic architectures for high performance IIR filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(1), pp. 9-24, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Graham A. Jullien, P. D. Bird, J. T. Carr, Majid Taheri, William C. Miller |
An efficient bit-level systolic cell design for finite ring digital signal processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(3), pp. 189-207, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
20 | Jianping He 0004, Jiahai Yang 0001, Changqing An, Xuenong Li |
BPR: a bit-level packet recovery in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), Honolulu, Hawaii, USA, March 9-12, 2009, pp. 59-65, 2009, ACM, 978-1-60558-166-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
packet recovery, wireless sensor networks, BPR |
20 | Dinesh Somasekhar, V. Visvanathan |
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 415-422, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
20 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Analytical estimation of signal transition activity from word-level statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7), pp. 718-733, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Sanghun Park, Kiyoung Choi |
Performance-driven high-level synthesis with bit-level chaining andclock selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2), pp. 199-212, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida |
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 617-627, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Roger F. Woods, John V. McCanny, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 35-49, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC architectures, DSP systems, pipelining, systolic arrays |
18 | Yong-Je Goo, Hanho Lee |
Two bit-level pipelined viterbi decoder for high-performance UWB applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1012-1015, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Takashi Ajiro, Kensei Tsuchida |
Visual programming language for bit-level concurrent programming: APECbits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VL/HCC ![In: IEEE Symposium on Visual Languages and Human-Centric Computing, VL/HCC 2008, Herrsching am Ammersee, Germany, 15-19 September 2008, Proceedings, pp. 113-116, 2008, IEEE Computer Society, 978-1-4244-2528-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Dominik Stoffel, Wolfgang Kunz |
Equivalence checking of arithmetic circuits on the arithmetic bit level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 586-597, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Pasin Israsena, S. Summerfield |
Bit-level retiming of high-speed digital recursive filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 19-24, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Mohammad K. Ibrahim, Abulaziz Almulhem |
Bit-level pipelined digit serial GF(2m) multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 586-589, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Ling Qiu, Jianxin Ma |
Bit-level probability shaping for partial parallel bit sequences based on power partition in OOFDM system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 47(1), pp. 9-17, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen 0001, Yi Kang |
Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(1), pp. 152-163, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor |
Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 216-221, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen 0001, Yi Kang |
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.00201, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Jou-An Chen, Hsin-Hsuan Sung, Nathan R. Tallent, Kevin J. Barker, Xipeng Shen, Ang Li 0006 |
Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2201.08560, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
17 | Jou-An Chen, Hsin-Hsuan Sung, Xipeng Shen, Nathan R. Tallent, Kevin J. Barker, Ang Li 0006 |
Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 2022 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2022, Lyon, France, May 30 - June 3, 2022, pp. 515-525, 2022, IEEE, 978-1-6654-8106-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Fangxin Liu, Wenbo Zhao 0005, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang 0002 |
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021, pp. 1-9, 2021, IEEE, 978-1-6654-4507-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Petrus Mursanto, R. Dimas Nugroho |
New Polynomial Based Bit-Level Serial GF(2m) Multiplier for RS(15, 11) 4-bit Codec Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWBIS ![In: 2018 International Workshop on Big Data and Information Security, IWBIS 2018, Jakarta, Indonesia, May 12-13, 2018, pp. 107-112, 2018, IEEE, 978-1-5386-5525-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh |
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA, June 1-6, 2018, pp. 764-775, 2018, IEEE Computer Society, 978-1-5386-5984-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Joon Kyung Kim, Vikas Chandra, Hadi Esmaeilzadeh |
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1712.01507, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
17 | Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang 0001 |
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | A. Neslin Ismailoglu, Murat Askar |
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 566-571, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang |
Design-for-testability and fault-tolerant techniques for FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 732-741, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Zhijie Shi, Ruby B. Lee |
Bit Permutation Instructions for Accelerating Software Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 138-148, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture |
16 | Madhu Sudan 0001 |
Maximum Likelihood Decoding of Reed Solomon Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 37th Annual Symposium on Foundations of Computer Science, FOCS '96, Burlington, Vermont, USA, 14-16 October, 1996, pp. 164-172, 1996, IEEE Computer Society, 0-8186-7594-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bit level soft decision decoding algorithm, low complexity code, coset properties, maximum likelihood decoding algorithm, soft output estimates, AWGN channel, BPSK signalling, Reed-Solomon codes, Reed Solomon codes, Galois field, SNR |
16 | Peter Kornerup, David W. Matula |
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1106-1115, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum |
16 | Yedidya Hilewitz, Cédric Lauradoux, Ruby B. Lee |
Bit matrix multiplication in commodity processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 7-12, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas |
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 252-257, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Sarah Thompson, Alan Mycroft |
Bit-level partial evaluation of synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PEPM ![In: Proceedings of the 2006 ACM SIGPLAN Workshop on Partial Evaluation and Semantics-based Program Manipulation, 2006, Charleston, South Carolina, USA, January 9-10, 2006, pp. 29-37, 2006, ACM, 1-59593-196-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
partial evaluation, loop unrolling, synchronous circuits |
15 | Chotirat (Ann) Ratanamahatana, Eamonn J. Keogh, Anthony J. Bagnall, Stefano Lonardi |
A Novel Bit Level Time Series Representation with Implication of Similarity Search and Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PAKDD ![In: Advances in Knowledge Discovery and Data Mining, 9th Pacific-Asia Conference, PAKDD 2005, Hanoi, Vietnam, May 18-20, 2005, Proceedings, pp. 771-777, 2005, Springer, 3-540-26076-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi |
Enhanced TED: A New Data Structure for RTL Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 481-486, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Berk Sunar, David Cyganski |
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 237-249, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Horner’s method, word level, finite fields, multivariate polynomials, polynomial evaluation |
15 | Hanqing Xing, Degang Chen 0001, Randall L. Geiger |
On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 117-122, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Kroening, Sanjit A. Seshia |
Formal verification at higher levels of abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 572-578, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Minar El-Aasser, Phoebe Edward, Mohamed Mandour, Mohamed Ashour, Tallal Elshabrawy |
A comprehensive hybrid bit-level and packet-level LoRa-LPWAN simulation model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Things ![In: Internet Things 14, pp. 100386, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Shahna K. U., Anuj Mohamed |
A novel image encryption scheme using both pixel level and bit level permutation with chaotic map. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Soft Comput. ![In: Appl. Soft Comput. 90, pp. 106162, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Yanghong Wu, Pengpeng Zhao, Yanchi Liu, Victor S. Sheng, Junhua Fang, Fuzhen Zhuang |
Vector-Level and Bit-Level Feature Adjusted Factorization Machine for Sparse Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASFAA (1) ![In: Database Systems for Advanced Applications - 25th International Conference, DASFAA 2020, Jeju, South Korea, September 24-27, 2020, Proceedings, Part I, pp. 386-402, 2020, Springer, 978-3-030-59409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Sangjoon Park, Sooyong Choi |
Performance of Symbol-Level Combining and Bit-Level Combining in MIMO Multiple ARQ Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 64(4), pp. 1517-1528, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
15 | Clément Fumex, Claire Dross, Jens Gerlach, Claude Marché |
Specification and Proof of High-Level Functional Properties of Bit-Level Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NFM ![In: NASA Formal Methods - 8th International Symposium, NFM 2016, Minneapolis, MN, USA, June 7-9, 2016, Proceedings, pp. 291-306, 2016, Springer, 978-3-319-40647-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
15 | Wenchao Li 0001, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari 0001, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia |
WordRev: Finding word-level structures in a sea of bit-level gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013, pp. 67-74, 2013, IEEE Computer Society, 978-1-4799-0559-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
15 | Mehmet Kayaalp 0001, Fahrettin Koc, Oguz Ergin |
Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012, pp. 280-287, 2012, IEEE Computer Society, 978-1-4673-2498-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita |
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 92-D(5), pp. 972-984, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Ranjit Jhala, Rupak Majumdar |
Bit level types for high level reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGSOFT FSE ![In: Proceedings of the 14th ACM SIGSOFT International Symposium on Foundations of Software Engineering, FSE 2006, Portland, Oregon, USA, November 5-11, 2006, pp. 128-140, 2006, ACM, 1-59593-468-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
model checking, type inference, bit vectors |
15 | Javier J. Sánchez Medina, Manuel J. Galán Moreno, Enrique Rubio |
Bit Level Versus Gene Level Crossover in a Traffic Modeling Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIMCA/IAWTIC ![In: 2005 International Conference on Computational Intelligence for Modelling Control and Automation (CIMCA 2005), International Conference on Intelligent Agents, Web Technologies and Internet Commerce (IAWTIC 2005), 28-30 November 2005, Vienna, Austria, pp. 1190-1195, 2005, IEEE Computer Society, 0-7695-2504-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | José Incera, Gerardo Rubino |
Bit-Level and Packet-Level, or Pollaczec-Khintchine Formulae Revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QEST ![In: 1st International Conference on Quantitative Evaluation of Systems (QEST 2004), 27-30 September 2004, Enschede, The Netherlands, pp. 82-89, 2004, IEEE Computer Society, 0-7695-2185-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Pallab Dasgupta, P. P. Chakrabarti 0001, Amit Nandi, Sekar Krishna, Arindam Chakrabarti |
Abstraction of word-level linear arithmetic functions from bit-level component descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 4-8, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Radomir S. Stankovic, Milena Stankovic, Jaakko Astola, Karen O. Egiazarian |
Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 31st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2001, Warsaw, Poland, May 22-24, 2001, Proceedings, pp. 305-310, 2001, IEEE Computer Society, 0-7695-1083-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Efstathios D. Kyriakis-Bitzaros, Spiridon Nikolaidis 0001, Anna Tatsaki |
Accurate calculation of bit-level transition activity using word-level statistics and entropy function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 607-610, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Bernd Becker 0001, Rolf Drechsler, Reinhard Enders |
On the representational power of bit-level and word-level decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 461-467, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | John V. McCanny |
Mapping system level functions on to bit level systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 1986, Tokyo, Japan, April 7-11, 1986, pp. 2159-2162, 1986, IEEE. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
14 | Darryl Dexu Lin, Teng Joon Lim |
Bit-Level Equalization and Soft Detection for Gray-Coded Multilevel Modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(10), pp. 4731-4742, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Anton Blad, Oscar Gustafsson |
Bit-level optimized FIR filter architectures for high-speed decimation applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1914-1917, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Sergey Tverdyshev, Eyad Alkassar |
Efficient Bit-Level Model Reductions for Automated Hardware Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TIME ![In: 15th International Symposium on Temporal Representation and Reasoning, TIME 2008, Université du Québec à Montréal, Canada, 16-18 June 2008, pp. 164-172, 2008, IEEE Computer Society, 978-0-7695-3181-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Min Woo Kim, Jun Dong Cho |
A VLSI Design of High Speed Bit-level Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 309-312, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida |
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 99-104, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | María C. Molina, José M. Mendías, Román Hermida |
Bit-Level Allocation of Multiple-Precision Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 385-392, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | María C. Molina, José M. Mendías, Román Hermida |
Bit-level scheduling of heterogeneous behavioural specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 602-608, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | M. Yan, John V. McCanny |
A bit-level systolic architecture for implementing a VQ tree search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(3), pp. 149-158, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Stuart Lawson, Steve Summerfield |
The design of wave digital filters using fully pipelined bit-level systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(1), pp. 7, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Muhammad Usman Ilyas, Hayder Radha |
Measurement Based Analysis and Modeling of the Error Process in IEEE 802.15.4 LR-WPANs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 1274-1282, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi 0001 |
Evolutionary Synthesis of Arithmetic Circuit Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Rev. ![In: Artif. Intell. Rev. 20(3-4), pp. 199-232, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
genetic algorithms, genetic programming, evolutionary computation, multiple-valued logic, arithmetic circuits, evolutionary design, circuit design |
14 | Andrea Acquaviva, Alessandro Bogliolo |
A Bottom-Up Approach to On-Chip Signal Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 540-549, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
High-level macro-modeling and estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 538-557, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Oskar Mencer |
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 67-76, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Eric Whitman Smith, David L. Dill |
Automatic Formal Verification of Block Cipher Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, FMCAD 2008, Portland, Oregon, USA, 17-20 November 2008, pp. 1-7, 2008, IEEE, 978-1-4244-2735-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Usman Ilyas, Hayder Radha |
On measuring memory length of the error rate process in wireless channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: 42nd Annual Conference on Information Sciences and Systems, CISS 2008, Princeton, NJ, USA, 19-21 March 2008, pp. 1262-1267, 2008, IEEE, 978-1-4244-2246-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit |
Fast, Accurate and Detailed NoC Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 323-332, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Tamás Szabó, Lörinc Antoni, Gábor Horváth 0001, Béla Fehér |
A Full-Parallel Digital Implementation for Pre-Trained NNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (2) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 2, pp. 49-54, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Kroening, Georg Weissenbacher |
Lifting Propositional Interpolants to the Word-Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 85-89, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
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