Search results for "bit-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
47	Panagiotis Manolios, Sudarshan K. Srinivasan	A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.	J. Autom. Reason.	2006	DBLP DOI BibTeX RDF	pipelined machines, bit-level, verification, refinement, automated reasoning, ACL2
46	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
45	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
42	Florent de Dinechin	Libraries of schedule-free operators in Alpha.	ASAP	1997	DBLP DOI BibTeX RDF	schedule-free operators, digital circuits synthesis, bit-level, binary implementation, bit-level dependency analysis, bit-parallel array, parallelism, digital circuits, arithmetic operators, affine recurrence equations, matrix-vector product
36	Radhika S. Grover, Weijia Shang, Qiang Li	A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
34	Ranjan Chaudhuri	Teaching bit-level algorithm analysis to the undergraduates in computer science.	ACM SIGCSE Bull.	2004	DBLP DOI BibTeX RDF	bit-level, bit-size, algorithms, complexity, run-time
33	Jae-Jin Lee, Gi-Yong Song	Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.	FPGA	2004	DBLP DOI BibTeX RDF
30	Markus Wedler, Dominik Stoffel, Wolfgang Kunz	Normalization at the arithmetic bit level.	DAC	2005	DBLP DOI BibTeX RDF	arithmetic bit level normalization, SAT, property checking
30	Jing Jiang 0010, Krishna R. Narayanan	Algebraic Soft-Decision Decoding of Reed-Solomon Codes Using Bit-Level Soft Information.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
28	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001	BAT: The Bit-Level Analysis Tool.	CAV	2007	DBLP DOI BibTeX RDF
27	Eirik Rosnes, Øyvind Ytrehus	On the Design of Bit-Interleaved Turbo-Coded Modulation With Low Error Floors.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
27	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
27	Peter Kollig, Bashir M. Al-Hashimi	Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.	FPGA	1999	DBLP DOI BibTeX RDF	bit-level pipelined, circuit latency, FPGA, recursive algorithms
26	David Wentzlaff, Anant Agarwal	A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation.	FCCM	2004	DBLP DOI BibTeX RDF
26	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
25	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
24	Joan Carletta, Christos A. Papachristou	Structural constraints for circular self-test paths.	VTS	1995	DBLP DOI BibTeX RDF	circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
23	John Patrick McGregor, Ruby B. Lee	Architectural techniques for accelerating subword permutations with repetitions.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
22	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
22	Per Gustafsson, Konstantinos Sagonas	Applications, Implementation and Performance Evaluation of Bit Stream Programming in Erlang.	PADL	2007	DBLP DOI BibTeX RDF
22	Yuan Yang, Junfeng Hu, Hailin Zhang	Bit-Level Deterministic Sequential Monte Carlo Method for MIMO Wireless Systems.	ICC	2008	DBLP DOI BibTeX RDF
22	Takashi Ajiro, Kensei Tsuchida	A Bit-Level Concurrent Visual Programming Language (A-BITS) and a Base Computation Model (APC) for Its Development.	VL/HCC	2005	DBLP DOI BibTeX RDF
22	Ján Glasa	On Bit-Level Systolic Arrays for Least-Squares Digital Contour Smoothing.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
21	Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani	A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems.	CAV	2007	DBLP DOI BibTeX RDF
21	Hyeong-Gun Joo, Dong-Joon Shin, Song-Nam Hong	Adaptive Bit-Reliability Mapping for LDPCCoded High-Order Modulation Systems.	VTC Spring	2007	DBLP DOI BibTeX RDF
21	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny	Bit-Level systolic architectures for high performance IIR filtering.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
21	Graham A. Jullien, P. D. Bird, J. T. Carr, Majid Taheri, William C. Miller	An efficient bit-level systolic cell design for finite ring digital signal processing applications.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
20	Jianping He 0004, Jiahai Yang 0001, Changqing An, Xuenong Li	BPR: a bit-level packet recovery in wireless sensor networks.	SAC	2009	DBLP DOI BibTeX RDF	packet recovery, wireless sensor networks, BPR
20	Dinesh Somasekhar, V. Visvanathan	A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
20	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Analytical estimation of signal transition activity from word-level statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	Sanghun Park, Kiyoung Choi	Performance-driven high-level synthesis with bit-level chaining andclock selection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida	Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.	PATMOS	2003	DBLP DOI BibTeX RDF
18	Roger F. Woods, John V. McCanny, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	SoC architectures, DSP systems, pipelining, systolic arrays
18	Yong-Je Goo, Hanho Lee	Two bit-level pipelined viterbi decoder for high-performance UWB applications.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Takashi Ajiro, Kensei Tsuchida	Visual programming language for bit-level concurrent programming: APECbits.	VL/HCC	2008	DBLP DOI BibTeX RDF
18	Dominik Stoffel, Wolfgang Kunz	Equivalence checking of arithmetic circuits on the arithmetic bit level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
18	Pasin Israsena, S. Summerfield	Bit-level retiming of high-speed digital recursive filters.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
18	Mohammad K. Ibrahim, Abulaziz Almulhem	Bit-level pipelined digit serial GF(2m) multiplier.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
17	Ling Qiu, Jianxin Ma	Bit-level probability shaping for partial parallel bit sequences based on power partition in OOFDM system.	Photonic Netw. Commun.	2024	DBLP DOI BibTeX RDF
17	Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen 0001, Yi Kang	Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
17	Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor	Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks.	VLSID	2024	DBLP DOI BibTeX RDF
17	Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen 0001, Yi Kang	Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity.	CoRR	2023	DBLP DOI BibTeX RDF
17	Jou-An Chen, Hsin-Hsuan Sung, Nathan R. Tallent, Kevin J. Barker, Xipeng Shen, Ang Li 0006	Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU.	CoRR	2022	DBLP BibTeX RDF
17	Jou-An Chen, Hsin-Hsuan Sung, Xipeng Shen, Nathan R. Tallent, Kevin J. Barker, Ang Li 0006	Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU.	IPDPS	2022	DBLP DOI BibTeX RDF
17	Fangxin Liu, Wenbo Zhao 0005, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang 0002	Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.	ICCAD	2021	DBLP DOI BibTeX RDF
17	Petrus Mursanto, R. Dimas Nugroho	New Polynomial Based Bit-Level Serial GF(2m) Multiplier for RS(15, 11) 4-bit Codec Optimization.	IWBIS	2018	DBLP DOI BibTeX RDF
17	Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh	Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.	ISCA	2018	DBLP DOI BibTeX RDF
17	Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Joon Kyung Kim, Vikas Chandra, Hadi Esmaeilzadeh	Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks.	CoRR	2017	DBLP BibTeX RDF
17	Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang 0001	A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
16	A. Neslin Ismailoglu, Murat Askar	SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.	DSD	2008	DBLP DOI BibTeX RDF
16	Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang	Design-for-testability and fault-tolerant techniques for FFT processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Zhijie Shi, Ruby B. Lee	Bit Permutation Instructions for Accelerating Software Cryptography.	ASAP	2000	DBLP DOI BibTeX RDF	bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture
16	Madhu Sudan 0001	Maximum Likelihood Decoding of Reed Solomon Codes.	FOCS	1996	DBLP DOI BibTeX RDF	bit level soft decision decoding algorithm, low complexity code, coset properties, maximum likelihood decoding algorithm, soft output estimates, AWGN channel, BPSK signalling, Reed-Solomon codes, Reed Solomon codes, Galois field, SNR
16	Peter Kornerup, David W. Matula	An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum
16	Yedidya Hilewitz, Cédric Lauradoux, Ruby B. Lee	Bit matrix multiplication in commodity processors.	ASAP	2008	DBLP DOI BibTeX RDF
16	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
15	Sarah Thompson, Alan Mycroft	Bit-level partial evaluation of synchronous circuits.	PEPM	2006	DBLP DOI BibTeX RDF	partial evaluation, loop unrolling, synchronous circuits
15	Chotirat (Ann) Ratanamahatana, Eamonn J. Keogh, Anthony J. Bagnall, Stefano Lonardi	A Novel Bit Level Time Series Representation with Implication of Similarity Search and Clustering.	PAKDD	2005	DBLP DOI BibTeX RDF
15	Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi	Enhanced TED: A New Data Structure for RTL Verification.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Berk Sunar, David Cyganski	Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings.	CHES	2005	DBLP DOI BibTeX RDF	Horner’s method, word level, finite fields, multivariate polynomials, polynomial evaluation
15	Hanqing Xing, Degang Chen 0001, Randall L. Geiger	On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering.	EIT	2008	DBLP DOI BibTeX RDF
15	Daniel Kroening, Sanjit A. Seshia	Formal verification at higher levels of abstraction.	ICCAD	2007	DBLP DOI BibTeX RDF
15	Minar El-Aasser, Phoebe Edward, Mohamed Mandour, Mohamed Ashour, Tallal Elshabrawy	A comprehensive hybrid bit-level and packet-level LoRa-LPWAN simulation model.	Internet Things	2021	DBLP DOI BibTeX RDF
15	Shahna K. U., Anuj Mohamed	A novel image encryption scheme using both pixel level and bit level permutation with chaotic map.	Appl. Soft Comput.	2020	DBLP DOI BibTeX RDF
15	Yanghong Wu, Pengpeng Zhao, Yanchi Liu, Victor S. Sheng, Junhua Fang, Fuzhen Zhuang	Vector-Level and Bit-Level Feature Adjusted Factorization Machine for Sparse Prediction.	DASFAA (1)	2020	DBLP DOI BibTeX RDF
15	Sangjoon Park, Sooyong Choi	Performance of Symbol-Level Combining and Bit-Level Combining in MIMO Multiple ARQ Systems.	IEEE Trans. Commun.	2016	DBLP DOI BibTeX RDF
15	Clément Fumex, Claire Dross, Jens Gerlach, Claude Marché	Specification and Proof of High-Level Functional Properties of Bit-Level Programs.	NFM	2016	DBLP DOI BibTeX RDF
15	Wenchao Li 0001, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari 0001, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia	WordRev: Finding word-level structures in a sea of bit-level gates.	HOST	2013	DBLP DOI BibTeX RDF
15	Mehmet Kayaalp 0001, Fahrettin Koc, Oguz Ergin	Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration.	DSD	2012	DBLP DOI BibTeX RDF
15	Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita	Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.	IEICE Trans. Inf. Syst.	2009	DBLP DOI BibTeX RDF
15	Ranjit Jhala, Rupak Majumdar	Bit level types for high level reasoning.	SIGSOFT FSE	2006	DBLP DOI BibTeX RDF	model checking, type inference, bit vectors
15	Javier J. Sánchez Medina, Manuel J. Galán Moreno, Enrique Rubio	Bit Level Versus Gene Level Crossover in a Traffic Modeling Environment.	CIMCA/IAWTIC	2005	DBLP DOI BibTeX RDF
15	José Incera, Gerardo Rubino	Bit-Level and Packet-Level, or Pollaczec-Khintchine Formulae Revisited.	QEST	2004	DBLP DOI BibTeX RDF
15	Pallab Dasgupta, P. P. Chakrabarti 0001, Amit Nandi, Sekar Krishna, Arindam Chakrabarti	Abstraction of word-level linear arithmetic functions from bit-level component descriptions.	DATE	2001	DBLP DOI BibTeX RDF
15	Radomir S. Stankovic, Milena Stankovic, Jaakko Astola, Karen O. Egiazarian	Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies.	ISMVL	2001	DBLP DOI BibTeX RDF
15	Efstathios D. Kyriakis-Bitzaros, Spiridon Nikolaidis 0001, Anna Tatsaki	Accurate calculation of bit-level transition activity using word-level statistics and entropy function.	ICCAD	1998	DBLP DOI BibTeX RDF
15	Bernd Becker 0001, Rolf Drechsler, Reinhard Enders	On the representational power of bit-level and word-level decision diagrams.	ASP-DAC	1997	DBLP DOI BibTeX RDF
15	John V. McCanny	Mapping system level functions on to bit level systolic arrays.	ICASSP	1986	DBLP DOI BibTeX RDF
14	Darryl Dexu Lin, Teng Joon Lim	Bit-Level Equalization and Soft Detection for Gray-Coded Multilevel Modulation.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
14	Anton Blad, Oscar Gustafsson	Bit-level optimized FIR filter architectures for high-speed decimation applications.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Sergey Tverdyshev, Eyad Alkassar	Efficient Bit-Level Model Reductions for Automated Hardware Verification.	TIME	2008	DBLP DOI BibTeX RDF
14	Min Woo Kim, Jun Dong Cho	A VLSI Design of High Speed Bit-level Viterbi Decoder.	APCCAS	2006	DBLP DOI BibTeX RDF
14	María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida	Behavioural Scheduling to Balance the Bit-Level Computational Effort.	ISVLSI	2004	DBLP DOI BibTeX RDF
14	María C. Molina, José M. Mendías, Román Hermida	Bit-Level Allocation of Multiple-Precision Specifications.	DSD	2002	DBLP DOI BibTeX RDF
14	María C. Molina, José M. Mendías, Román Hermida	Bit-level scheduling of heterogeneous behavioural specifications.	ICCAD	2002	DBLP DOI BibTeX RDF
14	M. Yan, John V. McCanny	A bit-level systolic architecture for implementing a VQ tree search.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
14	Stuart Lawson, Steve Summerfield	The design of wave digital filters using fully pipelined bit-level systolic arrays.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
14	Muhammad Usman Ilyas, Hayder Radha	Measurement Based Analysis and Modeling of the Error Process in IEEE 802.15.4 LR-WPANs.	INFOCOM	2008	DBLP DOI BibTeX RDF
14	Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi 0001	Evolutionary Synthesis of Arithmetic Circuit Structures.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	genetic algorithms, genetic programming, evolutionary computation, multiple-valued logic, arithmetic circuits, evolutionary design, circuit design
14	Andrea Acquaviva, Alessandro Bogliolo	A Bottom-Up Approach to On-Chip Signal Integrity.	PATMOS	2003	DBLP DOI BibTeX RDF
14	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
13	Oskar Mencer	PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs.	FCCM	2002	DBLP DOI BibTeX RDF
13	Eric Whitman Smith, David L. Dill	Automatic Formal Verification of Block Cipher Implementations.	FMCAD	2008	DBLP DOI BibTeX RDF
13	Muhammad Usman Ilyas, Hayder Radha	On measuring memory length of the error rate process in wireless channels.	CISS	2008	DBLP DOI BibTeX RDF
13	Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit	Fast, Accurate and Detailed NoC Simulations.	NOCS	2007	DBLP DOI BibTeX RDF
13	Tamás Szabó, Lörinc Antoni, Gábor Horváth 0001, Béla Fehér	A Full-Parallel Digital Implementation for Pre-Trained NNs.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
13	Daniel Kroening, Georg Weissenbacher	Lifting Propositional Interpolants to the Word-Level.	FMCAD	2007	DBLP DOI BibTeX RDF