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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2996 occurrences of 1338 keywords
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Results
Found 4838 publication records. Showing 4828 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
80 | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |
A genetic algorithm-based system for generating test programs for microprocessor IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 13-15 November 2000, Vancouver, BC, Canada, pp. 195-198, 2000, IEEE Computer Society, 0-7695-0909-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing |
68 | Pierre Salverda, Craig B. Zilles |
Fundamental performance constraints in horizontal fusion of in-order cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 252-263, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
68 | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1203-1212, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
63 | Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty |
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(3), pp. 409-423, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
62 | Jaime H. Moreno |
Chip-level integration: the new frontier for microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 328, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip-level integration, microprocessor architecture |
57 | Srinivasan Murali, Giovanni De Micheli |
Bandwidth-Constrained Mapping of Cores onto NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 896-903, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores |
57 | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
Architectures and algorithms for synthesizable embedded programmable logic cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 3-11, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
programmable logic cores, FPGA, standard cells, system-on-chip design |
57 | Peter Hallschmid, Steven J. E. Wilton |
Detailed routing architectures for embedded programmable logic IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 69-74, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, detailed routing, SoC design, embedded cores |
57 | Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor |
Conservation cores: reducing the energy of mature computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 205-218, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
conservation core, heterogeneous many-core, utilization wall, patching |
56 | Kuen-Jong Lee, Cheng-I Huang |
A hierarchical test control architecture for core based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 248-253, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design |
53 | Avi Mendelson |
Current trends in computer architectures: multi-cores, many-cores and special-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 21th Annual International Conference on Supercomputing, ICS 2007, Seattle, Washington, USA, June 17-21, 2007, pp. 1, 2007, ACM, 978-1-59593-768-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Nur A. Touba, Bahram Pouya |
Testing Embedded Cores Using Partial Isolation Rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 10-16, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing |
51 | Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid |
Web search using mobile cores: quantifying and mitigating the price of efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 314-325, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bing, mobile cores, energy efficiency, web search |
51 | Daniel Ziener, Jürgen Teich |
Power Signature Watermarking of IP Cores for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 123-136, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
IPP, FPGA, watermarking, signature, power analysis, IP cores |
51 | Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas |
The BubbleWrap many-core: popping cores for sequential acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 447-458, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
power wall, process scaling, processor aging, voltage scaling |
51 | Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian |
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 371-378, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Juan Carlos Saez, Manuel Prieto 0001, Alexandra Fedorova, Sergey Blagodurov |
A comprehensive scheduler for asymmetric multicore systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: European Conference on Computer Systems, Proceedings of the 5th European conference on Computer systems, EuroSys 2010, Paris, France, April 13-16, 2010, pp. 139-152, 2010, ACM, 978-1-60558-577-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asymmetric multicore, scheduling, operating systems |
51 | Vahid Kazempour, Ali Kamali, Alexandra Fedorova |
AASH: an asymmetry-aware scheduler for hypervisors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 6th International Conference on Virtual Execution Environments, VEE 2010, Pittsburgh, Pennsylvania, USA, March 17-19, 2010, pp. 85-96, 2010, ACM, 978-1-60558-910-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
heterogeneous, scheduling algorithms, multicore processors, virtual machine monitor, hypervisor, asymmetric |
51 | Enric Musoll |
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 201-207, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan |
A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 182-184, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
manycore chips, submesh allocation, algorithm, noc, temperature |
51 | Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský |
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 300-308, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Qiang Xu 0001, Nicola Nicolici |
Modular SOC testing with reduced wrapper count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1894-1908, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | A. Schubert, Walter Anheier |
On Random Pattern Testability of Cryptographic VLSI Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 185-192, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing |
46 | Tony Givargis, Frank Vahid, Jörg Henkel |
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 163-171, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
silicon platforms, caches, low-power design, estimation, System-on-a-chip, intellectual property, cores, system parameters |
46 | Andy Yan, Steven J. E. Wilton |
Product-Term-Based Synthesizable Embedded Programmable Logic Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 474-488, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | John D. Davis, James Laudon, Kunle Olukotun |
Maximizing CMP Throughput with Mediocre Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, pp. 51-62, 2005, IEEE Computer Society, 0-7695-2429-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Alex K. Jones, Prithviraj Banerjee |
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 244, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Lukás Sekanina |
Towards Evolvable IP Cores for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 145-154, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin |
Test Scheduling of BISTed Memory Cores for SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 356-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Daniel Zappala, Aaron Fabbri |
An Evaluation of Shared Multicast Trees with Multiple Active Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN (1) ![In: Networking - ICN 2001, First International Conference, Colmar, France, July 9-13, 2001 Proceedings, Part 1, pp. 620-629, 2001, Springer, 3-540-42302-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Hans G. Kerkhoff, Jarkko J. M. Huijts |
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 38-44, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair |
45 | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 |
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 52-61, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ia32, on-chip integration, chip multiprocessor, heterogeneous |
40 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Instruction-Based Self-Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 103-112, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
processor cores, built-in self-test, instruction set, at-speed testing, software-based self test |
40 | Tony Givargis, Frank Vahid, Jörg Henkel |
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 306-312, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
low power system design, parameterized architectures, system-on-a-chip, intellectual property, cores, system-level modeling |
40 | Ilker Hamzaoglu, Janak H. Patel |
Reducing Test Application Time for Full Scan Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 260-267, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
test generation, design-for-testability, fault simulation, embedded cores, full scan |
40 | Kaushik De |
Test methodology for embedded cores which protects intellectual property. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 2-9, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology |
40 | Wei Zhao, Christos A. Papachristou |
Synthesis of reusable DSP cores based on multiple behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 103-108, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips |
40 | Tameesh Suri, Aneesh Aggarwal |
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 145-150, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna |
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 167-176, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
Dependability Assessment for the Selection of Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Seventh European Dependable Computing Conference, EDCC-7 2008, Kaunas, Lithuania, 7-9 May 2008, pp. 79-84, 2008, IEEE Computer Society, 978-0-7695-3138-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | David Tarjan, Michael Boyer, Kevin Skadron |
Federation: repurposing scalar cores for out-of-order instruction issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 772-775, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMP, multicore, federation, out-of-order |
40 | Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty |
Test infrastructure design for mixed-signal SOCs with wrapped analog cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(3), pp. 292-304, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Simin Dai, Elaheh Bozorgzadeh |
CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 329-330, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Mario Donato Marino |
32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 17-20 October 2006, Ouro Preto, Minas Gerais, Brazil, pp. 141-150, 2006, IEEE Computer Society, 0-7695-2704-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Anuja Sehgal, Fang Liu 0029, Sule Ozev, Krishnendu Chakrabarty |
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 50-55, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Optimal Spare Utilization in Repairable and Reliable Memory Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 64-71, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair |
40 | Magnus Ekman, Per Stenström |
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 359-368, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Anoop Iyer, Diana Marculescu |
Power efficiency of voltage scaling in multiple clock, multiple voltage cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 379-386, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng |
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 198-203, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Philip James-Roxby, Steven A. Guccione |
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 153-164, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003 |
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 156-166, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GPU, openMP, heterogeneous multi-cores |
39 | Pierre Michaud, Yiannakis Sazeides, André Seznec |
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 237-246, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
activity migration, sequential performance, power, multicore, temperature, cache misses, manycore |
39 | Mario Donato Marino |
L2-Cache Hierarchical Organizations for Multi-core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking - ISPA 2006 Workshops, ISPA 2006 International Workshops, FHPCN, XHPC, S-GRACE, GridGIS, HPC-GTP, PDCE, ParDMCom, WOMP, ISDF, and UPWN, Sorrento, Italy, December 4-7, 2006, Proceedings, pp. 74-83, 2006, Springer, 3-540-49860-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec |
Performance implications of single thread migration on a chip multi-core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(4), pp. 80-91, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Francesco Menichelli, Mauro Olivieri, Simone Smorfa |
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 1483-1486, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
35 | Swann Perarnau, Guillaume Huard |
KRASH: reproducible CPU load generation on many cores machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2010, Bangalore, India, January 9-14, 2010, pp. 327-328, 2010, ACM, 978-1-60558-877-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cpu load generation, many cores, experimentation testbed |
35 | Roman L. Lysecky, Frank Vahid |
Prefetching for improved bus wrapper performance in cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 58-90, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus |
35 | T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua |
Compiler-directed customization of ASIP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 97-102, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
soft cores, embedded, customization, ASIP |
35 | Yulu Ma, Shiduan Cheng |
Multi-Cores Uni-Directional Shared Trees Multicast Routing Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 495-496, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-cores uni-directional shared trees, CBT, PIM-SM, intradomain multicast routing protocols, efficient member management mechanism, authentication, protocols, admission control, trees (mathematics), telecommunication network routing, multicast communication, multicast group, packet transmission |
35 | Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas |
Verification of configurable processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 426-431, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis |
35 | Omer Khan, Sandip Kundu |
A self-adaptive scheduler for asymmetric multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 397-400, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
scheduling, modeling, power |
35 | Tameesh Suri, Aneesh Aggarwal |
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 151-160, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data value prediction, dynamic reconfiguration, loop level parallelism |
35 | Takanori Ueda, Yu Hirate, Hayato Yamana |
Exploiting idle CPU cores to improve file access performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUIMC ![In: Proceedings of the 3rd International Conference on Ubiquitous Information Management and Communication, ICUIMC 2009, Suwon, Korea, January 15-16, 2009, pp. 529-535, 2009, ACM, 978-1-60558-405-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
access pattern mining, many core, access pattern, replacement algorithm, buffer caching |
35 | Albert Meixner, Daniel J. Sorin |
Detouring: Translating software to circumvent hard faults in simple cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 80-89, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Qiang Xu 0001, Nicola Nicolici, Krishnendu Chakrabarty |
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8), pp. 1539-1547, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 271-276, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoding Chen, Michael S. Hsiao |
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(2), pp. 150-162, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
built-in-self-test, System-on-a-chip, spectral analysis |
35 | Daniel Ziener, Stefan Assmus, Jürgen Teich |
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Umar Farooq 0009, Muhammad Saleem, Habibullah Jamal |
Parameterized FIR Filtering IP Cores for Reusable SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 554-559, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Finite Impulse Response (FIR) filter, Unfolded Direct Form (UDF), Folded Direct Form (FDF), Parameterized, SoC design, IP Core, Synthesis tools |
35 | Haihua Shen, Yunji Chen, Jing Huang |
EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 528-535, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis |
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20014-20019, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Huaguo Liang, Cuiyun Jiang |
Sharing BIST with Multiple Cores for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 418-423, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Effective Software Self-Test Methodology for Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 592-597, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | K. Y. Ko, Mike W. T. Wong, Yim-Shu Lee |
Testing System-On-Chip by Summations of Cores? Test Output Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 350-355, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Satnam Singh, Carl Johan Lillieroth |
Formal Verification of Reconfigurable Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 25-, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Janusz Rajski, Jerzy Tyszer |
Modular logic built-in self-test for IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 313-321, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh |
Parallelism via Multithreaded and Multicore CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 43(3), pp. 24-32, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Multithreaded cores, Heterogeneous cores, Application-level parallelism, Chip interconnects, GPUs, Multicore processors, Power efficiency |
34 | Roman L. Lysecky, Frank Vahid |
Design and implementation of a MicroBlaze-based warp processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 22:1-22:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
34 | Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger |
Multitasking workload scheduling on flexible-core chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 187-196, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flexible cores, multitask scheduling, multicore architectures |
34 | Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian |
On IEEE P1500's Standard for Embedded Core Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 365-383, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
core test wrapper, core test language, compliance levels, standardization, embedded cores |
34 | Roman L. Lysecky, Frank Vahid, Tony Givargis |
Techniques for Reducing Read Latency of Core Bus Wrappers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 84-91, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus |
34 | Major Bhadauria, Vincent M. Weaver, Sally A. McKee |
Accomodating Diversity in CMPs with Heterogeneous Frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 248-262, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti |
A compiler-directed data prefetching scheme for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 209-218, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, chip multiprocessors, prefetching, helper thread |
34 | Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal |
Multi-core architectures and streaming applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 35-42, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC design, multi-core SoC design, system design, streaming applications |
34 | Mijeom Kim, Mohan Kumar, Behrooz A. Shirazi |
An Integrated Scheme for Address Assignment and Service Location in Pervasive Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 967-976, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Indradeep Ghosh, Niraj K. Jha, Sujit Dey |
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11), pp. 1661-1676, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Brais Bosquet, Daniel Cores, Lorenzo Seidenari, Víctor M. Brea 0001, Manuel Mucientes, Alberto Del Bimbo |
A full data augmentation pipeline for small object detection based on generative adversarial networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pattern Recognit. ![In: Pattern Recognit. 133, pp. 108998, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes |
Spatiotemporal tubelet feature aggregation and object linking for small object detection in videos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 53(1), pp. 1205-1217, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Nicolás Vila Blanco, Manuel Mucientes, María J. Carreira |
Few-Shot Image Classification for Automatic COVID-19 Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IbPRIA ![In: Pattern Recognition and Image Analysis - 11th Iberian Conference, IbPRIA 2023, Alicante, Spain, June 27-30, 2023, Proceedings, pp. 545-556, 2023, Springer, 978-3-031-36615-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Lorenzo Seidenari, Alberto Del Bimbo, Víctor M. Brea 0001, Manuel Mucientes |
Relation Networks for Few-Shot Video Object Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IbPRIA ![In: Pattern Recognition and Image Analysis - 11th Iberian Conference, IbPRIA 2023, Alicante, Spain, June 27-30, 2023, Proceedings, pp. 238-248, 2023, Springer, 978-3-031-36615-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes, Lorenzo Seidenari, Alberto Del Bimbo |
Downsampling GAN for Small Object Data Augmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP (1) ![In: Computer Analysis of Images and Patterns - 20th International Conference, CAIP 2023, Limassol, Cyprus, September 25-28, 2023, Proceedings, Part I, pp. 89-98, 2023, Springer, 978-3-031-44236-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Lucía Cores-Sarría, Brent J. Hale, Annie Lang |
Danger, Sex, and Everything Else: A Comparison of Camera Angle and Camera Distance Effects Across Pictures of Varied Emotional Content. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Media Psychol. Theor. Methods Appl. ![In: J. Media Psychol. Theor. Methods Appl. 34(1), pp. 42-48, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes |
Short-term anchor linking and long-term self-guided attention for video object detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Image Vis. Comput. ![In: Image Vis. Comput. 110, pp. 104179, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Fernando Cores, Fernando Guirado, Josep Lluís Lérida |
High throughput BLAST algorithm using spark and cassandra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 77(2), pp. 1879-1896, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Jordi Lladós, Fernando Cores, Fernando Guirado, Josep L. Lérida |
Accurate consistency-based MSA reducing the memory footprint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Methods Programs Biomed. ![In: Comput. Methods Programs Biomed. 208, pp. 106237, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes |
Spatio-Temporal Object Detection from UAV On-Board Cameras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP (2) ![In: Computer Analysis of Images and Patterns - 19th International Conference, CAIP 2021, Virtual Event, September 28-30, 2021, Proceedings, Part II, pp. 143-152, 2021, Springer, 978-3-030-89130-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | John P. Morrissey, Prabhat Totoo, Kevin J. Hanley, Stefanos-Aldo Papanicolopulos, Jin Y. Ooi, Iván Cores Gonzalez, Bruno Raffin, Seyedmorteza Mostajabodaveh, Thomas Gierlinger |
Post-processing and visualization of large-scale DEM simulation data with the open-source VELaSSCo platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. ![In: Simul. 96(7), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes |
Spatio-temporal Tubelet Feature Aggregation and Object Linking in Videos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2004.00451, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
30 | Adrián González-Sieira, Daniel Cores, Manuel Mucientes, Alberto Bugarín |
Autonomous navigation for UAVs managing motion and sensing uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Robotics Auton. Syst. ![In: Robotics Auton. Syst. 126, pp. 103455, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Sergi Vila, Josep L. Lérida, Fernando Cores, Fernando Guirado, Fábio L. Verdi |
WPSP: A Multi-correlated Weighted Policy for VM Selection and Migration for Cloud Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2020: Parallel Processing - 26th International Conference on Parallel and Distributed Computing, Warsaw, Poland, August 24-28, 2020, Proceedings, pp. 312-326, 2020, Springer, 978-3-030-57674-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
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