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Publication years (Num. hits)
1955-1981 (15) 1982-1989 (15) 1990-1995 (24) 1996-1997 (36) 1998 (42) 1999 (55) 2000 (84) 2001 (94) 2002 (133) 2003 (176) 2004 (207) 2005 (335) 2006 (299) 2007 (398) 2008 (525) 2009 (429) 2010 (184) 2011 (101) 2012 (96) 2013 (193) 2014 (111) 2015 (205) 2016 (104) 2017 (150) 2018 (133) 2019 (159) 2020 (95) 2021 (150) 2022 (116) 2023 (138) 2024 (26)
Publication types (Num. hits)
article(1183) incollection(12) inproceedings(3579) phdthesis(45) proceedings(9)
Venues (Conferences, Journals, ...)
CORES(364) DATE(156) CoRR(139) IPDPS(99) DAC(90) FPL(80) SC(70) ITC(60) IEEE Trans. Comput. Aided Des....(55) ISCA(55) IEEE Trans. Very Large Scale I...(52) Asian Test Symposium(51) MICRO(51) VTS(49) ASP-DAC(46) ICS(42) More (+10 of total 1047)
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Found 4838 publication records. Showing 4828 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
80Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante A genetic algorithm-based system for generating test programs for microprocessor IP cores. Search on Bibsonomy ICTAI The full citation details ... 2000 DBLP  DOI  BibTeX  RDF industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
68Pierre Salverda, Craig B. Zilles Fundamental performance constraints in horizontal fusion of in-order cores. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
68Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
63Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
62Jaime H. Moreno Chip-level integration: the new frontier for microprocessor architecture. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF chip-level integration, microprocessor architecture
57Srinivasan Murali, Giovanni De Micheli Bandwidth-Constrained Mapping of Cores onto NoC Architectures. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores
57Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton Architectures and algorithms for synthesizable embedded programmable logic cores. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF programmable logic cores, FPGA, standard cells, system-on-chip design
57Peter Hallschmid, Steven J. E. Wilton Detailed routing architectures for embedded programmable logic IP cores. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF FPGA, programmable logic, detailed routing, SoC design, embedded cores
57Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor Conservation cores: reducing the energy of mature computations. Search on Bibsonomy ASPLOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF conservation core, heterogeneous many-core, utilization wall, patching
56Kuen-Jong Lee, Cheng-I Huang A hierarchical test control architecture for core based design. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
53Avi Mendelson Current trends in computer architectures: multi-cores, many-cores and special-cores. Search on Bibsonomy ICS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Nur A. Touba, Bahram Pouya Testing Embedded Cores Using Partial Isolation Rings. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
51Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid Web search using mobile cores: quantifying and mitigating the price of efficiency. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bing, mobile cores, energy efficiency, web search
51Daniel Ziener, Jürgen Teich Power Signature Watermarking of IP Cores for FPGAs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF IPP, FPGA, watermarking, signature, power analysis, IP cores
51Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas The BubbleWrap many-core: popping cores for sequential acceleration. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF power wall, process scaling, processor aging, voltage scaling
51Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian A Test Interface for Built-In Test of Non-Isolated Scanned Cores. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Juan Carlos Saez, Manuel Prieto 0001, Alexandra Fedorova, Sergey Blagodurov A comprehensive scheduler for asymmetric multicore systems. Search on Bibsonomy EuroSys The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asymmetric multicore, scheduling, operating systems
51Vahid Kazempour, Ali Kamali, Alexandra Fedorova AASH: an asymmetry-aware scheduler for hypervisors. Search on Bibsonomy VEE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF heterogeneous, scheduling algorithms, multicore processors, virtual machine monitor, hypervisor, asymmetric
51Enric Musoll Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
51Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. Search on Bibsonomy SPAA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF manycore chips, submesh allocation, algorithm, noc, temperature
51Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51Qiang Xu 0001, Nicola Nicolici Modular SOC testing with reduced wrapper count. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46A. Schubert, Walter Anheier On Random Pattern Testability of Cryptographic VLSI Cores. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing
46Tony Givargis, Frank Vahid, Jörg Henkel Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. Search on Bibsonomy ISSS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF silicon platforms, caches, low-power design, estimation, System-on-a-chip, intellectual property, cores, system parameters
46Andy Yan, Steven J. E. Wilton Product-Term-Based Synthesizable Embedded Programmable Logic Cores. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46John D. Davis, James Laudon, Kunle Olukotun Maximizing CMP Throughput with Mediocre Cores. Search on Bibsonomy IEEE PACT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Alex K. Jones, Prithviraj Banerjee An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Lukás Sekanina Towards Evolvable IP Cores for FPGAs. Search on Bibsonomy Evolvable Hardware The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin Test Scheduling of BISTed Memory Cores for SOC. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46Daniel Zappala, Aaron Fabbri An Evaluation of Shared Multicast Trees with Multiple Active Cores. Search on Bibsonomy ICN (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Hans G. Kerkhoff, Jarkko J. M. Huijts Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
45Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ia32, on-chip integration, chip multiprocessor, heterogeneous
40Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian Instruction-Based Self-Testing of Processor Cores. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
40Tony Givargis, Frank Vahid, Jörg Henkel Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF low power system design, parameterized architectures, system-on-a-chip, intellectual property, cores, system-level modeling
40Ilker Hamzaoglu, Janak H. Patel Reducing Test Application Time for Full Scan Embedded Cores. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF test generation, design-for-testability, fault simulation, embedded cores, full scan
40Kaushik De Test methodology for embedded cores which protects intellectual property. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
40Wei Zhao, Christos A. Papachristou Synthesis of reusable DSP cores based on multiple behaviors. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips
40Tameesh Suri, Aneesh Aggarwal Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
40Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
40David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil Dependability Assessment for the Selection of Embedded Cores. Search on Bibsonomy EDCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
40David Tarjan, Michael Boyer, Kevin Skadron Federation: repurposing scalar cores for out-of-order instruction issue. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CMP, multicore, federation, out-of-order
40Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty Test infrastructure design for mixed-signal SOCs with wrapped analog cores. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Simin Dai, Elaheh Bozorgzadeh CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. Search on Bibsonomy FCCM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Mario Donato Marino 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. Search on Bibsonomy SBAC-PAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Anuja Sehgal, Fang Liu 0029, Sule Ozev, Krishnendu Chakrabarty Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri Optimal Spare Utilization in Repairable and Reliable Memory Cores. Search on Bibsonomy MTDT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
40Magnus Ekman, Per Stenström Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. Search on Bibsonomy ICPP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Anoop Iyer, Diana Marculescu Power efficiency of voltage scaling in multiple clock, multiple voltage cores. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Philip James-Roxby, Steven A. Guccione Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations. Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003 EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. Search on Bibsonomy PLDI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF GPU, openMP, heterogeneous multi-cores
39Pierre Michaud, Yiannakis Sazeides, André Seznec Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF activity migration, sequential performance, power, multicore, temperature, cache misses, manycore
39Mario Donato Marino L2-Cache Hierarchical Organizations for Multi-core Architectures. Search on Bibsonomy ISPA Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec Performance implications of single thread migration on a chip multi-core. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Francesco Menichelli, Mauro Olivieri, Simone Smorfa Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
35Swann Perarnau, Guillaume Huard KRASH: reproducible CPU load generation on many cores machines. Search on Bibsonomy PPoPP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF cpu load generation, many cores, experimentation testbed
35Roman L. Lysecky, Frank Vahid Prefetching for improved bus wrapper performance in cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus
35T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua Compiler-directed customization of ASIP cores. Search on Bibsonomy CODES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF soft cores, embedded, customization, ASIP
35Yulu Ma, Shiduan Cheng Multi-Cores Uni-Directional Shared Trees Multicast Routing Protocol. Search on Bibsonomy LCN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF multi-cores uni-directional shared trees, CBT, PIM-SM, intradomain multicast routing protocols, efficient member management mechanism, authentication, protocols, admission control, trees (mathematics), telecommunication network routing, multicast communication, multicast group, packet transmission
35Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas Verification of configurable processor cores. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis
35Omer Khan, Sandip Kundu A self-adaptive scheduler for asymmetric multi-cores. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF scheduling, modeling, power
35Tameesh Suri, Aneesh Aggarwal Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF data value prediction, dynamic reconfiguration, loop level parallelism
35Takanori Ueda, Yu Hirate, Hayato Yamana Exploiting idle CPU cores to improve file access performance. Search on Bibsonomy ICUIMC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF access pattern mining, many core, access pattern, replacement algorithm, buffer caching
35Albert Meixner, Daniel J. Sorin Detouring: Translating software to circumvent hard faults in simple cores. Search on Bibsonomy DSN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Qiang Xu 0001, Nicola Nicolici, Krishnendu Chakrabarty Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Xiaoding Chen, Michael S. Hsiao Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF built-in-self-test, System-on-a-chip, spectral analysis
35Daniel Ziener, Stefan Assmus, Jürgen Teich Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Umar Farooq 0009, Muhammad Saleem, Habibullah Jamal Parameterized FIR Filtering IP Cores for Reusable SoC Design. Search on Bibsonomy ITNG The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Finite Impulse Response (FIR) filter, Unfolded Direct Form (UDF), Folded Direct Form (FDF), Parameterized, SoC design, IP Core, Synthesis tools
35Haihua Shen, Yunji Chen, Jing Huang EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores. Search on Bibsonomy ICESS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Huaguo Liang, Cuiyun Jiang Sharing BIST with Multiple Cores for System-on-a-Chip. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian Effective Software Self-Test Methodology for Processor Cores. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35K. Y. Ko, Mike W. T. Wong, Yim-Shu Lee Testing System-On-Chip by Summations of Cores? Test Output Voltages. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35Satnam Singh, Carl Johan Lillieroth Formal Verification of Reconfigurable Cores. Search on Bibsonomy FCCM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
35Janusz Rajski, Jerzy Tyszer Modular logic built-in self-test for IP cores. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh Parallelism via Multithreaded and Multicore CPUs. Search on Bibsonomy Computer The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Multithreaded cores, Heterogeneous cores, Application-level parallelism, Chip interconnects, GPUs, Multicore processors, Power efficiency
34Roman L. Lysecky, Frank Vahid Design and implementation of a MicroBlaze-based warp processor. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
34Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger Multitasking workload scheduling on flexible-core chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF flexible cores, multitask scheduling, multicore architectures
34Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian On IEEE P1500's Standard for Embedded Core Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF core test wrapper, core test language, compliance levels, standardization, embedded cores
34Roman L. Lysecky, Frank Vahid, Tony Givargis Techniques for Reducing Read Latency of Core Bus Wrappers. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
34Major Bhadauria, Vincent M. Weaver, Sally A. McKee Accomodating Diversity in CMPs with Heterogeneous Frequencies. Search on Bibsonomy HiPEAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti A compiler-directed data prefetching scheme for chip multiprocessors. Search on Bibsonomy PPoPP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF compiler, chip multiprocessors, prefetching, helper thread
34Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal Multi-core architectures and streaming applications. Search on Bibsonomy SLIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF NoC design, multi-core SoC design, system design, streaming applications
34Mijeom Kim, Mohan Kumar, Behrooz A. Shirazi An Integrated Scheme for Address Assignment and Service Location in Pervasive Environments. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Indradeep Ghosh, Niraj K. Jha, Sujit Dey A low overhead design for testability and test generation technique for core-based systems-on-a-chip. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
30Brais Bosquet, Daniel Cores, Lorenzo Seidenari, Víctor M. Brea 0001, Manuel Mucientes, Alberto Del Bimbo A full data augmentation pipeline for small object detection based on generative adversarial networks. Search on Bibsonomy Pattern Recognit. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes Spatiotemporal tubelet feature aggregation and object linking for small object detection in videos. Search on Bibsonomy Appl. Intell. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Nicolás Vila Blanco, Manuel Mucientes, María J. Carreira Few-Shot Image Classification for Automatic COVID-19 Diagnosis. Search on Bibsonomy IbPRIA The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Lorenzo Seidenari, Alberto Del Bimbo, Víctor M. Brea 0001, Manuel Mucientes Relation Networks for Few-Shot Video Object Detection. Search on Bibsonomy IbPRIA The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes, Lorenzo Seidenari, Alberto Del Bimbo Downsampling GAN for Small Object Data Augmentation. Search on Bibsonomy CAIP (1) The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Lucía Cores-Sarría, Brent J. Hale, Annie Lang Danger, Sex, and Everything Else: A Comparison of Camera Angle and Camera Distance Effects Across Pictures of Varied Emotional Content. Search on Bibsonomy J. Media Psychol. Theor. Methods Appl. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes Short-term anchor linking and long-term self-guided attention for video object detection. Search on Bibsonomy Image Vis. Comput. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
30Fernando Cores, Fernando Guirado, Josep Lluís Lérida High throughput BLAST algorithm using spark and cassandra. Search on Bibsonomy J. Supercomput. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
30Jordi Lladós, Fernando Cores, Fernando Guirado, Josep L. Lérida Accurate consistency-based MSA reducing the memory footprint. Search on Bibsonomy Comput. Methods Programs Biomed. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes Spatio-Temporal Object Detection from UAV On-Board Cameras. Search on Bibsonomy CAIP (2) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
30John P. Morrissey, Prabhat Totoo, Kevin J. Hanley, Stefanos-Aldo Papanicolopulos, Jin Y. Ooi, Iván Cores Gonzalez, Bruno Raffin, Seyedmorteza Mostajabodaveh, Thomas Gierlinger Post-processing and visualization of large-scale DEM simulation data with the open-source VELaSSCo platform. Search on Bibsonomy Simul. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
30Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes Spatio-temporal Tubelet Feature Aggregation and Object Linking in Videos. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
30Adrián González-Sieira, Daniel Cores, Manuel Mucientes, Alberto Bugarín Autonomous navigation for UAVs managing motion and sensing uncertainty. Search on Bibsonomy Robotics Auton. Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
30Sergi Vila, Josep L. Lérida, Fernando Cores, Fernando Guirado, Fábio L. Verdi WPSP: A Multi-correlated Weighted Policy for VM Selection and Migration for Cloud Computing. Search on Bibsonomy Euro-Par The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
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