Search results for "dual-port"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Christian Mandl, Adolfo Fucci	A fast FPGA based coprocessor supporting hard real-time search.	EUROMICRO	1997	DBLP DOI BibTeX RDF	fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs
74	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
68	Said Hamdioui, Ad J. van de Goor	Efficient Tests for Realistic Faults in Dual-Port SRAMs.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Multiport/single-port memories, weak faults, fault models, fault coverage, march tests
68	Steven J. E. Wilton	Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays.	FPGA	2000	DBLP DOI BibTeX RDF
64	Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang	The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection.	CCTA	2007	DBLP DOI BibTeX RDF	dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication
57	Hong-Hee Lee, Hoang M. Nguyen	Implementation of Induction Motor Control System Using Matrix Converter Based on CAN Network and Dual-Port RAM.	ICIC (2)	2009	DBLP DOI BibTeX RDF	CAN network, dual-port RAM, Matrix converter
57	Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha	Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.	CASES	2007	DBLP DOI BibTeX RDF	dual-port SDRAM, mobile embedded system, memory architecture
56	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Testing SRAM-Based Content Addressable Memories.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory
50	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
43	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
37	Fabio Ancona, Stefano Rovetta, Rodolfo Zunino	High performance in tree-based parallel architectures.	EUROMICRO	1997	DBLP DOI BibTeX RDF	tree-based parallel architectures, integrated schema, complex node, dual-port memory, bidirectional high-speed communication link, tree-structured processor hierarchies, memory speed, experimental development, associative models, performance evaluation, optimality, connectivity, high performance, transputers
37	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
31	Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb	New fault models and efficient BIST algorithms for dual-port memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
30	Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala	Parallel Memory Architecture for TTA Processor.	SAMOS	2007	DBLP DOI BibTeX RDF
27	Honglan Zhan, Chenxi Wang, Hongwei Cui, Xianhua Liu 0001, Feng Liu, Xu Cheng 0001	High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation.	DATE	2023	DBLP DOI BibTeX RDF
27	Nikesh Kumar Sahu, Ravi Kumar Gangwar	Dual-Port Compact MIMO-DRAs: Exploiting Metallic Sheets to Increase Inter-Port Isolation at 28-GHz 5G-Band.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
27	M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar 0002	A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance.	VLSID	2018	DBLP DOI BibTeX RDF
27	Harsh Rawat, K. Bharath, Alexander Fell	Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.	SoCC	2017	DBLP DOI BibTeX RDF
27	Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii	13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.	ISSCC	2014	DBLP DOI BibTeX RDF
27	Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii	40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.	A-SSCC	2014	DBLP DOI BibTeX RDF
27	Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto	A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
27	Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara	Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.	CICC	2011	DBLP DOI BibTeX RDF
27	Ho-Yong Choi, Kewal K. Saluja	Detection of inter-port bridging faults in dual-port memories.	ISCAS	2010	DBLP DOI BibTeX RDF
27	Yijun Gu, Zuo Wang	Mapping N-Port Memory with Dual-Port Array.	CSIE (3)	2009	DBLP DOI BibTeX RDF
26	Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon, Eui-Young Chung	Architecture Exploration of High-Performance PCs with a Solid-State Disk.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	dual-port DRAM, North Bridge, direct path, NAND flash memory, Solid-State Disk (SSD)
26	Adam Sampson, Zhizhang Chen	Wireless Video Graphics Array System Design.	CNSR	2005	DBLP DOI BibTeX RDF	Wireless computer video, dual-port ram, Wireless Video Graphics Array, compression, OFDM, decompression
26	Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams	Defect Analysis and a New Fault Model for Multi-port SRAMs.	DFT	2001	DBLP DOI BibTeX RDF	dual-port, SDDRF, electrical fault model, SRAM, defect analysis, multi-port
24	Ke Xu 0014, Chiu-sing Choy	A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
24	Abhinav Vishnu, Brad Benton, Dhabaleswar K. Panda 0001	High Performance MPI on IBM 12x InfiniBand Architecture.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Kimish Patel, Enrico Macii, Massimo Poncino	Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.	DATE	2004	DBLP DOI BibTeX RDF
24	Mohd. Hasan, Tughrul Arslan	A triple port RAM based low power commutator architecture for a pipelined FFT processor.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Tan Soon-Hwei, Loh Poh-Yee, Mohd-Shahiman Sulaiman	A Low-Power High-Speed 1-Mb CMOS SRAM.	DELTA	2006	DBLP DOI BibTeX RDF
21	Wei Qin, Hai-Ling Zhang, Yu-Ke Zhou, Wenwen Yang 0001, Jian-Xin Chen	Bandpass Filters Based on Dual-Disparate-Mode Dielectric Waveguide Resonators With Dual Port-Excitations.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
21	Mahmoud Wagih, Alex S. Weddell, Steve P. Beeby	Battery-Free Wireless Light-Sensing Tag Based on a Long-Range Dual-Port Dual-Polarized RFID Platform.	Sensors	2022	DBLP DOI BibTeX RDF
21	Min Wang 0008, Dao-Yu Wang, Wen Wu 0005, Da-Gang Fang	Single-Layer, Dual-Port, Dual-Band, and Orthogonal-Circularly Polarized Microstrip Antenna Array with Low Frequency Ratio.	Wirel. Commun. Mob. Comput.	2018	DBLP DOI BibTeX RDF
21	Chaoyi Wang, Peng Liu, Peng Wang, Yalong Zhang, Peng Gao	Design of Dual-Band Dual-Port MIMO Antenna for LTE and WIMAX Applications.	ISCID (1)	2018	DBLP DOI BibTeX RDF
21	Asim Quddus, Rashid Saleem 0001, Sabih ur Rehman, Muhammad Farhan Shafique	Dual port UWB diversity/MIMO antenna with dual band-notch characteristics.	ICSPCS	2016	DBLP DOI BibTeX RDF
21	Nan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu	Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation.	SoCC	2013	DBLP DOI BibTeX RDF
21	Peter Geens, Wim Dehaene	A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage.	ESSCIRC	2008	DBLP DOI BibTeX RDF
17	Mayank Tiwari 0002, Yuming Zhu, Chaitali Chakrabarti	Memory sub-banking scheme for high throughput MAP-based SISO decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
17	R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004	A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.	ISQED	2005	DBLP DOI BibTeX RDF
17	F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh 0004	Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.	ISQED	2003	DBLP DOI BibTeX RDF
17	Yong Liu 0023, Zhiqiang Gao, Xiangqing He	A Flexible Embedded SRAM Compiler.	DELTA	2002	DBLP DOI BibTeX RDF
17	Jacobo Riesco, Juan Carlos Diaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez Martínez	On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC.	ED&TC	1997	DBLP DOI BibTeX RDF
16	Shahanawaz Kamal, Padmanava Sen	Microstrip-Ministered Proximity-Coupled Stacked Dual-Port Antenna for 6G Applications.	IEEE Access	2024	DBLP DOI BibTeX RDF
16	Chaofan Ren, Junping Geng, Han Zhou, Kun Wang, Jingzheng Lu, Da Su, Yangzhou Zhang, Silei Yang, Chong He, Xianling Liang, Ronghong Jin	Study on the Wide-Angle Scanning Utilizing Dual-Port Phased Monopole Antenna With Corrugated Structure.	IEEE Trans. Veh. Technol.	2023	DBLP DOI BibTeX RDF
16	Zirun Li, Jin Xu, Pan Wu, Guojie Li, Keyou Wang, Yiming Yang, Jie Du	Unified Real-Time Simulation Method for DC/DC Conversion Systems Consisting of Cascaded Dual-Port Submodules.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
16	Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi	Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
16	Kai Li, Bingyi Zhang, Guihong Feng, Kai Liu	No-Load Characteristic Analysis of Single/Three-Phase Dual-Port Permanent Magnet Synchronous Generator With Eccentric Magnetic Metal Block Based on Nonlinear Magnetic Field Analytical Method.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch	Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
16	Feng Wei 0003, Yu-Chen Xue, Xi-Bei Zhao, Wei-Shen Liu, Le Xu, Peng-Fei Zhang	Balanced BPF With Dual-Port Quasi-Reflectionless Characteristic and Selectivity Enhancement.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Rania H. El-abd	Compact dual-port MIMO filtenna-based DMS with high isolation for C-band and X-band applications.	EURASIP J. Wirel. Commun. Netw.	2023	DBLP DOI BibTeX RDF
16	Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed 0011, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni 0004	Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.	CoRR	2023	DBLP DOI BibTeX RDF
16	Irina Subotic, Dominic Groß	Universal dual-port grid-forming control: bridging the gap between grid-forming and grid-following control.	CoRR	2023	DBLP DOI BibTeX RDF
16	Kosuke Mori, Fumio Teraoka, Shinichiro Haruyama	A Fast Handover Mechanism for Ground-to-Train Free-Space Optical Communication using Station ID Recognition by Dual-Port Camera.	IEICE Trans. Inf. Syst.	2023	DBLP DOI BibTeX RDF
16	Om Prakash 0007, Kai Ni 0004, Hussam Amrouch	Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness.	IRPS	2023	DBLP DOI BibTeX RDF
16	Rahul Gulve, Roberto Rangel, Ayandev Barman, Don Nguyen, Mian Wei, Motasem Sakr, Xiaonong Sun, David B. Lindell, Kiriakos N. Kutulakos, Roman Genov	Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns Rapid-Update Pixel-Wise Exposure Coding.	ISSCC	2023	DBLP DOI BibTeX RDF
16	Kai Ni	Multi-Functionalities and Applications of Dual-Port Ferroelectric FET.	ICICDT	2023	DBLP DOI BibTeX RDF
16	Ajay Kumar Dwivedi, Nagesh Kallollu Narayaswamy, H. Venkatesh Kumar, Suyash Kumar Singh, Jitendranath Mungara, Anand Sharma, Vivek Singh	Two asymmetric cylindrical dielectric resonator loaded dual port multiple-input multiple-output antenna for wide band application with circular polarization attributes.	Int. J. Commun. Syst.	2022	DBLP DOI BibTeX RDF
16	Longyue Qu, Haiyan Piao	A Dual-Port Single-Dipole MIMO Antenna Pair Based on Selective Modal Excitation for 5G Metal-Rimmed Terminals.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Nima Tashakor, Jan Kacetl, Jinyang Fang, Z. Li, Stefan M. Goetz	Dual-Port Dynamically Reconfigurable Battery with Semi-Controlled and Fully-Controlled Outputs.	CoRR	2022	DBLP DOI BibTeX RDF
16	Reza E. Rad, Kyung-Duk Choi, Sung-Jin Kim, YoungGun Pu, Yeon-Jae Jung, Hyung-Ki Huh, Joon-Mo Yoo, Seok-Kee Kim, Kang-Yoon Lee	A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode.	Sensors	2022	DBLP DOI BibTeX RDF
16	Irina Subotic, Dominic Groß	Power-Balancing Dual-Port Grid-Forming Power Converter Control for Renewable Integration and Hybrid AC/DC Power Systems.	IEEE Trans. Control. Netw. Syst.	2022	DBLP DOI BibTeX RDF
16	Wan Jiang, Yong Mao Huang, Christian Waldschmidt, Biao Zhang	Dual-port traveling-wave frequency-scanned patch array antenna for E-band vehicle sensing and imaging applications.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
16	Chi Chen, Kuan Hu, Weilin Luo, Kang Yin, Ruiyuan Kang, Ying Zhao, Fei Yang	A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites.	ICTA	2022	DBLP DOI BibTeX RDF
16	Valentina Palazzi, Leonardo Balocchi, Stefania Bonafoni, Luca Roselli	Slot-fed Dual-Port Patch Antenna for Compact Harmonic Transponders.	RFID-TA	2022	DBLP DOI BibTeX RDF
16	Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu	Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
16	Ali Bakbak, Mert Altintas, Murat Ayaz, Hüseyin Tayyer Canseven, Mutlu Boztepe, Ozkan Akin, Erkan Mese	PMSG-Based Dual-Port Wind-Energy Conversion System With Reduced Converter Size.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Muhammad Usman 0017, Enis Kobal, Jamal Nasir, Yuanwei Zhu, Chao Yu 0002, Anding Zhu	Compact SIW Fed Dual-Port Single Element Annular Slot MIMO Antenna for 5G mmWave Applications.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Dominic Groß, Enric Sánchez-Sánchez, Eduardo Prieto-Araujo, Oriol Gomis-Bellmunt	Dual-port grid-forming control of MMCs and its applications to grids of grids.	CoRR	2021	DBLP BibTeX RDF
16	Dai Li, Kaiyuan Yang 0001	A Dual-Port 8-T CAM-Based Network Intrusion Detection Engine for IoT.	CoRR	2021	DBLP BibTeX RDF
16	Deshun Li, Heng Qi, Yanming Shen, Keqiu Li	DPCell: Constructing Novel Architectures of Data Center Networks on Dual-Port Servers.	IEEE Netw.	2021	DBLP DOI BibTeX RDF
16	Masoud Nouripayam, Joachim Rodrigues, Xiao Luo, Tom Johansson, Babak Mohammadi	A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI.	ESSCIRC	2021	DBLP DOI BibTeX RDF
16	Hooman Saeidi, Suresh Venkatesh, Xuyang Lu, Kaushik Sengupta	22.1 THz Prism: One-Shot Simultaneous Multi-Node Angular Localization Using Spectrum-to-Space Mapping with 360-to-400GHz Broadband Transceiver and Dual-Port Integrated Leaky-Wave Antennas.	ISSCC	2021	DBLP DOI BibTeX RDF
16	Suresh Babu Kotha, Kumar Rahul, Mohammad Anees, Santosh Yachareni, Subodh Kumar	High speed low power SEU tolerant Pseudo dual port memory in 7nm.	ISNCC	2021	DBLP DOI BibTeX RDF
16	Omar Farrok, Md. Rabiul Islam 0001, Kashem M. Muttaqi, Danny Sutanto, Jianguo Zhu 0001	Design and Optimization of a Novel Dual-Port Linear Generator for Oceanic Wave Energy Conversion.	IEEE Trans. Ind. Electron.	2020	DBLP DOI BibTeX RDF
16	Moeen Al-Makhlafi, Huaxi Gu, Xiaoshan Yu, Yunfeng Lu	P-Cube: A New Two-Layer Topology for Data Center Networks Exploiting Dual-Port Servers.	IEICE Trans. Commun.	2020	DBLP DOI BibTeX RDF
16	Alejandro Erickson, Javier Navaridas, Iain A. Stewart	Relating the bisection width of dual-port, server-centric datacenter networks and the solution of edge isoperimetric problems in graphs.	J. Comput. Syst. Sci.	2020	DBLP DOI BibTeX RDF
16	Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu	Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
16	Wonwoo Lee, Beakcheol Jang	A Tunable MIMO Antenna With Dual-Port Structure for Mobile Phones.	IEEE Access	2019	DBLP DOI BibTeX RDF
16	Kunal Das, Arindam Sadhu, Debashis De, Jadav Chandra Das	Design and simulation of priority based dual port memory in quantum dot cellular automata.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
16	Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
16	Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang	A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.	ISSCC	2019	DBLP DOI BibTeX RDF
16	Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana	Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory.	IEEE Trans. Emerg. Top. Comput.	2018	DBLP DOI BibTeX RDF
16	Hyungkyu Yang, Wonwoo Lee, Byung-Ho Rhee	A High-Isolation MIMO Antenna with Dual-Port Structure for 5G Mobile Phones.	KSII Trans. Internet Inf. Syst.	2018	DBLP DOI BibTeX RDF
16	Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning.	ICECS	2018	DBLP DOI BibTeX RDF
16	Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka	12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
16	Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang	28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
16	Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara	A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
16	Bo Wang 0020, Jun Zhou 0017, Tony Tae-Hyoung Kim	A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
16	Alejandro Erickson, Iain A. Stewart, Jose Antonio Pascual, Javier Navaridas	Improved routing algorithms in the dual-port datacenter networks HCN and BCN.	Future Gener. Comput. Syst.	2017	DBLP DOI BibTeX RDF
16	Chao Qun Liu, Yue Zheng, Chip-Hong Chang	A new write-contention based dual-port SRAM PUF with multiple response bits per cell.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade	An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors.	SoCC	2017	DBLP DOI BibTeX RDF
16	Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii	A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.	A-SSCC	2017	DBLP DOI BibTeX RDF
16	Yeongkyo Seo, Kon-Woo Kwon, Xuanyao Fong, Kaushik Roy 0001	High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Qingzhong Jia, Xingdou Wang	Research on communication technology of complex system based on FPGA dual-port RAMs.	ICAC	2016	DBLP DOI BibTeX RDF
16	Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.	ICECS	2016	DBLP DOI BibTeX RDF
16	Ameer M. S. Abdelhadi, Guy G. F. Lemieux	A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs.	FCCM	2016	DBLP DOI BibTeX RDF
16	Mahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David T. Blaauw, Dennis Sylvester	17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.	ISSCC	2016	DBLP DOI BibTeX RDF
16	Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang	A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.	VLSI Circuits	2016	DBLP DOI BibTeX RDF