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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 170 publication records. Showing 170 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Christian Mandl, Adolfo Fucci |
A fast FPGA based coprocessor supporting hard real-time search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 499-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs |
74 | Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu |
N-port memory mapping for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 279, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logical-to-physical mapping, n-port memory, fpga, hierarchy |
68 | Said Hamdioui, Ad J. van de Goor |
Efficient Tests for Realistic Faults in Dual-Port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 460-473, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multiport/single-port memories, weak faults, fault models, fault coverage, march tests |
68 | Steven J. E. Wilton |
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 67-74, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
64 | Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang |
The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA ![In: Computer And Computing Technologies In Agriculture, Volume I, First IFIP TC 12 International Conference on Computer and Computing Technologies in Agriculture (CCTA 2007), Wuyishan, China, August 18-20, 2007, pp. 433-440, 2007, Springer, 978-0-387-77250-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication |
57 | Hong-Hee Lee, Hoang M. Nguyen |
Implementation of Induction Motor Control System Using Matrix Converter Based on CAN Network and Dual-Port RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (2) ![In: Emerging Intelligent Computing Technology and Applications. With Aspects of Artificial Intelligence, 5th International Conference on Intelligent Computing, ICIC 2009, Ulsan, South Korea, September 16-19, 2009, Proceedings, pp. 1067-1074, 2009, Springer, 978-3-642-04019-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CAN network, dual-port RAM, Matrix converter |
57 | Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha |
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 53-57, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-port SDRAM, mobile embedded system, memory architecture |
56 | Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
Testing SRAM-Based Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1054-1063, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory |
50 | Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar |
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 165-179, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multi-port SRAMs, Defect/fault tolerant design, Defect analysis |
43 | Puneet Sawhney, Haroon Rasheed |
Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 191-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators |
37 | Fabio Ancona, Stefano Rovetta, Rodolfo Zunino |
High performance in tree-based parallel architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 474-481, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
tree-based parallel architectures, integrated schema, complex node, dual-port memory, bidirectional high-speed communication link, tree-structured processor hierarchies, memory speed, experimental development, associative models, performance evaluation, optimality, connectivity, high performance, transputers |
37 | Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya |
A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 545-553, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb |
New fault models and efficient BIST algorithms for dual-port memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9), pp. 987-1000, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala |
Parallel Memory Architecture for TTA Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 273-282, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Honglan Zhan, Chenxi Wang, Hongwei Cui, Xianhua Liu 0001, Feng Liu, Xu Cheng 0001 |
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Nikesh Kumar Sahu, Ravi Kumar Gangwar |
Dual-Port Compact MIMO-DRAs: Exploiting Metallic Sheets to Increase Inter-Port Isolation at 28-GHz 5G-Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(12), pp. 4814-4818, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar 0002 |
A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pp. 266-270, 2018, IEEE Computer Society, 978-1-5386-3692-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Harsh Rawat, K. Bharath, Alexander Fell |
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-4034-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
27 | Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii |
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 234-235, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
27 | Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii |
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014, pp. 25-28, 2014, IEEE, 978-1-4799-4090-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
27 | Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto |
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, pp. 246-251, 2012, IEEE Computer Society, 978-1-4673-4555-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
27 | Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara |
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0222-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Ho-Yong Choi, Kewal K. Saluja |
Detection of inter-port bridging faults in dual-port memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 657-660, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Yijun Gu, Zuo Wang |
Mapping N-Port Memory with Dual-Port Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIE (3) ![In: CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes, pp. 444-447, 2009, IEEE Computer Society, 978-0-7695-3507-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon, Eui-Young Chung |
Architecture Exploration of High-Performance PCs with a Solid-State Disk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(7), pp. 878-890, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dual-port DRAM, North Bridge, direct path, NAND flash memory, Solid-State Disk (SSD) |
26 | Adam Sampson, Zhizhang Chen |
Wireless Video Graphics Array System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CNSR ![In: Third Annual Conference on Communication Networks and Services Research (CNSR 2005), 16-18 May 2005, Halifax, Novia Scotia, Canada, pp. 163-166, 2005, IEEE Computer Society, 0-7695-2333-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Wireless computer video, dual-port ram, Wireless Video Graphics Array, compression, OFDM, decompression |
26 | Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams |
Defect Analysis and a New Fault Model for Multi-port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 366-374, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
dual-port, SDDRF, electrical fault model, SRAM, defect analysis, multi-port |
24 | Ke Xu 0014, Chiu-sing Choy |
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(3), pp. 363-374, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Abhinav Vishnu, Brad Benton, Dhabaleswar K. Panda 0001 |
High Performance MPI on IBM 12x InfiniBand Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kimish Patel, Enrico Macii, Massimo Poncino |
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 700-701, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Mohd. Hasan, Tughrul Arslan |
A triple port RAM based low power commutator architecture for a pipelined FFT processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 353-356, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Tan Soon-Hwei, Loh Poh-Yee, Mohd-Shahiman Sulaiman |
A Low-Power High-Speed 1-Mb CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 281-288, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Wei Qin, Hai-Ling Zhang, Yu-Ke Zhou, Wenwen Yang 0001, Jian-Xin Chen |
Bandpass Filters Based on Dual-Disparate-Mode Dielectric Waveguide Resonators With Dual Port-Excitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(9), pp. 3303-3307, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Mahmoud Wagih, Alex S. Weddell, Steve P. Beeby |
Battery-Free Wireless Light-Sensing Tag Based on a Long-Range Dual-Port Dual-Polarized RFID Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(13), pp. 4782, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Min Wang 0008, Dao-Yu Wang, Wen Wu 0005, Da-Gang Fang |
Single-Layer, Dual-Port, Dual-Band, and Orthogonal-Circularly Polarized Microstrip Antenna Array with Low Frequency Ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Commun. Mob. Comput. ![In: Wirel. Commun. Mob. Comput. 2018, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Chaoyi Wang, Peng Liu, Peng Wang, Yalong Zhang, Peng Gao |
Design of Dual-Band Dual-Port MIMO Antenna for LTE and WIMAX Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCID (1) ![In: 11th International Symposium on Computational Intelligence and Design, ISCID 2018, Hangzhou, China, December 8-9, 2018, Volume 1, pp. 21-24, 2018, IEEE, 978-1-5386-8527-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Asim Quddus, Rashid Saleem 0001, Sabih ur Rehman, Muhammad Farhan Shafique |
Dual port UWB diversity/MIMO antenna with dual band-notch characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSPCS ![In: 10th International Conference on Signal Processing and Communication Systems, ICSPCS 2016, Surfers Paradise, Gold Coast, Australia, December 19-21, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0941-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Nan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu |
Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 105-109, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Peter Geens, Wim Dehaene |
A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008., pp. 290-293, 2008, IEEE, 978-1-4244-2361-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Mayank Tiwari 0002, Yuming Zhu, Chaitali Chakrabarti |
Memory sub-banking scheme for high throughput MAP-based SISO decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(4), pp. 494-498, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004 |
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 193-196, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh 0004 |
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 119-124, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Yong Liu 0023, Zhiqiang Gao, Xiangqing He |
A Flexible Embedded SRAM Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 474-476, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Jacobo Riesco, Juan Carlos Diaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez Martínez |
On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 218-222, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Shahanawaz Kamal, Padmanava Sen |
Microstrip-Ministered Proximity-Coupled Stacked Dual-Port Antenna for 6G Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 2817-2829, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Chaofan Ren, Junping Geng, Han Zhou, Kun Wang, Jingzheng Lu, Da Su, Yangzhou Zhang, Silei Yang, Chong He, Xianling Liang, Ronghong Jin |
Study on the Wide-Angle Scanning Utilizing Dual-Port Phased Monopole Antenna With Corrugated Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 72(12), pp. 15463-15476, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Zirun Li, Jin Xu, Pan Wu, Guojie Li, Keyou Wang, Yiming Yang, Jie Du |
Unified Real-Time Simulation Method for DC/DC Conversion Systems Consisting of Cascaded Dual-Port Submodules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 70(11), pp. 11368-11378, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi |
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(7), pp. 2098-2108, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kai Li, Bingyi Zhang, Guihong Feng, Kai Liu |
No-Load Characteristic Analysis of Single/Three-Phase Dual-Port Permanent Magnet Synchronous Generator With Eccentric Magnetic Metal Block Based on Nonlinear Magnetic Field Analytical Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 132955-132965, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch |
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(7), pp. 2891-2903, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Feng Wei 0003, Yu-Chen Xue, Xi-Bei Zhao, Wei-Shen Liu, Le Xu, Peng-Fei Zhang |
Balanced BPF With Dual-Port Quasi-Reflectionless Characteristic and Selectivity Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(3), pp. 994-998, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Rania H. El-abd |
Compact dual-port MIMO filtenna-based DMS with high isolation for C-band and X-band applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Wirel. Commun. Netw. ![In: EURASIP J. Wirel. Commun. Netw. 2023(1), pp. 110, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed 0011, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni 0004 |
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.01484, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Irina Subotic, Dominic Groß |
Universal dual-port grid-forming control: bridging the gap between grid-forming and grid-following control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.04939, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kosuke Mori, Fumio Teraoka, Shinichiro Haruyama |
A Fast Handover Mechanism for Ground-to-Train Free-Space Optical Communication using Station ID Recognition by Dual-Port Camera. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 106(5), pp. 940-951, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Om Prakash 0007, Kai Ni 0004, Hussam Amrouch |
Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Gulve, Roberto Rangel, Ayandev Barman, Don Nguyen, Mian Wei, Motasem Sakr, Xiaonong Sun, David B. Lindell, Kiriakos N. Kutulakos, Roman Genov |
Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns Rapid-Update Pixel-Wise Exposure Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 104-105, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kai Ni |
Multi-Functionalities and Applications of Dual-Port Ferroelectric FET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023, pp. xxx, 2023, IEEE, 979-8-3503-1931-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Ajay Kumar Dwivedi, Nagesh Kallollu Narayaswamy, H. Venkatesh Kumar, Suyash Kumar Singh, Jitendranath Mungara, Anand Sharma, Vivek Singh |
Two asymmetric cylindrical dielectric resonator loaded dual port multiple-input multiple-output antenna for wide band application with circular polarization attributes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Syst. ![In: Int. J. Commun. Syst. 35(10), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Longyue Qu, Haiyan Piao |
A Dual-Port Single-Dipole MIMO Antenna Pair Based on Selective Modal Excitation for 5G Metal-Rimmed Terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 100208-100214, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Nima Tashakor, Jan Kacetl, Jinyang Fang, Z. Li, Stefan M. Goetz |
Dual-Port Dynamically Reconfigurable Battery with Semi-Controlled and Fully-Controlled Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.01435, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Reza E. Rad, Kyung-Duk Choi, Sung-Jin Kim, YoungGun Pu, Yeon-Jae Jung, Hyung-Ki Huh, Joon-Mo Yoo, Seok-Kee Kim, Kang-Yoon Lee |
A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(6), pp. 2276, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Irina Subotic, Dominic Groß |
Power-Balancing Dual-Port Grid-Forming Power Converter Control for Renewable Integration and Hybrid AC/DC Power Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Control. Netw. Syst. ![In: IEEE Trans. Control. Netw. Syst. 9(4), pp. 1949-1961, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Wan Jiang, Yong Mao Huang, Christian Waldschmidt, Biao Zhang |
Dual-port traveling-wave frequency-scanned patch array antenna for E-band vehicle sensing and imaging applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(3), pp. 20210367, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Chi Chen, Kuan Hu, Weilin Luo, Kang Yin, Ruiyuan Kang, Ying Zhao, Fei Yang |
A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 100-101, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Valentina Palazzi, Leonardo Balocchi, Stefania Bonafoni, Luca Roselli |
Slot-fed Dual-Port Patch Antenna for Compact Harmonic Transponders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFID-TA ![In: 12th IEEE International Conference on RFID Technology and Applications, RFID-TA 2022, Cagliari, Italy, September 12-14, 2022, pp. 86-89, 2022, IEEE, 978-1-6654-6594-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu |
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(4), pp. 1116-1128, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Ali Bakbak, Mert Altintas, Murat Ayaz, Hüseyin Tayyer Canseven, Mutlu Boztepe, Ozkan Akin, Erkan Mese |
PMSG-Based Dual-Port Wind-Energy Conversion System With Reduced Converter Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 118953-118967, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Usman 0017, Enis Kobal, Jamal Nasir, Yuanwei Zhu, Chao Yu 0002, Anding Zhu |
Compact SIW Fed Dual-Port Single Element Annular Slot MIMO Antenna for 5G mmWave Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 91995-92002, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Dominic Groß, Enric Sánchez-Sánchez, Eduardo Prieto-Araujo, Oriol Gomis-Bellmunt |
Dual-port grid-forming control of MMCs and its applications to grids of grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.11378, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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16 | Dai Li, Kaiyuan Yang 0001 |
A Dual-Port 8-T CAM-Based Network Intrusion Detection Engine for IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.02992, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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16 | Deshun Li, Heng Qi, Yanming Shen, Keqiu Li |
DPCell: Constructing Novel Architectures of Data Center Networks on Dual-Port Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Netw. ![In: IEEE Netw. 35(4), pp. 206-212, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Masoud Nouripayam, Joachim Rodrigues, Xiao Luo, Tom Johansson, Babak Mohammadi |
A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 47th ESSCIRC 2021 - European Solid State Circuits Conference, ESSCIR 2021, Grenoble, France, September 13-22, 2021, pp. 459-462, 2021, IEEE, 978-1-6654-3751-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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16 | Hooman Saeidi, Suresh Venkatesh, Xuyang Lu, Kaushik Sengupta |
22.1 THz Prism: One-Shot Simultaneous Multi-Node Angular Localization Using Spectrum-to-Space Mapping with 360-to-400GHz Broadband Transceiver and Dual-Port Integrated Leaky-Wave Antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 314-316, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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16 | Suresh Babu Kotha, Kumar Rahul, Mohammad Anees, Santosh Yachareni, Subodh Kumar |
High speed low power SEU tolerant Pseudo dual port memory in 7nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNCC ![In: International Symposium on Networks, Computers and Communications, ISNCC 2021, Dubai, United Arab Emirates, October 31 - November 2, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-0304-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Omar Farrok, Md. Rabiul Islam 0001, Kashem M. Muttaqi, Danny Sutanto, Jianguo Zhu 0001 |
Design and Optimization of a Novel Dual-Port Linear Generator for Oceanic Wave Energy Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 67(5), pp. 3409-3418, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Moeen Al-Makhlafi, Huaxi Gu, Xiaoshan Yu, Yunfeng Lu |
P-Cube: A New Two-Layer Topology for Data Center Networks Exploiting Dual-Port Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Commun. ![In: IEICE Trans. Commun. 103-B(9), pp. 940-950, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Alejandro Erickson, Javier Navaridas, Iain A. Stewart |
Relating the bisection width of dual-port, server-centric datacenter networks and the solution of edge isoperimetric problems in graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Syst. Sci. ![In: J. Comput. Syst. Sci. 108, pp. 10-28, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu |
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-9942-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Wonwoo Lee, Beakcheol Jang |
A Tunable MIMO Antenna With Dual-Port Structure for Mobile Phones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 34113-34120, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Kunal Das, Arindam Sadhu, Debashis De, Jadav Chandra Das |
Design and simulation of priority based dual port memory in quantum dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 69, pp. 118-137, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4), pp. 1442-1453, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang |
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 390-392, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana |
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 6(2), pp. 184-199, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Hyungkyu Yang, Wonwoo Lee, Byung-Ho Rhee |
A High-Isolation MIMO Antenna with Dual-Port Structure for 5G Mobile Phones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KSII Trans. Internet Inf. Syst. ![In: KSII Trans. Internet Inf. Syst. 12(4), pp. 1458-1470, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pp. 161-164, 2018, IEEE, 978-1-5386-9562-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka |
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 19-20, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang |
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4260-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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16 | Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara |
A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(11), pp. 1061-1068, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Bo Wang 0020, Jun Zhou 0017, Tony Tae-Hyoung Kim |
A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 69, pp. 78-85, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Alejandro Erickson, Iain A. Stewart, Jose Antonio Pascual, Javier Navaridas |
Improved routing algorithms in the dual-port datacenter networks HCN and BCN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 75, pp. 58-71, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Chao Qun Liu, Yue Zheng, Chip-Hong Chang |
A new write-contention based dual-port SRAM PUF with multiple response bits per cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade |
An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pp. 12-17, 2017, IEEE, 978-1-5386-4034-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii |
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 13-16, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Yeongkyo Seo, Kon-Woo Kwon, Xuanyao Fong, Kaushik Roy 0001 |
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3), pp. 293-304, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Qingzhong Jia, Xingdou Wang |
Research on communication technology of complex system based on FPGA dual-port RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAC ![In: 22nd International Conference on Automation and Computing, ICAC 2016, Colchester, United Kingdom, September 7-8, 2016, pp. 32-36, 2016, IEEE, 978-1-86218-132-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 532-535, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Ameer M. S. Abdelhadi, Guy G. F. Lemieux |
A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016, pp. 140-147, 2016, IEEE Computer Society, 978-1-5090-2356-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Mahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David T. Blaauw, Dennis Sylvester |
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 310-312, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang |
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
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