Search results for "dual-rail"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
123	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Design and Analysis of Dual-Rail Circuits for Security Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
113	Karthik Baddam, Mark Zwolinski	Divided Backend Duplication Methodology for Balanced Dual Rail Routing.	CHES	2008	DBLP DOI BibTeX RDF	Dual Rail Routing, Dual Rail FPGA Implementation, Differential Power Analysis
96	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Improving the Security of Dual-Rail Circuits.	CHES	2004	DBLP DOI BibTeX RDF
86	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
86	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
85	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
73	Akira Mochizuki, Takahiro Hanyu	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
73	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.	ISMVL	1999	DBLP DOI BibTeX RDF
72	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	Three-Phase Dual-Rail Pre-charge Logic.	CHES	2006	DBLP DOI BibTeX RDF	dual-rail logic, SABL, security, DPA
72	Thomas Popp, Stefan Mangard	Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.	CHES	2005	DBLP DOI BibTeX RDF	Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis
70	Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama	Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
61	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
59	Alin Razafindraibe, Michel Robert, Philippe Maurine	Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.	PATMOS	2007	DBLP DOI BibTeX RDF
59	Alin Razafindraibe, Michel Robert, Philippe Maurine	Improvement of dual rail logic as a countermeasure against DPA.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
59	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
59	Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine	A Method to Design Compact Dual-rail Asynchronous Primitives.	PATMOS	2005	DBLP DOI BibTeX RDF
59	Geun Rae Cho, Tom Chen 0001	Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
59	Byung-Soo Choi, Dong-Ik Lee	Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.	PATMOS	2003	DBLP DOI BibTeX RDF
58	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
56	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed
56	Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin	Power Balanced Gates Insensitive to Routing Capacitance Mismatch.	DATE	2008	DBLP DOI BibTeX RDF
56	Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald	Delay Insensitive Encoding and Power Analysis: A Balancing Act.	ASYNC	2005	DBLP DOI BibTeX RDF
55	Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani	A Practical DPA Countermeasure with BDD Architecture.	CARDIS	2008	DBLP DOI BibTeX RDF	dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure
47	Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
47	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
47	Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang	A new robust handshake for asymmetric asynchronous micro-pipelines.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
47	Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu	A Robust Handshake for Asynchronous System.	IWSOC	2003	DBLP DOI BibTeX RDF
47	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
45	Fu-Wei Chen, Yi-Yu Liu	Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.	DATE	2008	DBLP DOI BibTeX RDF
45	Akira Mochizuki, Masatomo Miura, Takahiro Hanyu	High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.	ISMVL	2007	DBLP DOI BibTeX RDF
45	Koji Ohashi, Mineo Kaneko	Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	high-level synthesis, asynchronous circuit, datapath, register binding
45	Patrick Schaumont, Kris Tiri	Masking and Dual-Rail Logic Don't Add Up.	CHES	2007	DBLP DOI BibTeX RDF
45	Alin Razafindraibe, Michel Robert, Philippe Maurine	Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.	PATMOS	2006	DBLP DOI BibTeX RDF
45	Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin	Security evaluation of dual rail logic against DPA attacks.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
45	Daisuke Suzuki, Minoru Saeki	Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.	CHES	2006	DBLP DOI BibTeX RDF
45	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
44	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu	Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.	SSIRI	2008	DBLP DOI BibTeX RDF	Power Constant Logic, WDDL, Positive Dual-Rail with Precharge Logic, FPGA, Side-Channel Attacks
44	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
42	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin	Physical Design of FPGA Interconnect to Prevent Information Leakage.	ARC	2008	DBLP DOI BibTeX RDF
42	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
42	Daniele Rossi 0001, S. Cavallotti, Cecilia Metra	Error Correcting Codes for Crosstalk Effect Minimization.	DFT	2003	DBLP DOI BibTeX RDF
41	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
41	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.	CHES	2005	DBLP DOI BibTeX RDF	dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure
41	Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor	Security Evaluation of Asynchronous Circuits.	CHES	2003	DBLP DOI BibTeX RDF	Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis
41	J. Yeandel, D. Thulborn, Simon Jones	An on-line testable UART implemented using IFIS.	VTS	1997	DBLP DOI BibTeX RDF	data communication equipment, online testable UART, IFIS methodology, complex integrated circuit, FPGA technology, dual-rail coding, failure detection, handshaking protocol
41	Eckhard Grass, Simon Jones	Asynchronous circuits based on multiple localised current-sensing completion detection.	ASYNC	1995	DBLP DOI BibTeX RDF	dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
41	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
40	Geun Rae Cho, Tom Chen 0001	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.	VLSI Design	2003	DBLP DOI BibTeX RDF
38	Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng	A semi-custom memory design for an asynchronous 8051 microcontroller.	ISCAS	2008	DBLP DOI BibTeX RDF
38	Jae-Hee Won, Kiyoung Choi	Low power self-timed Radix-2 division (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	RSD, radix-2 division, low power, self-timed
38	Mark E. Dean, David L. Dill, Mark Horowitz	Self-timed logic using Current-Sensing Completion Detection (CSCD).	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
33	Eric Menendez, Ken Mai	A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.	HOST	2008	DBLP DOI BibTeX RDF
33	Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya	A zero-time-overhead asynchronous four-phase controller.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
31	Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng	An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates.	ISCAS	2007	DBLP DOI BibTeX RDF
31	Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya	Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.	APCCAS	2006	DBLP DOI BibTeX RDF
31	Jason Waddle, David A. Wagner 0001	Fault Attacks on Dual-Rail Encoded Systems.	ACSAC	2005	DBLP DOI BibTeX RDF
31	Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa	On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
28	Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu	A dual-rail/single-rail hybrid system using null convention logic circuits.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
28	Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.	ISCAS	2012	DBLP DOI BibTeX RDF
28	Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra	Power Consumption of Fault Tolerant Busses.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
28	Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky	Asynchronous balanced gates tolerant to interconnect variability.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Orna Grumberg, Assaf Schuster, Avi Yadgar	3-Valued Circuit SAT for STE with Automatic Refinement.	ATVA	2007	DBLP DOI BibTeX RDF
28	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani	Power Analysis Attacks on MDPL and DRSL Implementations.	ICISC	2007	DBLP DOI BibTeX RDF	DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop
28	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
28	Myeong-Hoon Oh, Dong-Soo Har	A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
28	Frederic Worm, Paolo Ienne, Patrick Thiran	Soft self-synchronising codes for self-calibrating communication.	ICCAD	2004	DBLP DOI BibTeX RDF
28	T. Felicijan, Stephen B. Furber	An asynchronous ternary logic signaling system.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
28	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
27	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane	Fault Injection Resilience.	FDTC	2010	DBLP DOI BibTeX RDF	Fault Injection Attack (FIA), symmetric block encryption, Fault Injection Resilience (FIR), Differential Fault Analysis (DFA), Dual-rail with Precharge Logic (DPL), Side-Channel Attack (SCA), Denial of Service (DoS)
27	Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu	DPL on Stratix II FPGA: What to Expect?.	ReConFig	2009	DBLP DOI BibTeX RDF	Dual-rail with Precharge Logic (DPL), Wave Dynamic Differential Logic (WDDL), Field Programmable Gates Array (FPGA), Differential Power Analysis (DPA), Commercial Off-The-Shelf (COTS), Side-Channel Analysis (SCA)
27	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar	Parallel vs. serial on-chip communication.	SLIP	2008	DBLP DOI BibTeX RDF	dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
27	Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu	An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node.	ISQED	2008	DBLP DOI BibTeX RDF	Asynchronous Circuit Design, Single Track, Dual-Rail, Fast Forwarding
27	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards.	IEEE Trans. Dependable Secur. Comput.	2007	DBLP DOI BibTeX RDF	differential logic, dual rail logic, chip-cards, cryptography, differential power analysis, DPA, power analysis
27	Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard	Evaluation of the Masked Logic Style MDPL on a Prototype Chip.	CHES	2007	DBLP DOI BibTeX RDF	DPA-Resistant Logic Styles, Masked Logic, Dual-Rail Precharge Logic, Early Propagation Effect, Improved MDPL, Prototype Chip
27	Benedikt Gierlichs	DPA-Resistance Without Routing Constraints?	CHES	2007	DBLP DOI BibTeX RDF	Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP
27	Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan	A New Control Circuit for Asynchronous Micropipelines.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	zero-overhead, dual-rail coding, Asynchronous design, micropipeline
27	Daniel H. Linder, James C. Harden	Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs
24	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
24	Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev	Delay/Phase Regeneration Circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
24	K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov	A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.	IOLTS	2007	DBLP DOI BibTeX RDF
24	Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.	FPL	2006	DBLP DOI BibTeX RDF
24	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
24	Luis A. Plana, Steven M. Nowick	Architectural optimization for low-power nonpipelined asynchronous systems.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
22	Jean Pierre T. Habimana, Francis Sabado, Jia Di	Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation.	ISCAS	2016	DBLP DOI BibTeX RDF
22	Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith	Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
22	Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu	Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.	Int. J. Reconfigurable Comput.	2010	DBLP DOI BibTeX RDF
17	Farzad Niknia, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi	Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
17	Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu	Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
17	David Drahi, Demid V. Sychev, Khurram K. Pirov, Ekaterina A. Sazhina, Valeriy A. Novikov, Ian A. Walmsley, A. I. Lvovsky 0001	Entangled resource for interfacing single- and dual-rail optical qubits.	Quantum	2021	DBLP DOI BibTeX RDF
17	Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi 0001, Taejoong Song, Jongwook Kye	5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
17	Yongjie Lu, Weifeng He	A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor.	ASICON	2021	DBLP DOI BibTeX RDF
17	Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew	A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
17	Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung	An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez 0002, Antonio J. Acosta 0001	Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
17	Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith	Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.	MWSCAS	2020	DBLP DOI BibTeX RDF
17	Xiaosen Liu, Harish K. Krishnamurthy, Claudia P. Barrera, Jing Han, Rajasekhara M. Narayana Bhatla, Scott Chiu, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De	A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
17	Kurt M. English	A highly parallel automated SFQ circuit design and margin optimization tool applied to a dual rail logic single flux quanta cell library.		2020	RDF
17	M. Suresh, A. K. Panda, J. Sudhakar	Low power aware standard cells using dual rail multi threshold null convention logic methodology.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
17	Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li	DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
17	Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang 0096, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang	Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.	AsianHOST	2019	DBLP DOI BibTeX RDF