Search results for "leakage-power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
236	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
198	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
97	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001, Wenping Wang	Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
96	Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester	Gate-length biasing for runtime-leakage control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
93	Jason Helge Anderson, Farid N. Najm	Active leakage power optimization for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
90	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
90	Kamal S. Khouri, Niraj K. Jha	Leakage power analysis and reduction during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
83	Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001	Controlling leakage power with the replacement policy in slumberous caches.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	tranquility level, leakage power, replacement policy, drowsy cache
82	Min Ni, Seda Ogrenci Memik	Thermal-induced leakage power optimization by redundant resource allocation.	ICCAD	2006	DBLP DOI BibTeX RDF
78	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
78	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
78	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
78	Nam Sung Kim, David T. Blaauw, Trevor N. Mudge	Quantitative analysis and optimization techniques for on-chip cache leakage power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
77	Yuan-Shin Hwang, Jia-Jhe Li	Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Caches, leakage power, drowsy caches, cache decay
77	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
76	Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma	Defocus-Aware Leakage Estimation and Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
75	Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache
74	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
73	Kamal S. Khouri, Niraj K. Jha	Leakage Power Analysis and Reduction during Behavioral Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
72	Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir	Analytical models for leakage power estimation of memory array structures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	estimation, SRAMs, leakage power
72	Wei Wang, Yu Hu 0001, Yinhe Han 0001, Xiaowei Li 0001, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
71	Yan Meng, Timothy Sherwood, Ryan Kastner	Leakage power reduction of embedded memories on FPGAs through location assignment.	DAC	2006	DBLP DOI BibTeX RDF	location assignment, leakage power, embedded memory
71	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
70	Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy 0001	Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.	ISLPED	1998	DBLP DOI BibTeX RDF
69	Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang	Accurate temperature-dependent integrated circuit leakage power estimation is easy.	DATE	2007	DBLP DOI BibTeX RDF
68	Houman Homayoun, Ted H. Szymanski	Reducing the Instruction Queue Leakage Power in Superscalar Processors.	CCECE	2006	DBLP DOI BibTeX RDF
68	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
68	Rahul Kumar, C. P. Ravikumar	Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Power Estimation, Leakage Power, Linear Regression, Deep Submicron
66	Yan Meng, Timothy Sherwood, Ryan Kastner	Exploring the limits of leakage power reduction in caches.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	cache intervals, leakage power, Limits
66	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	A sink-n-hoist framework for leakage power reduction.	EMSOFT	2005	DBLP DOI BibTeX RDF	balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
65	Xiaoji Ye, Yaping Zhan, Peng Li 0001	Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.	DAC	2007	DBLP DOI BibTeX RDF
65	Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi	Cache decay: exploiting generational behavior to reduce cache leakage power.	ISCA	2001	DBLP DOI BibTeX RDF
65	Jia-Jhe Li, Yuan-Shin Hwang	Snug set-associative caches: reducing leakage power while improving performance.	ISLPED	2005	DBLP DOI BibTeX RDF	leakage power, set-associative caches
64	Hongliang Chang, Sachin S. Sapatnekar	Prediction of leakage power under process uncertainties.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	process variation, yield, leakage, Circuit
64	Peng Li 0001, Yangdong Deng, Lawrence T. Pileggi	Temperature-Dependent Optimization of Cache Leakage Power Dissipation.	ICCD	2005	DBLP DOI BibTeX RDF
64	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
64	Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001	Closed-loop modeling of power and temperature profiles of FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	sub-threshold leakage, dynamic power
64	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
64	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
63	Mark Hempstead, Gu-Yeon Wei, David M. Brooks	Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations.	CASES	2006	DBLP DOI BibTeX RDF	wireless sensor networks, low power, system architecture, technology scaling, leakage power reduction
62	Akhilesh Kumar, Mohab Anis	An analytical state dependent leakage power model for FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
62	Shilpa Bhoj, Dinesh Bhatia	Early stage FPGA interconnect leakage power estimation.	ICCD	2008	DBLP DOI BibTeX RDF
62	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
62	Xuning Chen, Li-Shiuan Peh	Leakage power modeling and optimization in interconnection networks.	ISLPED	2003	DBLP DOI BibTeX RDF	interconnection networks, leakage power, power optimization
62	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
62	Vishal Khandelwal, Ankur Srivastava 0001	Active mode leakage reduction using fine-grained forward body biasing strategy.	ISLPED	2004	DBLP DOI BibTeX RDF	forward body biasing, leakage power optimization
62	Lei He 0001, Weiping Liao, Mircea R. Stan	System level leakage reduction considering the interdependence of temperature and leakage.	DAC	2004	DBLP DOI BibTeX RDF	microarchitecture, leakage power, temperature
61	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
61	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
61	Daniel Eckerbert, Per Larsson-Edefors	Cycle-true leakage current modeling for CMOS gates.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
61	Le Yan, Jiong Luo, Niraj K. Jha	Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
60	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
60	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
59	Feng Gao 0017, John P. Hayes	Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
59	Preetham Lakshmikanthan, Adrian Nunez	A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
59	Yu Wang 0002, Xiaoming Chen 0003, Wenping Wang, Varsha Balakrishnan, Yu Cao 0001, Yuan Xie 0001, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
59	Wen-Tsong Shiue	Leakage power estimation and minimization in VLSI circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
59	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.	DAC	2006	DBLP DOI BibTeX RDF	leakage, technology mapping, logical effort
59	Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri	A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.	DAC	2005	DBLP DOI BibTeX RDF	leakage power, self-adjusting, body-biasing
58	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.	DAC	2010	DBLP DOI BibTeX RDF	statistical analysis, spatial correlation, dynamic power
58	Chandramouli Gopalakrishnan, Srinivas Katkoori	Behavioral synthesis of datapaths with low leakage power.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
58	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors.	LCPC	2002	DBLP DOI BibTeX RDF
58	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Defocus-aware leakage estimation and control.	ISLPED	2005	DBLP DOI BibTeX RDF	ACLV, yield, leakage, lithography
58	Jun-Cheol Park, Vincent John Mooney III	Sleepy Stack Leakage Reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
58	Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran	SRAM supply voltage scaling: A reliability perspective.	ISQED	2009	DBLP DOI BibTeX RDF
57	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang	Nanoscale CMOS circuit leakage power reduction by double-gate device.	ISLPED	2004	DBLP DOI BibTeX RDF	double-gate device, short-channel effect, leakage power
57	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
57	Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
56	Hongliang Chang, Sachin S. Sapatnekar	Full-chip analysis of leakage power under process variations, including spatial correlations.	DAC	2005	DBLP DOI BibTeX RDF
56	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
56	Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas	A simple mechanism to adapt leakage-control policies to temperature.	ISLPED	2005	DBLP DOI BibTeX RDF	hybrid leakage mechanism, thermal adaptation, drowsy cache, cache decay
56	Xin Li 0001, Jiayong Le, Lawrence T. Pileggi	Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.	DAC	2006	DBLP DOI BibTeX RDF	statistical analysis, leakage power
56	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
56	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Tradeoffs between date oxide leakage and delay for dual Tox circuits.	DAC	2004	DBLP DOI BibTeX RDF	dual Tox circuits, leakage power
55	Siva G. Narendra	Challenges and design choices in nanoscale CMOS.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
55	J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot	A Precise Model for Leakage Power Estimation in VLSI Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
55	Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger	Sleepy Stack Reduction of Leakage Power.	PATMOS	2004	DBLP DOI BibTeX RDF
55	Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge	Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.	MICRO	2002	DBLP DOI BibTeX RDF
55	Liqiong Wei, Zhanping Chen, Kaushik Roy 0001, Mark C. Johnson, Yibin Ye, Vivek De	Design and optimization of dual-threshold circuits for low-voltage low-power applications.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
55	Weiping Liao, Lei He 0001, Kevin M. Lepak	Temperature and supply Voltage aware performance and power modeling at microarchitecture level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
55	Avi Mendelson	Memory management challenges in the power-aware computing era.	ISMM	2006	DBLP DOI BibTeX RDF
54	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.	CASES	2008	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power
54	Haihua Su, Frank Liu 0001, Anirudh Devgan, Emrah Acar, Sani R. Nassif	Full chip leakage estimation considering power supply and temperature variations.	ISLPED	2003	DBLP DOI BibTeX RDF	supply voltage variation, leakage power, thermal analysis
53	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
53	Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka	Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
53	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
52	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	Compilation for compact power-gating controls.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction
52	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail	Power density minimization for highly-associative caches in embedded processors.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	cache, embedded processor, leakage power, temperature
52	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak	Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.	VLSI Design	2006	DBLP DOI BibTeX RDF
52	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
52	Yann-Hang Lee, Krishna P. Reddy, C. Mani Krishna 0001	Scheduling Techniques for Reducing Leakage Power in Hard Real-Time Systems.	ECRTS	2003	DBLP DOI BibTeX RDF
52	Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001	Low-leakage robust SRAM cell design for sub-100nm technologies.	ASP-DAC	2005	DBLP DOI BibTeX RDF
51	Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu	Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks
51	Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee	Leakage power optimization with dual-Vth library in high-level synthesis.	DAC	2005	DBLP DOI BibTeX RDF	dual-Vth, optimization, high-level synthesis, leakage power
51	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
51	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device and architecture considerations.	ISLPED	2003	DBLP DOI BibTeX RDF	forward body-biasing, super high VT, SRAM, leakage power
51	Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken	The challenges of implementing fine-grained power gating.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
50	Ashish Srivastava, Robert Bai, David T. Blaauw, Dennis Sylvester	Modeling and analysis of leakage power considering within-die process variations.	ISLPED	2002	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
50	Houman Homayoun, Alexander V. Veidenbaum	Reducing leakage power in peripheral circuits of L2 caches.	ICCD	2007	DBLP DOI BibTeX RDF
50	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF