Search results for "multiple-valued"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
147	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
136	Hafiz Md. Hasan Babu, Tsutomu Sasao	Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams.	ISMVL	2000	DBLP DOI BibTeX RDF	Binary decision diagram (BDD), multiple-valued decision diagram (MDD), multi-level logic synthesis, look-up table type FPGA design, multiple-valued logic, multiple-output function
116	Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models
109	Jon T. Butler, J. L. Nowlin, Tsutomu Sasao	Planarity in ROMDD's of Multiple-Valued Symmetric Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	ROMDD, multiple-valued symmetric function, reduced ordered multiple-valued decision diagram, logic values, voting functions, multivalued logic, decision diagrams, decision tables, multiple-valued functions, multiple-valued function
107	Guoyin Wang 0001, Hongbao Shi	TMLNN: triple-valued or multiple-valued logic neural network.	IEEE Trans. Neural Networks	1998	DBLP DOI BibTeX RDF
104	Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak	Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations.	ISMVL	1997	DBLP DOI BibTeX RDF	cube diagram bundles, strongly unspecified multiple-valued functions, multiple-valued decomposers, multiple-valued relations, rough partition representation, machine learning, learning (artificial intelligence), function representation
99	Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono	A Necessary and Sufficient Condition for Lukasiewicz Logic Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design
89	Kyoichi Nakashima, Y. Nakamura, Noboru Takagi	Logic Expressions of Monotonic Multiple-Valued Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	partial-ordering relation, unary operators, monotonic multiple-valued functions, monotonic p-valued functions, multivalued logic, multiple-valued logic, multiple-valued functions, logic functions
86	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
75	Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini	A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	multiple-valued clock, CMOS, flip-flops, multiple-valued logic
75	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	On Input Permutation Technique for Multiple-Valued Logic Synthesis.	ISMVL	1995	DBLP DOI BibTeX RDF	input permutation technique, multiple-valued logic synthesis, multiple valued sum of products expressions, TSUM, minimal sum of products expressions, permuted logic values, randomly generated functions, input permutation, output permutation, minimization times, window literals, sum of products expressions, set literals, logic design, set theory, multivalued logic
70	Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.	ISMVL	2008	DBLP DOI BibTeX RDF	multiple-valued logic circuits, arithmetic circuits, high-level design, circuit synthesis
69	Andreas Etzel	Mixed Discrete Optimization of Multiple-Valued Systems.	ISMVL	1997	DBLP DOI BibTeX RDF	mixed discrete optimization, multiple-valued systems, mixed multiple-valued optimization problems, zero-one integer programs, discrete intervals, industrial power plants, integer programming, fuzzy sets, mixed integer programming, flexible manufacturing systems, cutting-plane method
69	Stefan Gerberding	DT - An Automated Theorem Prover for Multiple-Valued First-Order Predicate Logics.	ISMVL	1996	DBLP DOI BibTeX RDF	Deep Thought, multiple-valued first-order logics, lemma generation, tableau expansion, branch closure, theorem proving, multivalued logic, multiple-valued logics, quantifiers, first-order predicate logic, truth tables, automated theorem prover
69	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals.	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
68	Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam 0001, Md. Mazder Rahman	On the Minimization of Multiple-Valued Input Binary-Valued Output Functions.	ISMVL	2004	DBLP DOI BibTeX RDF	Multiple-Valued Input Two-Valued Output Functions, Sum-of-Products (SOPs), Logic Minimization, Prime Implicant
65	Denis V. Popel	Conquering Uncertainty in Multiple-Valued Logic Design.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	machine learning, knowledge representation, information theory, discretization, multiple-valued logic, decision diagrams
64	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
62	Bogdan J. Falkowski, Susanto Rahardja	Complex Spectral Decision Diagrams.	ISMVL	1996	DBLP DOI BibTeX RDF	spectral decision diagrams, Complex Hadamard Transforms, multivalued logic, multiple-valued logic, decision diagrams, decision tables, multiple-valued functions, Hadamard transforms
62	Elena Dubrova, Petra Färm	A Conjunctive Canonical Expansion of Multiple-Valued Functions.	ISMVL	2002	DBLP DOI BibTeX RDF	generalized cofactor, conjunctive decomposition, hamming distance, multiple-valued function
62	Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama	DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.	ISMVL	2000	DBLP DOI BibTeX RDF	logic-in-memory, communication bottleneck, threshold operation, functional pass gate, DRAM, multiple-valued logic
62	Tsutomu Sasao, Jon T. Butler	Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.	ISMVL	1997	DBLP DOI BibTeX RDF	best sum-of-products expressions, worst sum-of-products expressions, logic design algorithms, product terms, multiple-valued variables, upper bound, switching functions, switching functions, multiple-valued functions
62	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation.	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
62	T. C. Wesselkamper, J. Danowitz	Some New Results for Multiple-Valued Genetic Algorithms.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued genetic algorithms, reproduction, classical multiple-valued logic, highly fit population members, genetic algorithms, convergence, selection, multivalued logic, mutation, convergence of numerical methods, genetic operators, theorems
61	Tetsuya Uemura, Toshio Baba	Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop.	ISMVL	2000	DBLP DOI BibTeX RDF	tunnel transistor, multiple-valued T-gate, D-FF, NDR
59	Denis V. Popel, Elena I. Popel	Controlling Uncertainty in Discretization of Continuous Data.	ISMVL	2004	DBLP DOI BibTeX RDF	continuous data, knowledge representation, information theory, discretization, multiple-valued logic, decision diagrams
59	Wang Pengjun, Lu Jingang, Xu Jian	Application of Neuron MOS in multiple-valued logic.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	Neuron MOS transistor, Multiple-valued D/A converter, Multiple-valued A/D converter
58	Igor N. Aizenberg, Claudio Moraga	The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons.	ISMVL	2007	DBLP DOI BibTeX RDF
58	Theodore W. Manikas, Dale Teeters	Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	electrochemical cells, memory, nanotechnology, multiple-valued logic
58	Zheng Tang, Takayuki Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno	Multiple-Valued Immune Network Model and Its Simulations.	ISMVL	1997	DBLP DOI BibTeX RDF	multiple-valued immune network model, biological immune response network, B cells, T cells, experimentally testable predictions, letter recognition application, memory pattern, memory capacity, simulations, multivalued logic circuits, noise immunity
56	Tsutomu Sasao, Jon T. Butler	Planar Multiple-Valued Decision Diagrams.	ISMVL	1995	DBLP DOI BibTeX RDF	planar multiple-valued decision diagrams, monotone increasing functions, binary functions, field programmable gate arrays, programmable logic arrays, multivalued logic circuits, threshold logic, symmetric functions, threshold functions
56	A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
56	Radomir S. Stankovic	Functional Decision Diagrams for Multiple-Valued Functions.	ISMVL	1995	DBLP DOI BibTeX RDF	functional decision diagrams, uniform interpretation, binary switching functions, MV functions, Reed-Muller-Fourier representations, Reed-Muller-Fourier coefficients, decision theory, multivalued logic, Galois fields, Galois field, switching functions, multiple valued functions, multiple-valued functions
55	Elena Dubrova	Implementation of Multiple-Valued Functions Using Literal-Splitting Technique.	ISMVL	2003	DBLP DOI BibTeX RDF
55	Debatosh Debnath, Tsutomu Sasao	Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates.	ISMVL	1999	DBLP DOI BibTeX RDF	Three-level network, programmable logic array, adder, multiple-valued logic, logic minimization
53	Noboru Takagi, Kyoichi Nakashima	Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals.	ISMVL	2002	DBLP DOI BibTeX RDF
53	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	Multiple-Valued Product-of-Sums Expression with Truncated Sum.	ISMVL	1997	DBLP DOI BibTeX RDF
51	Claudio Moraga	Improving the Characterization of p-Valued Threshold Functions.	ISMVL	2002	DBLP DOI BibTeX RDF	Multiple-valued threshold functions, semiduality, table-based realization of m-v threshold functions
51	Nobuaki Okada, Michitaka Kameyama	Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture
51	Susanto Rahardja, Bogdan J. Falkowski	Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	fast mixed arithmetic logic transforms, multiple-valued input binary functions, transform matrices, mixed arithmetic logic spectra, Boolean functions, transforms, matrix algebra, multivalued logic, multivalued logic circuits, inverse transforms
51	Hiroaki Kikuchi, Noboru Takagi, Shohachiro Nakanishi, Masao Mukaidono	Uniqueness of Partially Specified Multiple-Valued Kleenean Function.	ISMVL	1995	DBLP DOI BibTeX RDF	partially specified multiple-valued Kleenean function, logic formula, logical connectives, identification problem, fuzzy logic, multivalued logic, uniqueness, necessary and sufficient condition
50	Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki	Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
50	Bogdan J. Falkowski, Susanto Rahardja	Fast Transforms for Multiple-Valued Input Binary Output PLI Logic.	ISMVL	2000	DBLP DOI BibTeX RDF	GF(2) Logic, Linearly Independent Logic, Multiple Valued Input Binary Functions
50	Elena Dubrova, Harald Sack	Probabilistic Verification of Multiple-Valued Functions.	ISMVL	2000	DBLP DOI BibTeX RDF	multiple-valued functions, hash code, probabilistic verification
50	Elena Dubrova, Jon C. Muzio, Bernhard von Stengel	Finding Composition Trees for Multiple-Valued Functions.	ISMVL	1997	DBLP DOI BibTeX RDF	composition trees, disjunctive decompositions, m-valued n-variable functions, test generation, multivalued logic, computation time, multiple-valued functions, recursive algorithm
50	Grant Pogosyan, Akihiro Nozaki	Join-Irreducible Clones of Multiple-Valued Logic Algebra.	ISMVL	1995	DBLP DOI BibTeX RDF	join-irreducible clones, multiple valued logic algebra, synthetic means, lattice elements, join irreducible elements, unary functions, constructive criteria, graph theoretical property, one variable function, k valued logic, graph theory, set theory, multivalued logic, group theory, monoids, join operation, generating system
49	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
48	H. Kondou, Sumio Fukai, Yohei Ishikawa	Multiple-valued SRAM with FG-MOSFETs.	APCCAS	2006	DBLP DOI BibTeX RDF
48	Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul	An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions.	ICCD	1995	DBLP DOI BibTeX RDF	minimization algorithm, exclusive-OR sum-of-products, rule-based heuristics, initial circuit description, MINT, multiple-product-term transformations, multiple-valued input two-valued multiple-output functions, knowledge based systems, logic design, heuristic programming, minimisation of switching nets, incompletely specified functions
47	Igor N. Aizenberg, Claudio Moraga	The Genetic Code as a Function of Multiple-Valued Logic Over the Field of Complex Numbers and its Learning using Multilayer Neural Network Based on Multi-Valued Neurons.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
47	Sumiyasu Yamamoto, Shinsei Tazawa, Kazuhiko Ushio, Hideto Ikeda	Design of a Balanced Multiple Valued File Organization Schema with the Least Redundancy.	ACM Trans. Database Syst.	1979	DBLP DOI BibTeX RDF	balanced filing scheme, claw, multipartite graph, multiple-valued attributes, secondary index, information retrieval, redundancy, inverted file, file organization, graph decomposition, information storage, bucket
47	Emre Özer 0001, Resit Sendag, David Gregg	Multiple-Valued Caches for Power-Efficient Embedded Systems.	ISMVL	2005	DBLP DOI BibTeX RDF
47	Denis V. Popel, Rolf Drechsler	Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions.	ISMVL	2003	DBLP DOI BibTeX RDF
47	Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama	Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.	ISMVL	1999	DBLP DOI BibTeX RDF
46	Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim	Fault Analysis of the Multiple Valued Logic Using Spectral Method.	ISMVL	2000	DBLP DOI BibTeX RDF	spectral domain, bridging fault, multiple valued logic, fault analysis
46	K. J. Adams, Jonathan G. Campbell, Liam P. Maguire, J. A. C. Webb	State Assignment Techniques in Multiple-Valued Logic.	ISMVL	1999	DBLP DOI BibTeX RDF	Multiple-Valued Logic, Galois Fields, State Assignment, Transform matrix
46	Takao Waho	Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits.	ISMVL	1995	DBLP DOI BibTeX RDF	resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability
45	Radomir S. Stankovic, Jaakko Astola	Edge-Valued Decision Diagrams for Multiple-Valued Functions.	ISMVL	2004	DBLP DOI BibTeX RDF
45	Denis V. Popel	From Continuous to Multiple-valued Data.	ISMVL	2003	DBLP DOI BibTeX RDF
45	Jon T. Butler, Tsutomu Sasao	On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.	ISMVL	2003	DBLP DOI BibTeX RDF
45	K. Vijayan Asari, C. Eswaran	An Optimization Technique for the Design of Multiple Valued PLA's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis
45	Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design
45	Thyagaraju R. Damarla	Generalized Transforms for Multiple Valued Circuits and Their Fault Detection.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	generalised transforms, simple transforms, multiple value network, multiple valued circuits, spectral coefficients, VLSI, transforms, fault detection, upper bound, fault location, stuck at faults, many-valued logics, bridging faults, logic circuits, multiple valued functions, test patterns, test set generation, canonical representation, radix
45	Parthasarathy P. Tirumalai, Jon T. Butler	Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	minimisation algorithms, multiple-valued programmable logic arrays, sum-of products, MIN operation, random-symmetric functions, constrained implicant sets, charge-coupled device circuits, performance, CMOS, heuristic algorithms, many-valued logics, minimisation, CMOS integrated circuits, backtracking, logic arrays, tree search, multiple-valued functions, charge-coupled device
45	John A. Chandy, Faquir C. Jain	Multiple Valued Logic Using 3-State Quantum Dot Gate FETs.	ISMVL	2008	DBLP DOI BibTeX RDF	multiple-valued logic, quantum dots
45	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller	On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams.	ISMVL	2008	DBLP DOI BibTeX RDF	Quantum Logic Decision Diagrams, Quantum Computing, Multiple-valued Logic, Reversible Logic
45	Alioune Ngom, Dan A. Simovici, Ivan Stojmenovic	Evolutionary Strategy for Learning Multiple-Valued Logic Functions.	ISMVL	2004	DBLP DOI BibTeX RDF	Multiple-threshold perceptron, Neural network, Evolution strategy, Multiple-valued logic, Constructive algorithm, Partitioning method
45	Bogdan J. Falkowski, Beata T. Olejnicka	Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images.	ISMVL	2002	DBLP DOI BibTeX RDF	Variable segmentation, Biomedical images, Multiple-Valued functions, Walsh transform, Lossless image compression, Reed-Muller transform
45	Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko	The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model.	ISMVL	2002	DBLP DOI BibTeX RDF	multiple-valued logic functions, linear word-level expressions, word-level decision diagrams
45	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui	PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM
45	Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko	The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model.	ISMVL	2002	DBLP DOI BibTeX RDF	multiple-valued logic circuits, word-level decision diagrams
45	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.	ISMVL	2002	DBLP DOI BibTeX RDF	Ferroelectric capacitor, multiple-valued current-mode logic circuit, arithmetic operation, full adder
45	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
45	Bogdan J. Falkowski, Lip-San Lim	Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra.	ISMVL	2000	DBLP DOI BibTeX RDF	logic coding, multiple-valued input binary functions, Lossless compression, Gray scale images, Walsh transform, Reed-Muller transform
45	Yutaka Hata, Syoji Kobashi, Naotake Kamiura, Yuri T. Kitamura, Toshio Yanagida	On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic.	ISMVL	2000	DBLP DOI BibTeX RDF	MR brain image, medical image, registration, multiple-valued logic
45	Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui	Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm.	ISMVL	2000	DBLP DOI BibTeX RDF	controllability measure, observability measure, test generation, multiple-valued logic, D-algorithm
45	M. Ryu, Michitaka Kameyama	Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.	ISMVL	1995	DBLP DOI BibTeX RDF	highly parallel multiple-valued linear digital system, k-ary operations, extended representation matrices, minimum critical path delay, unary operations, sparse representation matrices, output digit, decomposed unary operations, delays, multivalued logic circuits, sparseness, superposition, code assignment, signal representation
45	Zheng Tang, Okihiko Ishizuka, Koichi Tanno	Learning Multiple-Valued Logic Networks Based on Back Propagation.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness
45	Tadeusz Luba	Decomposition of Multiple-Valued Functions.	ISMVL	1995	DBLP DOI BibTeX RDF	silicon space, PLA implementations, information storing systems, information systems, logic design, decomposition, logic synthesis, programmable logic arrays, multivalued logic, logic circuits, data bases, multiple-valued functions
44	Elena Dubrova	Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.	ISMVL	1999	DBLP DOI BibTeX RDF	Reed-Muller canonical form, fixed polarity, multiple-valued function
44	R. Oenning, Claudio Moraga	Properties of the Zhang-Watari Transform.	ISMVL	1995	DBLP DOI BibTeX RDF	2D multiple-valued Haar transform, 2D real valued Zhang-Watari transform, Haar spectrum, real arithmetic, permutation operation, extended 1D results, 2D Chrestenson transform, pattern partition, pattern recognition, patterns, transforms, multivalued logic, combinatorial mathematics
44	Robert J. Bignall, Matthew Spinks	Multiple-Valued Logic as a Programming Language.	ISMVL	1997	DBLP DOI BibTeX RDF
44	Omid Mirmotahari, Yngvar Berg	A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC.	ISMVL	2003	DBLP DOI BibTeX RDF
43	Elena Dubrova	A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions.	ISMVL	2004	DBLP DOI BibTeX RDF
43	Toshio Baba	Development of Quantum Functional Devices for Multiple-Valued Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF
43	Alioune Ngom, Ivan Stojmenovic, Jovisa D. Zunic	On the Number of Multilinear Partitions and the Computing Capacity of Multiple-Valued Multiple-Threshold Perceptrons.	ISMVL	1999	DBLP DOI BibTeX RDF	k-valued s- threshold perceptron, (k,k)-grid, minimal pair, general position, complexity, partition, separability, multiple-valued logic, Farey sequences
42	Ofer Arieli, Marc Denecker	Modeling Paraconsistent Reasoning by Classical Logic.	FoIKS	2002	DBLP DOI BibTeX RDF
42	Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler	Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.	ISMVL	2007	DBLP DOI BibTeX RDF
42	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
40	Radomir S. Stankovic, Jaakko Astola	Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups.	ISMVL	2008	DBLP DOI BibTeX RDF	sampling theorem, spectral coefficients, multiple-valued logic, non-Abelian groups
40	Elena Dubrova, Jon C. Muzio	Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Reed-Muller circuit, easily testable circuit, stuck-at fault, Multiple-valued function
40	Tsutomu Sasao	Design Methods for Multiple-Valued Input Address Generators.	ISMVL	2006	DBLP DOI BibTeX RDF
40	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.	ISMVL	2006	DBLP DOI BibTeX RDF
40	Jaakko Astola, Radomir S. Stankovic	Signal Processing Algorithms and Multiple-Valued Logic Design Methods.	ISMVL	2006	DBLP DOI BibTeX RDF
40	Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama	Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.	ISMVL	2005	DBLP DOI BibTeX RDF
40	Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama	Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
40	D. Michael Miller, Rolf Drechsler	On the Construction of Multiple-Valued Decision Diagrams.	ISMVL	2002	DBLP DOI BibTeX RDF
40	Claudio Moraga, Ralph Heider	"New lamps for old!" (Generalized Multiple-valued Neurons).	ISMVL	1999	DBLP DOI BibTeX RDF
40	Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato	Multiple-Valued Logic Minimization by Genetic Algorithms.	ISMVL	1997	DBLP DOI BibTeX RDF
39	Ivan Prokic	Characterization of Multiple-Valued Threshold Functions in the Vilenkin-Chrestenson Basis.	J. Multiple Valued Log. Soft Comput.	2020	DBLP BibTeX RDF