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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 609 occurrences of 276 keywords
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Results
Found 516 publication records. Showing 516 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
59 | Issam Alzaher-Noufal, Michael Nicolaidis |
A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 122-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits |
53 | Michel Diaz, Guy Juanole, Jean-Pierre Courtiat |
Observer-A Concept for Formal On-Line Validation of Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(12), pp. 900-913, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
observer concept, formal online validation, self-checking distributed systems design, erroneous behavior detection, observable output level, continuous checking, formal verified model, quasi-self-checking observers, industrial LAN, broadcast service, virtual ring MAC protocol testing, OSI layering management, open system architecture, run-time validation, Petri net based models, layered distributed architectures, formal verification, distributed processing, local area networks, transport protocols, performance measurements, open systems, access protocols, formal description techniques, transport layer, reference, link layer, online operation |
50 | Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis |
Totally Self Checking reconfigurable duplication system with separate internal fault indication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 316-321, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication |
47 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 64-73, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
47 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 460-466, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
46 | Petros Oikonomakos, Mark Zwolinski |
On the Design of Self-Checking Controllers with Datapath Interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(11), pp. 1423-1434, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault tolerance, Reliability, testing, automatic synthesis, error-checking, redundant design |
45 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
Design for Self-Checking and Self-Timed Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 417-430, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits |
44 | Michael Nicolaidis |
Efficient UBIST implementation for microprocessor sequencing parts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 295-312, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits |
44 | Michael Nicolaidis |
Shorts in self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 257-273, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
43 | Ilya Levin, Vladimir Sinelnikov |
Self-Checking of FPGA-Based Control Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 292-295, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | José Manuel Cazeaux, Daniele Rossi 0001, Cecilia Metra |
Self-Checking Voter for High Speed TMR Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(4), pp. 377-389, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high reliabily, duplication and comparison, self-checking, voter, TMR systems |
42 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A Totally Self-Checking Dynamic Asynchronous Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 27-32, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider |
42 | Michael J. Liebelt, Cheng-Chew Lim |
A method for determining whether asynchronous circuits are self-checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 472-477, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise |
42 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 27-36, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits |
42 | Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian |
Efficient Totally Self-Checking Shifter Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 29-39, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
parity prediction, fault-secure circuits, on-line testing, self-checking circuits |
39 | Petros Oikonomakos, Mark Zwolinski |
Foundation of Combined Datapath and Controller Self-checking Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 30-34, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Niraj K. Jha, Sying-Jyan Wang |
Design and synthesis of self-checking VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6), pp. 878-887, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
39 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 332-336, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Ilana David, Ran Ginosar, Michael Yoeli |
Self-timed is self-checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 219-228, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
finite state machines, asynchronous systems, combinational logic, self-checkings, self-timed |
39 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Highly testable and compact single output comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 210-215, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparators (circuits), single output comparator, self-checking n-input comparator, n-variable two-rail checker, equality checker, strongly code-disjoint, input code words, embedded comparators, VLSI, fault detection, totally-self-checking |
38 | Steven W. Burns, Niraj K. Jha |
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(4), pp. 490-495, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
parallel unordered coding scheme, parallel encoding/decoding, information symbols, checkbits, TSC checker, parallel algorithms, built-in self test, logic design, error detection codes, error-detecting codes, concurrent error detection, transient faults, unidirectional errors, totally self-checking checker, unordered codes, self-checking checker |
38 | Nikolaos Gaitanis |
Totally Self-Checking Checkers with Separate Internal Fault Indication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(10), pp. 1206-1213, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
separate internal fault indication, functional circuit, two-element Boolean algebra, self-checking operator blocks, logic testing, fault location, fault, design technique, totally self-checking checkers, algebraic approach |
37 | Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky |
Synthesis of ASM-based Self-Checking Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 87-93, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 403-411, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
SSMM, fault tolerance, finite state machine, VHDL, signature analysis, self checking |
36 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 560-574, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults |
36 | Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal |
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 55-66, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Concurrent checking, self–checking circuits, timing faults, very deep submicron, hardware fault tolerance, soft errors, defects, nanometer technologies |
36 | Vladimír Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois |
Thermal Monitoring of Self-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 81-92, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
self-checking circuits, thermal testing, temperature sensors, thermal sensors |
36 | Donatella Sciuto, Cristina Silvano, Renato Stefanelli |
Systematic AUED Codes for Self-Checking Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 183-191, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
AUED Codes, Self-Checking Combinational Circuits, Stuck-at Faults, Unidirectional Errors |
36 | Michele Favalli, Cecilia Metra |
Low-level error recovery mechanism for self-checking sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 234-242, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
low-level error recovery mechanism, self-checking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults |
34 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 275-279, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Niraj K. Jha |
A totally self-checking checker for Borden's code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7), pp. 731-736, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
33 | Steffen Tarnick |
Controllable self-checking checkers for conditional concurrent checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 547-553, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
33 | Stanislaw J. Piestrak |
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(6), pp. 735-736, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TSC Berger code checker, Berger code, totally self-checking circuit, self-testing checker, two-rail code |
30 | Jerzy W. Greblicki, Jerzy Kotowski |
Automated Design of Totally Self-Checking Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2009, 12th International Conference, Las Palmas de Gran Canaria, Spain, February 15-20, 2009, Revised Selected Papers, pp. 98-105, 2009, Springer, 978-3-642-04771-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sequential circuits, Fault tolerant systems, totally self-checking circuits |
30 | Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin |
Survivable Self-Checking Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 395-402, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
self-checking sequential machines, survivable circuits, partially monotonous functions |
30 | Anzhela Yu. Matrosova, Sergey Ostanin |
Self-Checking FSM Design with Observing only FSM Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 153-154, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Self-checking design, unidirectional fault, PLA description, multilevel synthesis, FSM |
30 | Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri |
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 274-, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Self-checking systems, Field Programmable Gate Arrays, Artificial neural networks, Space applications |
30 | Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee |
Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 82-87, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in intermediate voltage sensor, bridging fault, totally self-checking circuit |
30 | Shujian Zhang, Jon C. Muzio |
Evaluating the safety of self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 243-253, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fail-safe evaluation, TSC, Markov model, self-checking circuit |
30 | Fadi Y. Busaba, Parag K. Lala |
A graph coloring based approach for self-checking logic circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 327-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault |
30 | Fadi Y. Busaba, Parag K. Lala |
Self-checking combinational circuit design for single and unidirectional multibit error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 19-28, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Input encoding, output encoding, unidirectional error, self-checking |
29 | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
Modified Stability Checking for On-line Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 787-792, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection |
29 | Anna Antola, Vincenzo Piuri, Mariagiovanna Sami |
High-level Synthesis of Data Paths with Concurrent Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 292-300, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
self-checking systems, high-level synthesis, concurrent error detection, data path |
28 | Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006 |
Design and Test of Self-checking Asynchronous Control Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 320-329, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Self Checking Reed Solomon Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 201-202, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Dilip P. Vasudevan, Parag K. Lala |
A Technique for Modular Design of Self-Checking Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 325-333, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | C. K. Tang, Parag K. Lala, James Patrick Parkerson |
A Technique for Designing Totally Self-Checking Domino Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 128-132, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | José Manuel Cazeaux, Daniele Rossi 0001, Cecilia Metra |
New High Speed CMOS Self-Checking Voter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 58-66, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale |
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 207-215, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto |
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 98-103, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois |
Design of self-checking fully differential circuits and boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 113-128, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Michele Favalli, Cecilia Metra |
On the Design of Self-Checking Functional Units Based on Shannon Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 368-375, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Kanji Hirabayashi |
Self-checking CMOS circuits using pass-transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(2), pp. 205-208, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
28 | David S. Rosenblum, Sriram Sankar, David C. Luckham |
Concurrent Runtime Checking of Annotated Ada Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, Sixth Conference, New Delhi, India, December 18-20, 1986, Proceedings, pp. 10-35, 1986, Springer, 3-540-17179-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
27 | Daniel Etiemble |
Multivalued I2L Circuits for TSC Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(6), pp. 537-540, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
totally self-checking comparator, multivalued logic, Error-detecting codes, totally self-checking checkers, I |
27 | Dhiraj K. Pradhan |
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(5), pp. 396-404, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
upper bound on the number of state variables, fault-secure networks, self-checking networks, single-transition-time assignments, unate next-state functions, unidirectional faults, universal assignments, fault detection, Asynchronous networks, Berger codes, self-checking checker |
27 | Alberto Bartoli, Giovanni Masarin |
On-line self-checking of replication consistency for autonomic computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 9(4), pp. 449-463, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fault detectors, Web services, Dependability, Availability, On-line testing, Self-check |
27 | Danny C. C. Ko, Melvin A. Breuer |
The design of self-checking multi-output combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1977 National Computer Conference, June 13-16, 1977, Dallas, Texas, USA, pp. 711-721, 1977, AFIPS Press, 978-1-4503-7914-4. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
|
26 | Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami |
Semiconcurrent Error Detection in Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(5), pp. 449-465, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Semiconcurrent error detection, checking periodicity, resource minimization, fault tolerance, high-level synthesis, data flow graph, self-checking circuits |
26 | Anna Antola, Vincenzo Piuri, Mariagiovanna Sami |
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 266-272, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Semi-concurrent error detection, Fault tolerance, High-level synthesis, Data Flow Graphs, Self-checking circuits |
25 | Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky |
Self-checking sequential circuits with self-healing ability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 71-76, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra |
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 93-103, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Error detecting codes, Transient faults, Self-checking circuits, Checker |
25 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Low Cost and High Speed Embedded Two-Rail Code Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(2), pp. 153-164, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Self-checking circuits, checkers, error indicators, two-rail code |
25 | Michael Nicolaidis, Yervant Zorian |
On-Line Testing for VLSI - A Compendium of Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 7-20, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
fail-safe circuits, SEU hardened circuits, monitoring of reliability indicators, thermal monitors, radiation monitors, on-line testing, self-checking circuits, current monitors |
25 | Michele Favalli, Cecilia Metra |
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(3), pp. 273-283, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bus based systems, on-line testing, two-rail checker |
25 | Michele Favalli, Cecilia Metra |
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 100-105, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Jerzy W. Greblicki, Stanislaw J. Piestrak |
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-3, Third European Dependable Computing Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings, pp. 251-266, 1999, Springer, 3-540-66483-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis |
An SFS Berger check prediction ALU and its application to self-checking processor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 525-540, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Wonhak Hong, Rajashekhar Modugu, Minsu Choi |
Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(9), pp. 1354-1365, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Modulo 2^n+1 multiplier, arithmetic circuit design, compressor, online self-checking, international data encryption algorithm (IDEA), residue arithmetic |
25 | Wen-Feng Chang, Cheng-Wen Wu |
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(8), pp. 815-826, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault tolerance, logic testing, on-line testing, totally-self-checking checker, m-out-of-n code |
25 | Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis |
Concurrent Delay Testing in Totally Self-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 55-61, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators |
25 | Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis |
A Totally Self-Checking 1-out-of-3 Code Error Indicator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 61-66, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
1-out-of-3 code, totally self checking circuits, error indicator |
25 | Jien-Chung Lo |
A Hyper Optimal Encoding Scheme for Self-Checking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(9), pp. 1022-1030, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic circuit synthesis, output encoding, Concurrent error detection, self-checking circuits, unordered codes |
25 | D. A. Pierce, Parag K. Lala |
Modular implementation of efficient self-checking checkers for the Berger code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 279-294, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
conventional Berger code, 1's counters, fully-testable circuits, partitioning, CMOS technology, totally self-checking checkers, Berger code |
25 | Steven S. Gorshe, Bella Bose |
A self-checking ALU design with efficient codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 157-161, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors |
25 | Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis |
An asynchronous totally self-checking two-rail code error indicator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 151-156, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults |
25 | Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos |
Efficient Totally Self-Checking Checkers for a Class of Borden Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(11), pp. 1318-1322, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Borden codes, t-unidirectional error detecting (t-UED) codes, fault tolerant, fault detection, totally self-checking checker |
25 | Niraj K. Jha |
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(2), pp. 179-189, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers |
25 | T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo |
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(8), pp. 1020-1024, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
totally self-checking Berger code checker designs, generalized Berger code partitioning, m-out-of-n checker, error correction codes, error detection codes |
25 | Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram |
Design of Self-Checking Circuits Using DCVS Logic: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(7), pp. 891-896, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
DCVS logic, differential cascode voltage switch, low hardware-overhead costs, fault tolerance, fault tolerant computing, logic design, error detection, error correction, logic circuits, self-checking circuits |
25 | Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala |
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(7), pp. 881-886, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker |
25 | Jien-Chung Lo, Suchai Thanawastien |
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(3), pp. 387-393, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
combinational totally self-checking 1-out-of-3 code checkers, NMOS, TSC goal, fault sequences, minimum fault sequences, MOS integrated circuits, logic testing, logic design, automatic testing, integrated logic circuits |
25 | Sudhir Dhawan, Ronald C. de Vries |
Design of Self-Checking Sequential Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(10), pp. 1280-1285, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
error transmission, self-checking sequential machines, design, error detection, flip-flops, flip-flops, sequential machines, excitation, memory elements |
25 | Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou |
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(7), pp. 807-814, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
low-cost arithmetic codes, reliability, fault tolerant computing, partitioning, trees, error detection codes, totally self-checking checkers, gate levels |
25 | Sudhir Dhawan, Ronald C. de Vries |
Design of Self-Checking Iterative Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(9), pp. 1121-1125, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
iterative network, iterated switching networks, redundancy, error detection, combinational circuit, error, combinatorial circuits, self-checking |
25 | Nikolaos Gaitanis |
Totally Self-Checking Checkers for Low-Cost Arithmetic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(7), pp. 596-601, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
TSC residue generators, Inverse residue codes, low-cost codes, totally self-checking checkers |
25 | Petr Golan |
Design of Totally Self-Checking Checker for 1-out-of-3 Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(3), pp. 285, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
fixed-weight codes, 1-out-of-3 code, TSC checkers, totally self-checking checkers, Constant weight codes, m-out-of-n codes |
25 | Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala |
Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(5), pp. 507-511, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
totally self-checking checkers, m-out-of-n codes |
25 | W. Kenneth Jenkins |
The Design of Error Checkers for Self-Checking Residue Number Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(4), pp. 388-396, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
Digital processors, self-checking arithmetic, fault tolerance, modular arithmetic, special purpose hardware, residue arithmetic |
25 | K. V. S. S. Prasad Rao, Dhruba Basu |
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(5), pp. 464-475, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
time domain redundancy, self-dual function, space domain redundancy, CMOS, multiple faults, self-checking circuits, combinatorial logic |
25 | James E. Smith 0001, Paklin Lam |
A Theory of Totally Self-Checking System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(9), pp. 831-844, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
totally self-checking systems, Checker placement, detecting codes, self-testing, error propagation, fault secure |
25 | Javad Khakbaz |
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(7), pp. 677-681, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
code disjoint, 1-out-of-n code, programmable logic array (PLA) totally self-checking (TSC), Checker, two-rail code |
22 | Pavel Kubalík, Petr Fiser, Hana Kubátová |
Fault Tolerant System Design Method Based on Self-Checking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 185-186, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Adam Matthews |
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 519-524, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld |
A Modulo p Checked Self-Checking Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 25-29, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cecilia Metra, Stefano Di Francescantonio, Martin Omaña 0001 |
Automatic Modification of Sequential Circuits for Self-Checking Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 417-424, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli |
Self-Checking Scheme for the On-Line Testing of Power Supply Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 832-836, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Luca Schiano, Cecilia Metra, Diego Marino |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 49-56, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Luca Schiano, Cecilia Metra, Diego Marino |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 243-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Parag K. Lala, Alfred L. Burress |
A technique for designing self-checking logic for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 94-96, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
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