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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 3867 publication records. Showing 3867 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
104 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Global interconnect sizing and spacing with consideration of coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 628-633, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance |
86 | Puneet Gupta 0001, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma |
Eyecharts: constructive benchmarking of gate sizing heuristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 597-602, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic programming, benchmarking, gate sizing |
80 | Chung-Ping Chen, D. F. Wong 0001 |
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 604-607, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
78 | Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal |
Optimal wire and transistor sizing for circuits with non-tree topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 252-259, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
optimal circuit sizing, crosstalk, Elmore delay, clock distribution networks |
75 | Jason Cong, Lei He 0001 |
An efficient approach to simultaneous transistor and interconnect sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 181-186, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing |
72 | Chris C. N. Chu, D. F. Wong 0001 |
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 343-371, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing |
70 | Vishal Khandelwal, Ankur Srivastava 0001 |
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 11-18, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing |
70 | Narender Hanchate, Nagarajan Ranganathan |
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 1011-1023, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay |
69 | Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera |
Crosstalk noise optimization by post-layout transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 126-130, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise |
69 | Alain Abran, Marcela Maya |
A sizing measure for adaptive maintenance work products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: Proceedings of the International Conference on Software Maintenance, ICSM 1995, Opio (Nice), France, October 17-20, 1995, pp. 286-294, 1995, IEEE Computer Society, 0-8186-7141-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
software sizing measure, adaptive maintenance work products, productivity analysis, sizing technique, software maintenance, software maintenance, software metrics, organization, granularity, software development management, software cost estimation, human resource management, Function Points, productivity models |
66 | Ashutosh Chakraborty, David Z. Pan |
On stress aware active area sizing, gate sizing, and repeater insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 35-42, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, buffer, sizing, stress, repeater |
64 | Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich |
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 323-327, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
64 | Chris C. N. Chu, D. F. Wong 0001 |
VLSI Circuit Performance Optimization by Geometric Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 105(1-4), pp. 37-60, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
63 | Narender Hanchate, Nagarajan Ranganathan |
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 711-739, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay |
63 | William Roshan Quadros, Ved Vyas, Michael L. Brewer, Steven J. Owen, Kenji Shimada |
A Computational Framework for Generating Sizing Function in Assembly Meshing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMR ![In: Proceedings of the 14th International Meshing Roundtable, IMR 2005, September 11-14, 2005, San Diego, CA, USA, pp. 55-72, 2005, Springer, 978-3-540-25137-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Assembly meshing, finite element mesh sizing function, pre-mesh, skeleton |
61 | Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001 |
Optimal non-uniform wire-sizing under the Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 38-43, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation |
61 | Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal |
Optimizing dominant time constant in RC circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 110-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
60 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 565-572, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Chris C. N. Chu, D. F. Wong 0001 |
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 479-485, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing |
57 | Vishal Khandelwal, Ankur Srivastava 0001 |
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4), pp. 610-620, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
57 | Murari Mani, Mahesh Sharma, Michael Orshansky |
Application of fast SOCP based statistical sizing in the microprocessor design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 372-375, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Chris C. N. Chu, D. F. Wong 0001 |
Greedy wire-sizing is linear time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 39-44, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
57 | Qing Zhu, Wayne Wei-Ming Dai |
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1106-1118, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
55 | Jiang Wu, Zhizhong Li 0003, Jianwei Niu 0003 |
A 3D Method for Fit Assessment of a Sizing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (11) ![In: Digital Human Modeling, Second International Conference, ICDHM 2009, Held as Part of HCI International 2009, San Diego, CA, USA, July 19-24, 2009. Proceedings, pp. 737-743, 2009, Springer, 978-3-642-02808-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fit assessment, sizing system, 3D modeling |
55 | Paul G. A. Jespers |
Sizing CMOS circuits by means of the gm/ID methodology and a compact model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 1, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
circuit sizing |
55 | Mehdi Hakimi, Seyyed Masoud Moghaddas Tafreshi, M. R. Rajati |
Unit Sizing of a Stand-Alone Hybrid Power System Using Model-Free Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GrC ![In: 2007 IEEE International Conference on Granular Computing, GrC 2007, San Jose, California, USA, 2-4 November 2007, pp. 751-756, 2007, IEEE Computer Society, 0-7695-3032-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reformer, hybrid power system, optimal sizing, particle swarm optimization I. NOMENCLATURE P conv wg - Power delivered from wind turbines to converter (kw) P el wg - Power delivered from wind turbines to electrolyzer (kw) P k el tan - Power delive, K. N. Toosi University of Technology, Tehran-Iran (e-mail: sm_hakimi@yahoo.com). S.M.M.Tafreshi is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: tafreshi@eetd.kntu.ac.ir). M. R. Rajati is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: mohammadreza.rajati@gmail.com). P wt Power generated by wind turbines (kw) Pload Load power (kw) E k tan Stored energy in the hydrogen tank (kwh) fc, el, conv Efficiency of fuel cell, electrolyzer, converter NPCindex Net present cost (the index shows the corresponding component) ($) S Single-payment present worth factor R Life time of project (year) L Life time of each components (year) Ir Inter, fuel cell, wind turbine |
55 | Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu |
Optimal gate sizing for coupling-noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 176-181, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
coupling-noise, gate-sizing, lattice theory, fixpoint |
55 | Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj |
Post-route gate sizing for crosstalk noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 954-957, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
crosstalk noise repair, gate sizing |
55 | Takumi Okamoto, Jason Cong |
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 44-49, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing |
55 | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 467-470, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications |
55 | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
An iterative gate sizing approach with accurate delay evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 422-427, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay evaluation, linear program, iteration, gate sizing |
53 | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay |
Interconnect synthesis without wire tapering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 90-104, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1915-1924, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 113-116, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia |
Fast interconnect synthesis with layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 71-77, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
buffer insertion, wire sizing, layer assignment, interconnect synthesis |
49 | Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh |
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1788-1797, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
Sizing Rules for Bipolar Analog Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 140-145, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi |
Wire Sizing for Non-Tree Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 872-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Lakulish Antani, Christophe Delage, Pierre Alliez |
Mesh Sizing with Additively Weighted Voronoi Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMR ![In: Proceedings of the 16th International Meshing Roundtable, October 14-17, 2007, Seattle, Washington, USA, Proceedings, pp. 335-346, 2007, Springer, 978-3-540-75102-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Jia Wang 0003, Debasish Das, Hai Zhou 0001 |
Gate sizing by Lagrangian relaxation revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 111-118, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang |
Switching-activity driven gate sizing and Vth assignment for low power design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 576-581, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Narender Hanchate, Nagarajan Ranganathan |
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 283-290, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 136-141, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Yue Chen, Barry W. Boehm, Raymond J. Madachy, Ricardo Valerdi |
An Empirical Study of eServices Product UML Sizing Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISESE ![In: 2004 International Symposium on Empirical Software Engineering (ISESE 2004), 19-20 August 2004, Redondo Beach, CA, USA, pp. 199-206, 2004, IEEE Computer Society, 0-7695-2165-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Ashok K. Murugavel, N. Ranganathan |
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 195-200, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Marko Loparic, Hugues Marchand, Laurence A. Wolsey |
Dynamic knapsack sets and capacitated lot-sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 95(1), pp. 53-69, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 104-109, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 173-182, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
49 | Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen |
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 374-381, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
behavioral signal path, incremental modeling, small-signal, sequential design space pruning, minimax optimization |
49 | Jason Cong, Cheng-Kok Koh |
Simultaneous driver and wire sizing for performance and power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 408-425, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
49 | Jason Cong, Cheng-Kok Koh |
Simultaneous driver and wire sizing for performance and power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 206-212, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
49 | Edward G. Rodgers |
Software sizing problems in software engineering metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the Sixteenth ACM Annual Conference on Computer Science, Atlanta, Georgia, USA, February 23-25, 1988, pp. 713-714, 1988, ACM, 0-89791-260-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
48 | Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002 |
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 87-90, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
STT MRAM, defect tolerance, transistor sizing |
48 | Claudio Fabiano Motta Toledo, Paulo Morelato França, Kalianne Almeida Rosa |
Evaluating genetic algorithms with different population structures on a lot sizing and scheduling problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1777-1781, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-population, soft drink company, genetic algorithms, scheduling, lot sizing |
48 | Koustav Bhattacharya, Nagarajan Ranganathan |
A linear programming formulation for security-aware gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 273-278, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing |
48 | Yongjian Li, Jian Chen, Xiaoqiang Cai |
An integrated staff-sizing approach considering feasibility of scheduling decision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 155(1), pp. 361-390, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Staff-sizing, Staff flexibility, Multiple objective linear programming (MOLP), Scheduling, Planning |
48 | Fabrizio Marinelli 0001, Maria Elena Nenni, Antonio Sforza |
Capacitated lot sizing and scheduling with parallel machines and shared buffers: A case study in a packaging company. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 150(1), pp. 177-192, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Scheduling, Packaging, Lot sizing |
48 | Yongpei Guan, Shabbir Ahmed 0001, George L. Nemhauser, Andrew J. Miller |
A branch-and-cut algorithm for the stochastic uncapacitated lot-sizing problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 105(1), pp. 55-84, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stochastic Lot-Sizing, Multi-stage Stochastic Integer Programming, Polyhedral Study, Branch-and-Cut |
48 | Fernando G. Lobo, Cláudio F. Lima |
A review of adaptive population sizing schemes in genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO Workshops ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Workshop Proceedings, Washington DC, USA, June 25-26, 2005, pp. 228-234, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
genetic algorithms, population sizing, parameter setting |
48 | Hiran Tennakoon, Carl Sechen |
Efficient and accurate gate sizing with piecewise convex delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 807-812, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling |
48 | Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar |
Robust gate sizing by geometric programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 315-320, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
posynomial, uncertainty ellipsoid, optimization, gate sizing, geometric program |
48 | William Roshan Quadros, Kenji Shimada, Steven J. Owen |
Skeleton-based computational method for the generation of a 3D finite element mesh sizing function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eng. Comput. ![In: Eng. Comput. 20(3), pp. 249-264, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Finite element mesh sizing function, Skeleton, Octree, Medial axis transform |
48 | Ted J. Wasserman, Patrick Martin 0001, David B. Skillicorn, Haider Rizvi |
Developing a characterization of business intelligence workloads for sizing new database systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DOLAP ![In: DOLAP 2004, ACM Seventh International Workshop on Data Warehousing and OLAP, Washington, DC, USA, November 12-13, 2004, Proceedings, pp. 7-13, 2004, ACM, 1-58113-977-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clustering, workload characterization, business intelligence, sizing, capacity planning |
48 | David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer |
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 158-163, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dual threshold, sizing, dual supply voltage, simultaneous |
48 | Chang Woo Kang, Soroush Abbaspour, Massoud Pedram |
Buffer sizing for minimum energy-delay product by using an approximating polynomial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 112-115, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
short circuit energy, buffer sizing, polynomial approximation |
48 | M. Y. Y. Leung, John C. S. Lui, Leana Golubchik |
Use of Analytical Performance Models for System Sizing and Resource Allocation in Interactive Video-on-Demand Systems Employing Data Sharing Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 14(3), pp. 615-637, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
data sharing techniques, resource allocation, Video-on-demand, system sizing |
48 | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
CMOS Combinational Circuit Sizing by Stage-wise Tapering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 985-986, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
tapering, Transistor sizing, resynthesis |
45 | I-Min Liu, Adnan Aziz |
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 209-214, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
45 | Chris C. N. Chu, Martin D. F. Wong |
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 787-798, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Xiaochun Zhu, Bo Zhou 0010, Lu Chen |
Software testing sizing in incremental development: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESEM ![In: Proceedings of the Third International Symposium on Empirical Software Engineering and Measurement, ESEM 2009, October 15-16, 2009, Lake Buena Vista, Florida, USA, pp. 490-493, 2009, IEEE Computer Society, 978-1-4244-4842-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Joel Sommers, Paul Barford, Albert G. Greenberg, Walter Willinger |
An SLA perspective on the router buffer sizing problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 35(4), pp. 40-51, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2209-2222, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng |
An optimal algorithm for sizing sequential circuits for industrial library based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 148-151, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Xiaoqing Cheng |
Performance, Benchmarking and Sizing in Developing Highly Scalable Enterprise Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIPEW ![In: Performance Evaluation: Metrics, Models and Benchmarks, SPEC International Performance Evaluation Workshop, SIPEW 2008, Darmstadt, Germany, June 27-28, 2008. Proceedings, pp. 174-190, 2008, Springer, 978-3-540-69813-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh |
Soft Error-Aware Power Optimization Using Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 255-267, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Mei Wang, Yashar Ganjali |
The Effects of Fairness in Buffer Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2007. Ad Hoc and Sensor Networks, Wireless Networks, Next Generation Internet, 6th International IFIP-TC6 Networking Conference, Atlanta, GA, USA, May 14-18, 2007, Proceedings, pp. 867-878, 2007, Springer, 978-3-540-72605-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | DiaaEldin Khalil, Yehea I. Ismail |
Optimum sizing of power grids for IR drop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Fujita Tomohiro, Iiduka Osamu |
Analog circuit sizing with dynamic search window. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Preetam Patil, Varsha Apte |
Sizing of IEEE 802.11 wireless LANs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMASH ![In: Proceedings of the 3rd ACM International Workshop on Wireless Mobile Applications and Services on WLAN Hotspots, WMASH 2005, Cologne, Germany, September 2, 2005, pp. 96-99, 2005, ACM, 1-59593-143-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
simulations, wireless LANs, MAC, analytical models |
41 | Amogh Dhamdhere, Hao Jiang, Constantinos Dovrolis |
Buffer sizing for congested Internet links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 13-17 March 2005, Miami, FL, USA, pp. 1072-1083, 2005, IEEE, 0-7803-8968-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj |
Postroute gate sizing for crosstalk noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1670-1677, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Debjit Sinha, Hai Zhou 0001 |
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 14-19, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Te-Kai Liu, Hui Shen, Santhosh Kumaran |
A Capacity Sizing Tool for a Business Process Integration Middleware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CEC ![In: 2004 IEEE International Conference on E-Commerce Technology (CEC 2004), 6-9 July 2004, San Diego, CA, USA, pp. 195-202, 2004, IEEE Computer Society, 0-7695-2098-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Ted J. Wasserman, Patrick Martin 0001, Haider Rizvi |
Sizing DB2 UDB® servers for business intelligence workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 2004 conference of the Centre for Advanced Studies on Collaborative research, October 5-7, 2004, Markham, Ontario, Canada, pp. 135-149, 2004, IBM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
DB2 |
41 | Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis 0001, José Luís Almada Güntzel |
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 303-, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Ruibing Lu, Cheng-Kok Koh |
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 227-231, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | N. Ranganathan, Ashok K. Murugavel |
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 276-281, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj |
Post-Route Gate Sizing for Crosstalk Noise Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 171-176, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained transistor sizing and power optimization for dual Vst domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 532-541, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | James T. Kao, Anantha P. Chandrakasan, Dimitri A. Antoniadis |
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 409-414, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Claudio Fabiano Motta Toledo, Lucas de Oliveira, Renato Resende Ribeiro de Oliveira, Marluce Rodrigues Pereira |
Parallel genetic algorithm approaches applied to solve a synchronized and integrated lot sizing and scheduling problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 1148-1152, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multi-population, soft drink company, scheduling, parallel genetic algorithms, lot sizing |
40 | Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam |
Variation-aware multimetric optimization during gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 54:1-54:30, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise |
40 | Shoshana Anily, Michal Tzur, Laurence A. Wolsey |
Multi-item lot-sizing with joint set-up costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 119(1), pp. 79-94, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-item lot-sizing, Joint set-up cost, Extended formulation, Convex hull, Mixed integer programming |
40 | Yifang Liu, Jiang Hu |
A new algorithm for simultaneous gate sizing and threshold voltage assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 27-34, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
threshold voltage assignment, gate sizing |
40 | Ruichun Yang, Zhen Wang, Dachuan Xu |
A Cost-Sharing Method for the Soft-Capacitated Economic Lot-Sizing Game. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOA ![In: Combinatorial Optimization and Applications, Third International Conference, COCOA 2009, Huangshan, China, June 10-12, 2009. Proceedings, pp. 166-173, 2009, Springer, 978-3-642-02025-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Economic lot-sizing game, cost-sharing method, cross- monotonic, approximate cost recovery |
40 | Jason Cong, John Lee 0002, Lieven Vandenberghe |
Robust gate sizing via mean excess delay minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 10-14, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
robust gate sizing, process variation, geometric programming, conditional value-at-risk |
40 | Eleftherios I. Amoiralis, Pavlos S. Georgilakis, Marina A. Tsili, Antonios G. Kladas |
Ant Colony System-Based Algorithm for Optimal Multi-stage Planning of Distribution Transformer Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 12th International Conference, KES 2008, Zagreb, Croatia, September 3-5, 2008, Proceedings, Part II, pp. 9-17, 2008, Springer, 978-3-540-85564-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimal Transformer Sizing, Thermal Loading, Energy Loss Cost, Distribution Network Planning, Transformers, Ant Colony Optimization |
40 | Kumar Yelamarthi, Chien-In Henry Chen |
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 143-147, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders |
40 | Zhanyuan Jiang, Weiping Shi |
Circuit-wise buffer insertion and gate sizing algorithm with scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 708-713, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
buffer insertion, gate sizing, interconnect synthesis |
40 | Tian-Li Yu 0001, Kumara Sastry, David E. Goldberg, Martin Pelikan |
Population sizing for entropy-based model building in discrete estimation of distribution algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 601-608, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
genetic algorithms, entropy, mutual information, estimation of distribution algorithms, population sizing, model building |
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