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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 624 occurrences of 414 keywords
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Results
Found 1074 publication records. Showing 1074 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
58 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Peter Spindler, Ulf Schlichtmann, Frank M. Johannes |
Abacus: fast legalization of standard cell circuits with minimal movement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 47-53, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
minimal movement, standard cell circuits, dynamic programming, legalization |
52 | Hailong Jiao, Lan Chen |
Cellwise OPC Based on Reduced Standard Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 810-814, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cellwise OPC, reduced standard cell library, design for manufacturability |
48 | Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani |
Optimal algorithms for planar over-the-cell routing in the presence of obstacles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 3-7, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout |
46 | Jin-Tai Yan |
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 100-, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
43 | Jason Cong, Bryan Preas, C. L. Liu 0001 |
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 709-715, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
43 | Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw |
STEEL: a technique for stress-enhanced standard cell library design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 691-697, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Jin-Tai Yan |
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 128-131, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Rashed Zafar Bhatti, Monty Denneau, Jeff Draper |
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 198-203, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection |
42 | Hans T. Heineken, Wojciech Maly |
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 368-373, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield |
42 | John A. Chandy, Prithviraj Banerjee |
Parallel simulated annealing strategies for VLSI cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 37-42, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement |
41 | Andrea Ricci, Ilaria De Munari, Paolo Ciampolini |
An evolutionary approach for standard-cell library reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 305-310, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
compact library, mutation algorithm, standard-cell, digital design |
41 | Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl |
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(2), pp. 251-261, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
substitution box (S-box), inversion in the finite field GF($28$), standard cell implementation, Advanced Encryption Standard (AES), power consumption, silicon area, critical path delay |
39 | Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen |
Closed-loop adaptive voltage scaling controller for standard-cell ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 103-107, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter |
38 | Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger |
An ASIC Implementation of the AES SBoxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2002, The Cryptographer's Track at the RSA Conference, 2002, San Jose, CA, USA, February 18-22, 2002, Proceedings, pp. 67-78, 2002, Springer, 3-540-43224-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic |
37 | Seungwhun Paik, Youngsoo Shin |
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 600-605, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sleep vector, zigzag power gating, low power, leakage current, standard-cell |
37 | Faris H. Khundakjie, Patrick H. Madden, Nael B. Abu-Ghazaleh, Mehmet Can Yildiz |
Parallel Standard Cell Placement on a Cluster of Workstations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 8-11 October 2001, Newport Beach, CA, USA, pp. 85-94, 2001, IEEE Computer Society, 0-7695-1116-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Partitioning based Placement, Parallel VLSI Placement, Message Passing Applications, Standard Cell |
37 | Marc Renaudin, Pascal Vivet, Frédéric Robin |
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 22-31, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design |
37 | Jitendra Khare, Wojciech Maly, Nathan Tiday |
Fault characterization of standard cell libraries using inductive contamination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 405-413, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
surface contamination, fault characterization, standard cell libraries, inductive contamination analysis, contamination diagnosis, gate-level delay characterization, fault diagnosis, test generation, integrated circuit testing, cellular arrays, defect coverage |
37 | Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten |
Performance driven standard-cell placement using the genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 124-127, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement |
37 | H. J. Kappen, F. M. J. de Bont |
An efficient placement method for large standard-cell and sea-of-gates designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 312-316, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
optimization, Quadratic Assignment Problem, recursive partitioning, Standard Cell placement |
36 | Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri |
A design flow to optimize circuit delay by using standard cells and PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 217-222, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
PLA, standard cell |
35 | Uday Doddannagari, Shiyan Hu, Weiping Shi |
Fast characterization of parameterized cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 500-505, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Natarajan Viswanathan, Chris C. N. Chu |
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 26-33, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
net models, analytical placement, standard cell placement |
35 | Hart Anway, Greg Farnham, Rebecca Reid |
PLINT layout system for VLSI chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 449-452, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout |
33 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 276-285, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Mehrdad Najibi, Kamran Saleh, Hossein Pedram |
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 299-304, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, standard-cell layout, asynchronous circuits |
32 | Ke Cao, Sorin Dobre, Jiang Hu |
Standard cell characterization considering lithography induced variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 801-804, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
process CD, CAD, OPC, design flow, standard cell, RET |
32 | Hiroaki Yoshida, Kaushik De, Vamsi Boppana |
Accurate pre-layout estimation of standard cell characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 208-211, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cell characterization, transistor-level optimization, standard cell |
32 | Guoqiang Chen, Sachin S. Sapatnekar |
Partition-driven standard cell thermal placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 75-80, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI, partition, placement, temperature, standard cell, thermal model |
32 | Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel |
A single-rail re-implementation of a DCC error detector using a generic standard-cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 72-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits |
32 | Jason Cong, Bryan Preas, C. L. Liu 0001 |
Physical models and efficient algorithms for over-the-cell routing in standard cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 723-734, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
31 | D. V. Poornaiah, P. V. Ananda Mohan |
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 392-397, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron |
31 | Hsiao-Ping Tseng, Carl Sechen |
A gridless multi-layer router for standard cell circuits using CTM cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 319-326, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Michel Côté, Philippe Hurat |
Standard Cell Printability Grading and Hot Spot Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 264-269, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | David S. Kung 0001, Ruchir Puri |
Optimal P/N width ratio selection for standard cell libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 178-184, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 12-17, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Nikhil Jayakumar, Sunil P. Khatri |
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 128-133, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
standby current, leakage current, standard cells, MTCMOS |
30 | Anil Bahuman, Benjamin Bishop, Khaled Rasheed |
Automated Synthesis of Standard Cells using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 141-150, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standard cell design automation, cell synthesis, Genetic Algorithms, optimization, MAGIC, evolutionary approach |
28 | Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 983-986, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
28 | Hsiao-Ping Tseng, Carl Sechen |
A gridless multilayer router for standard cell circuits using CTMcells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10), pp. 1462-1479, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Antonio Blotti, Maurizio Castellucci, Roberto Saletti |
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 118-127, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Wern-Jieh Sun, Carl Sechen |
A parallel standard cell placement algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1342-1357, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Wern-Jieh Sun, Carl Sechen |
A loosely coupled parallel algorithm for standard cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 137-144, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Andrew A. Kennings, Kristofer Vorwerk |
Force-Directed Methods for Generic Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2076-2087, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz |
Cell replication and redundancy elimination during placement for cycle time optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 25-30, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Sung-Hsien Sun, Shie-Jue Lee |
A JPEG Chip for Image Compression and Decompression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(1), pp. 43-60, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip |
26 | Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin |
Double-via-driven standard cell library design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1212-1217, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 79-82, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai |
Benchmark Circuits Improve the Quality of a Standard Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 173-176, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Ralph-Michael Kling, Prithviraj Banerjee |
ESP: A New Standard Cell Placement Package Using Simulated Evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 60-66, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
26 | Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones |
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 327-332, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Juin-Yeu Lu, Shiu-Kai Chin |
Linking HOL to a VLSI CAD System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HUG ![In: Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings, pp. 199-212, 1993, Springer, 3-540-57826-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 654-659, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
25 | Lun Li, Mitchell A. Thornton, David W. Matula |
A digit serial algorithm for the integer power operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 302-307, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
power operation, standard cell implementation, exponential, discrete log |
25 | David G. Chinnery, Kurt Keutzer |
Closing the power gap between ASIC and custom: an ASIC perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 275-280, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
power, energy, custom, ASIC, comparison, standard cell |
25 | Ad M. G. Peeters, Kees van Berkel 0001 |
Single-rail handshake circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 53-62, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays |
25 | Kenneth Y. Yun, David L. Dill |
A high-performance asynchronous SCSI controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 44-49, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
peripheral interfaces, high-performance asynchronous SCSI controller, small computer systems interface, asynchronous pipeline, extended burst-mode machines, CMOS standard cell, data transfer throughput, distributed control scheme, extended burst-mode state machines, synchronisation, distributed control, CMOS integrated circuits, FIFO |
25 | Bret Stott, Dave Johnson 0003, Venkatesh Akella |
Asynchronous 2-D discrete cosine transform core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 380-385, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron |
25 | Mian Dong, Lin Zhong 0001 |
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 268-271, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | David M. Pawlowski, Liang Deng, Martin D. F. Wong |
Fast and Accurate OPC for Standard-Cell Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 7-12, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 776-781, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee |
An evaluation of parallel simulated annealing strategies with application to standard cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4), pp. 398-410, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
A power modeling and characterization method for the CMOS standard cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 400-404, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
power characterization, power consumption, power estimation |
25 | Jeff S. Sargent, Prithviraj Banerjee |
A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 590-593, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
24 | Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani |
High Yield Standard Cell Libraries: Optimization and Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 129-137, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Saurabh N. Adya, Igor L. Markov |
Combinatorial techniques for mixed-size placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 58-90, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, placement, floorplanning |
23 | Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici |
A Generic Standard Cell Design Methodology for Differential Circuit Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 843-848, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Jason G. Brown, R. D. (Shawn) Blanton |
Automated Standard Cell Library Analysis for Improved Defect Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 643-648, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
test generation, diagnosis, fault simulation, fault, defect |
23 | Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali |
Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo |
Physical design methodology of power gating circuits for standard-cell-based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 109-112, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, leakage current, power gating |
23 | Guofang Nan, Minqiang Li, Dan Lin 0002, Jisong Kou |
Adaptive Simulated Annealing for Standard Cell Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (3) ![In: Advances in Natural Computation, First International Conference, ICNC 2005, Changsha, China, August 27-29, 2005, Proceedings, Part III, pp. 943-947, 2005, Springer, 3-540-28320-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj |
Timing and area optimization for standard-cell VLSI circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 308-320, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | C. P. Hsu, B. N. Tien, K. Chow, R. A. Perry, J. Tang |
ALPS2: a standard cell layout system for double-layer metal technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 443-448, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Timing-Aware Power-Noise Reduction in Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 527-541, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Fadi J. Kurdahi, Alice C. Parker |
Techniques for area estimation of VLSI layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1), pp. 81-92, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj |
Optimizing Interconnect for Performance in Standard Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1280-1284, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Vinícius P. Correia, André Inácio Reis |
Advanced technology mapping for standard-cell generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 254-259, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cell library, library-free, logic synthesis, technology mapping, complex gates |
21 | Shin'ichi Wakabayashi, Nobuyuki Iwauchi, Hajime Kubota |
A hierarchical standard cell placement method based on a new cluster placement model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 273-278, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Optimal partitioners and end-case placers for standard-cell layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1304-1313, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Chingwei Yeh, Yin-Shuin Kang |
A simulated annealing based method supporting dual supply voltages in standard cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 310-313, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Paolo Ienne, Alexander Grießing |
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 396-401, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
21 | Khushro Shahookar, Pinaki Mazumder |
GASP: a Genetic Algorithm for Standard cell Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 660-664, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Mark Jones, Prithviraj Banerjee |
Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 807-813, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
21 | Amit Goel, Sarma B. K. Vrudhula |
Current source based standard cell model for accurate signal integrity and timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 574-579, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Stefan Tillich, Martin Feldhofer, Johann Großschädl |
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 457-466, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans |
A standard cell characterization flow for non-standard voltage supplies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-2736-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Chin-Chih Chang, Jason Cong |
Pseudopin assignment with crosstalk noise control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 598-611, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Stephen P. Kornachuk, Michael C. Smayling |
New strategies for gridded physical design for 32nm technologies and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 61-62, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm |
20 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 177-182, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
20 | Zhen Yang 0006, Anthony Vannelli, Shawki Areibi |
An ILP based hierarchical global routing approach for VLSI ASIC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optim. Lett. ![In: Optim. Lett. 1(3), pp. 281-297, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VLSI physical design, Standard cell global routing, Integer Linear Programming |
20 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Timing-driven row-based power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 104-109, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
20 | Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 501-504, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
layout, leakage power, insertion, standard-cell, sleep transistor |
20 | Tony F. Chan, Jason Cong, Kenton Sze |
Multilevel generalized force-directed method for circuit placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 185-192, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
force-directed method, multilevel, standard cell placement |
20 | Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind |
Architecting ASIC libraries and flows in nanometer era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 776-781, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nanometer design, libraries, standard cell |
20 | Venkat Thanvantri, Sartaj Sahni |
Optimal folding of standard and custom cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(1), pp. 123-143, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
custom cell folding, standard cell folding, layout area |
20 | James W. Watterson, Jill J. Hallenbeck |
Modulo 3 Residue Checker: New Results on Performance and Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(5), pp. 608-612, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage |
19 | Weiguang Sheng, Liyi Xiao, Zhigang Mao |
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 502-507, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
genetic algorithm, optimization, soft error, multi-objective |
19 | Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur |
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 667-672, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Shubhankar Basu, Priyanka Thakore, Ranga Vemuri |
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 814-820, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
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