Search results for "standard-cell"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
58	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes	Abacus: fast legalization of standard cell circuits with minimal movement.	ISPD	2008	DBLP DOI BibTeX RDF	minimal movement, standard cell circuits, dynamic programming, legalization
52	Hailong Jiao, Lan Chen	Cellwise OPC Based on Reduced Standard Cell Library.	ISQED	2008	DBLP DOI BibTeX RDF	cellwise OPC, reduced standard cell library, design for manufacturability
48	Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani	Optimal algorithms for planar over-the-cell routing in the presence of obstacles.	VLSI Design	1995	DBLP DOI BibTeX RDF	planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout
46	Jin-Tai Yan	An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
43	Jason Cong, Bryan Preas, C. L. Liu 0001	General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.	DAC	1990	DBLP DOI BibTeX RDF
43	Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw	STEEL: a technique for stress-enhanced standard cell library design.	ICCAD	2008	DBLP DOI BibTeX RDF
43	Jin-Tai Yan	An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF
42	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
42	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
42	John A. Chandy, Prithviraj Banerjee	Parallel simulated annealing strategies for VLSI cell placement.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement
41	Andrea Ricci, Ilaria De Munari, Paolo Ciampolini	An evolutionary approach for standard-cell library reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	compact library, mutation algorithm, standard-cell, digital design
41	Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl	Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	substitution box (S-box), inversion in the finite field GF($28$), standard cell implementation, Advanced Encryption Standard (AES), power consumption, silicon area, critical path delay
39	Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen	Closed-loop adaptive voltage scaling controller for standard-cell ASICs.	ISLPED	2002	DBLP DOI BibTeX RDF	delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter
38	Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger	An ASIC Implementation of the AES SBoxes.	CT-RSA	2002	DBLP DOI BibTeX RDF	standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
37	Seungwhun Paik, Youngsoo Shin	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.	DAC	2008	DBLP DOI BibTeX RDF	sleep vector, zigzag power gating, low power, leakage current, standard-cell
37	Faris H. Khundakjie, Patrick H. Madden, Nael B. Abu-Ghazaleh, Mehmet Can Yildiz	Parallel Standard Cell Placement on a Cluster of Workstations.	CLUSTER	2001	DBLP DOI BibTeX RDF	Partitioning based Placement, Parallel VLSI Placement, Message Passing Applications, Standard Cell
37	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
37	Jitendra Khare, Wojciech Maly, Nathan Tiday	Fault characterization of standard cell libraries using inductive contamination.	VTS	1996	DBLP DOI BibTeX RDF	surface contamination, fault characterization, standard cell libraries, inductive contamination analysis, contamination diagnosis, gate-level delay characterization, fault diagnosis, test generation, integrated circuit testing, cellular arrays, defect coverage
37	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
37	H. J. Kappen, F. M. J. de Bont	An efficient placement method for large standard-cell and sea-of-gates designs.	EURO-DAC	1990	DBLP DOI BibTeX RDF	optimization, Quadratic Assignment Problem, recursive partitioning, Standard Cell placement
36	Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri	A design flow to optimize circuit delay by using standard cells and PLAs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	PLA, standard cell
35	Uday Doddannagari, Shiyan Hu, Weiping Shi	Fast characterization of parameterized cell library.	ISQED	2009	DBLP DOI BibTeX RDF
35	Natarajan Viswanathan, Chris C. N. Chu	FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model.	ISPD	2004	DBLP DOI BibTeX RDF	net models, analytical placement, standard cell placement
35	Hart Anway, Greg Farnham, Rebecca Reid	PLINT layout system for VLSI chips.	DAC	1985	DBLP DOI BibTeX RDF	IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout
33	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
33	Mehrdad Najibi, Kamran Saleh, Hossein Pedram	Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	quasi-delay insensitive, standard-cell layout, asynchronous circuits
32	Ke Cao, Sorin Dobre, Jiang Hu	Standard cell characterization considering lithography induced variations.	DAC	2006	DBLP DOI BibTeX RDF	process CD, CAD, OPC, design flow, standard cell, RET
32	Hiroaki Yoshida, Kaushik De, Vamsi Boppana	Accurate pre-layout estimation of standard cell characteristics.	DAC	2004	DBLP DOI BibTeX RDF	cell characterization, transistor-level optimization, standard cell
32	Guoqiang Chen, Sachin S. Sapatnekar	Partition-driven standard cell thermal placement.	ISPD	2003	DBLP DOI BibTeX RDF	VLSI, partition, placement, temperature, standard cell, thermal model
32	Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel	A single-rail re-implementation of a DCC error detector using a generic standard-cell library.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits
32	Jason Cong, Bryan Preas, C. L. Liu 0001	Physical models and efficient algorithms for over-the-cell routing in standard cell design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
31	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
31	Hsiao-Ping Tseng, Carl Sechen	A gridless multi-layer router for standard cell circuits using CTM cells.	ED&TC	1997	DBLP DOI BibTeX RDF
31	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
31	David S. Kung 0001, Ruchir Puri	Optimal P/N width ratio selection for standard cell libraries.	ICCAD	1999	DBLP DOI BibTeX RDF
31	Saurabh N. Adya, Igor L. Markov	Consistent placement of macro-blocks using floorplanning and standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF
30	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
30	Anil Bahuman, Benjamin Bishop, Khaled Rasheed	Automated Synthesis of Standard Cells using Genetic Algorithms.	ISVLSI	2002	DBLP DOI BibTeX RDF	standard cell design automation, cell synthesis, Genetic Algorithms, optimization, MAGIC, evolutionary approach
28	Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
28	Hsiao-Ping Tseng, Carl Sechen	A gridless multilayer router for standard cell circuits using CTMcells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
28	Antonio Blotti, Maurizio Castellucci, Roberto Saletti	Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.	PATMOS	2002	DBLP DOI BibTeX RDF
28	Wern-Jieh Sun, Carl Sechen	A parallel standard cell placement algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
28	Wern-Jieh Sun, Carl Sechen	A loosely coupled parallel algorithm for standard cell placement.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Andrew A. Kennings, Kristofer Vorwerk	Force-Directed Methods for Generic Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz	Cell replication and redundancy elimination during placement for cycle time optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
26	Sung-Hsien Sun, Shie-Jue Lee	A JPEG Chip for Image Compression and Decompression.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip
26	Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin	Double-via-driven standard cell library design.	DATE	2007	DBLP DOI BibTeX RDF
26	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
26	Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai	Benchmark Circuits Improve the Quality of a Standard Cell Library.	ASP-DAC	1999	DBLP DOI BibTeX RDF
26	Ralph-Michael Kling, Prithviraj Banerjee	ESP: A New Standard Cell Placement Package Using Simulated Evolution.	DAC	1987	DBLP DOI BibTeX RDF
26	Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones	CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.	DAC	1997	DBLP DOI BibTeX RDF
25	Juin-Yeu Lu, Shiu-Kai Chin	Linking HOL to a VLSI CAD System.	HUG	1993	DBLP DOI BibTeX RDF
25	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
25	Lun Li, Mitchell A. Thornton, David W. Matula	A digit serial algorithm for the integer power operation.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power operation, standard cell implementation, exponential, discrete log
25	David G. Chinnery, Kurt Keutzer	Closing the power gap between ASIC and custom: an ASIC perspective.	DAC	2005	DBLP DOI BibTeX RDF	power, energy, custom, ASIC, comparison, standard cell
25	Ad M. G. Peeters, Kees van Berkel 0001	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
25	Kenneth Y. Yun, David L. Dill	A high-performance asynchronous SCSI controller.	ICCD	1995	DBLP DOI BibTeX RDF	peripheral interfaces, high-performance asynchronous SCSI controller, small computer systems interface, asynchronous pipeline, extended burst-mode machines, CMOS standard cell, data transfer throughput, distributed control scheme, extended burst-mode state machines, synchronisation, distributed control, CMOS integrated circuits, FIFO
25	Bret Stott, Dave Johnson 0003, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor.	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
25	Mian Dong, Lin Zhong 0001	Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration.	DATE	2008	DBLP DOI BibTeX RDF
25	David M. Pawlowski, Liang Deng, Martin D. F. Wong	Fast and Accurate OPC for Standard-Cell Layouts.	ASP-DAC	2007	DBLP DOI BibTeX RDF
25	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.	ISQED	2007	DBLP DOI BibTeX RDF
25	John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee	An evaluation of parallel simulated annealing strategies with application to standard cell placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
25	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for the CMOS standard cell library.	ICCAD	1996	DBLP DOI BibTeX RDF	power characterization, power consumption, power estimation
25	Jeff S. Sargent, Prithviraj Banerjee	A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control.	DAC	1989	DBLP DOI BibTeX RDF
24	Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani	High Yield Standard Cell Libraries: Optimization and Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF
23	Saurabh N. Adya, Igor L. Markov	Combinatorial techniques for mixed-size placement.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning
23	Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici	A Generic Standard Cell Design Methodology for Differential Circuit Styles.	DATE	2008	DBLP DOI BibTeX RDF
23	Jason G. Brown, R. D. (Shawn) Blanton	Automated Standard Cell Library Analysis for Improved Defect Modeling.	ISQED	2008	DBLP DOI BibTeX RDF	test generation, diagnosis, fault simulation, fault, defect
23	Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali	Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo	Physical design methodology of power gating circuits for standard-cell-based design.	DAC	2006	DBLP DOI BibTeX RDF	low power, leakage current, power gating
23	Guofang Nan, Minqiang Li, Dan Lin 0002, Jisong Kou	Adaptive Simulated Annealing for Standard Cell Placement.	ICNC (3)	2005	DBLP DOI BibTeX RDF
23	Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj	Timing and area optimization for standard-cell VLSI circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
23	C. P. Hsu, B. N. Tien, K. Chow, R. A. Perry, J. Tang	ALPS2: a standard cell layout system for double-layer metal technology.	DAC	1985	DBLP DOI BibTeX RDF
22	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Timing-Aware Power-Noise Reduction in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
22	Fadi J. Kurdahi, Alice C. Parker	Techniques for area estimation of VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
21	Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj	Optimizing Interconnect for Performance in Standard Cell Library.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Vinícius P. Correia, André Inácio Reis	Advanced technology mapping for standard-cell generators.	SBCCI	2004	DBLP DOI BibTeX RDF	cell library, library-free, logic synthesis, technology mapping, complex gates
21	Shin'ichi Wakabayashi, Nobuyuki Iwauchi, Hajime Kubota	A hierarchical standard cell placement method based on a new cluster placement model.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
21	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Optimal partitioners and end-case placers for standard-cell layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Chingwei Yeh, Yin-Shuin Kang	A simulated annealing based method supporting dual supply voltages in standard cell placement.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Paolo Ienne, Alexander Grießing	Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
21	Khushro Shahookar, Pinaki Mazumder	GASP: a Genetic Algorithm for Standard cell Placement.	EURO-DAC	1990	DBLP DOI BibTeX RDF
21	Mark Jones, Prithviraj Banerjee	Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube.	DAC	1987	DBLP DOI BibTeX RDF
21	Amit Goel, Sarma B. K. Vrudhula	Current source based standard cell model for accurate signal integrity and timing analysis.	DATE	2008	DBLP DOI BibTeX RDF
21	Stefan Tillich, Martin Feldhofer, Johann Großschädl	Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box.	SAMOS	2006	DBLP DOI BibTeX RDF
20	Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans	A standard cell characterization flow for non-standard voltage supplies.	SBCCI	2016	DBLP DOI BibTeX RDF
20	Chin-Chih Chang, Jason Cong	Pseudopin assignment with crosstalk noise control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
20	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
20	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
20	Zhen Yang 0006, Anthony Vannelli, Shawki Areibi	An ILP based hierarchical global routing approach for VLSI ASIC design.	Optim. Lett.	2007	DBLP DOI BibTeX RDF	VLSI physical design, Standard cell global routing, Integer Linear Programming
20	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
20	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
20	Tony F. Chan, Jason Cong, Kenton Sze	Multilevel generalized force-directed method for circuit placement.	ISPD	2005	DBLP DOI BibTeX RDF	force-directed method, multilevel, standard cell placement
20	Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind	Architecting ASIC libraries and flows in nanometer era.	DAC	2003	DBLP DOI BibTeX RDF	nanometer design, libraries, standard cell
20	Venkat Thanvantri, Sartaj Sahni	Optimal folding of standard and custom cells.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	custom cell folding, standard cell folding, layout area
20	James W. Watterson, Jill J. Hallenbeck	Modulo 3 Residue Checker: New Results on Performance and Cost.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage
19	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
19	Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur	Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.	ISQED	2007	DBLP DOI BibTeX RDF