Search results for "standard-cells"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
51	Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz	CMOS Standard Cells Characterization for Defect Based Testing.	DFT	2001	DBLP DOI BibTeX RDF	standard cells characterization, VLSI circuits, critical area, spot defects, defect based testing
48	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
46	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
46	Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal	Metal filling impact on standard cells: definition of the metal fill corner concept.	SBCCI	2008	DBLP DOI BibTeX RDF	metal filling, modelization, interconnect, design of experiment, dispersion, standard cells, capacitance, corners, ring oscillators
45	Ravi Arora, Sachin Shrivastava	Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint!	APCCAS	2006	DBLP DOI BibTeX RDF
42	Alfred E. Dunlop	Will Cell Generation Displace Standard Cells?	DAC	1988	DBLP BibTeX RDF
42	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes	Abacus: fast legalization of standard cell circuits with minimal movement.	ISPD	2008	DBLP DOI BibTeX RDF	minimal movement, standard cell circuits, dynamic programming, legalization
40	Jens Vygen	Algorithms for Detailed Placement of Standard Cells.	DATE	1998	DBLP DOI BibTeX RDF	combinatorial optimization, standard cells, Detailed placement
34	Bingzhong Guan, Carl Sechen	Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc.	ICCD	1996	DBLP DOI BibTeX RDF
30	Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton	Architectures and algorithms for synthesizable embedded programmable logic cores.	FPGA	2003	DBLP DOI BibTeX RDF	programmable logic cores, FPGA, standard cells, system-on-chip design
30	Glenn Holt, Akhilesh Tyagi	EPNR: an energy-efficient automated layout synthesis package.	ICCD	1995	DBLP DOI BibTeX RDF	EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing
30	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
30	Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel	High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.	ASYNC	2004	DBLP DOI BibTeX RDF
29	Mely Chen Chi	An Automatic Rectilinear Partitioning Procedure for Standard Cells.	DAC	1987	DBLP DOI BibTeX RDF
27	Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw	On the decreasing significance of large standard cells in technology mapping.	ICCAD	2008	DBLP DOI BibTeX RDF
27	Jonathan Rose	LocusRoute: A Parallel Global Router for Standard Cells.	DAC	1988	DBLP BibTeX RDF
26	Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang	An Automatic Layout Generator for I/O Cells.	IWSOC	2005	DBLP DOI BibTeX RDF
26	Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri	A design flow to optimize circuit delay by using standard cells and PLAs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	PLA, standard cell
25	Dan Hillman	Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.	DATE	2004	DBLP DOI BibTeX RDF
25	Hans-Rudolf Heeb, Wolfgang Fichtner	A module generator based on the PQ-tree algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	Seyed-Abdollah Aftabjahani, Linda S. Milor	Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis
24	Shawn Phillips, Scott Hauck	Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip.	FPGA	2002	DBLP DOI BibTeX RDF	automatic layout generation, domain-specific FPGA, system-on a-chip, standard cells
24	Rob Roy, Debashis Bhattacharya, Vamsi Boppana	Transistor-Level Optimization of Digital Designs with Flex Cells.	Computer	2005	DBLP DOI BibTeX RDF	ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design
24	Faizal Arya Samman, Rhiza S. Sadjad	Analog MOS circuit design for reconfigurable fuzzy logic controller.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
23	Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz	CMOS Standard Cells Characterization for IDDQ Testing.	DFT	2002	DBLP DOI BibTeX RDF
23	Jonathan Rose	Parallel global routing for standard cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
23	Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones	CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.	DAC	1997	DBLP DOI BibTeX RDF
22	Saurabh N. Adya, Igor L. Markov	Combinatorial techniques for mixed-size placement.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning
21	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
21	Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye	Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera	Timing- / Power-Optimization for Digital Logic Based on Standard Cells.	DSD	2007	DBLP DOI BibTeX RDF
21	Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson	Yield Enhancement Methodology for CMOS Standard Cells.	ISQED	2006	DBLP DOI BibTeX RDF
21	Bruce F. Cockburn, Keith Boyle	Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells.	CCECE	2006	DBLP DOI BibTeX RDF
21	Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa	A routing procedure for mixed array of custom macros and standard cells.	DAC	1985	DBLP DOI BibTeX RDF
21	Yongchan Ban, Savithri Sundareswaran, David Z. Pan	Total sensitivity based dfm optimization of standard library cells.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, VLSI, sensitivity, DFM, lithography
20	Bo Hu 0006, Malgorzata Marek-Sadowska	Multilevel expansion-based VLSI placement with blockages.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Dawei Liu, Qiang Zhou 0001, Jinian Bian, Yici Cai, Xianlong Hong	Cell shifting aware of wirelength and overlap.	ISQED	2009	DBLP DOI BibTeX RDF
18	Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima	A Functional Unit with Small Variety of Highly Reliable Cells.	PRDC	2008	DBLP DOI BibTeX RDF
18	Hwan Gue Cho, C. M. Kyung	A heuristic standard cell placement algorithm using constrained multistage graph model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
17	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace: an analytical placer for mixed-mode designs.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-mode placement, floorplanning, analytical placement
17	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
16	Saurabh N. Adya, Igor L. Markov	Consistent placement of macro-blocks using floorplanning and standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF
16	Daijoon Hyun, Wonjae Lee, JinHyeong Park, Youngsoo Shin	Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel 0001, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel	Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
16	Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez 0002, Rafael Castro-López, Elisenda Roca, Hussam Amrouch	Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths.	IRPS	2023	DBLP DOI BibTeX RDF
16	Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim	Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility.	DATE	2023	DBLP DOI BibTeX RDF
16	Kihwang Son, Seulki Park, Kyunghoon Jung, Jun-Gyu Kim, Younggun Ko, Keonyong Cheon, Changkeun Yoon, Jiho Kim, Jaehun Jeong, Taehun Myung, Changmin Hong, Weonwi Jang, Min-Chul Sun, Sungil Jo, Ju-Youn Kim, Byungmoo Song, Yuri Yasuda-Masuoka, Ja-Hum Ku, Gitae Jeong	Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
16	Pei-Sheng Lu, Rung-Bin Lin	Improving Pin Accessibility of Standard Cells under Power/Ground Stripes.	NEWCAS	2023	DBLP DOI BibTeX RDF
16	Christian Lanius, Jie Lou, Johnson Loh, Tobias Gemmeke	Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM.	ISLPED	2023	DBLP DOI BibTeX RDF
16	Shubham Yadav, André B. J. Kokkeler, Mark S. Oude Alink	Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology.	ISCAS	2023	DBLP DOI BibTeX RDF
16	Hwapyong Kim, Taewhan Kim	Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
16	Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula	A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
16	Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula	A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells.	CoRR	2022	DBLP DOI BibTeX RDF
16	Suman Bhowmik	Power reduction of standard cells by controlling leakage current.	Int. J. Comput. Aided Eng. Technol.	2022	DBLP DOI BibTeX RDF
16	Jaehoon Jeong, JongHyun Ko, Taigon Song	A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node.	ISLPED	2022	DBLP DOI BibTeX RDF
16	Doyeon Won, Taewhan Kim	Improving Pin Accessibility of Standard Cells Through Fin Depopulation.	ISCAS	2022	DBLP DOI BibTeX RDF
16	Kyungjoon Chang, Taewhan Kim	Analysis of Impacting Multi-stack Standard Cells on Chip Implementation.	ISOCC	2022	DBLP DOI BibTeX RDF
16	Furkan Eris	Leveraging machine learning for managing prefetchers and designing secure standard cells		2022	RDF
16	Zhixuan Wang, Le Ye, Qianqian Huang, Kaixuan Du, Zhichao Tan, Yangyuan Wang, Ru Huang	Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
16	Linan Cao, Simon J. Bale, Martin A. Trefzer	Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
16	Linan Cao, Simon J. Bale, Martin A. Trefzer	Multi-objective Digital Design Optimisation via Improved Drive Granularity Standard Cells.	CoRR	2021	DBLP BibTeX RDF
16	Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.	CoRR	2021	DBLP BibTeX RDF
16	Aaron C.-W. Liang, Hsuan-Ming Huang, Charles H.-P. Wen	Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes.	DATE	2021	DBLP DOI BibTeX RDF
16	Prasenjit Saha, Salman Ahmed, Hema Sai Kalluru, Zia Abbas	Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence.	ISCAS	2021	DBLP DOI BibTeX RDF
16	Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang	A fully asynchronous QDI mesh router based on 28nm standard cells.	ASICON	2021	DBLP DOI BibTeX RDF
16	Jinliang Han, Yongzhong Wen, Yuejun Zhang, Pengjun Wang, Huihong Zhang	A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger.	ASICON	2021	DBLP DOI BibTeX RDF
16	Jay Pathak, Anand D. Darji	Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications.	VDAT	2021	DBLP DOI BibTeX RDF
16	Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar 0001	DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.	DATE	2020	DBLP DOI BibTeX RDF
16	Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.	ICCD	2020	DBLP DOI BibTeX RDF
16	Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.	Integr.	2019	DBLP DOI BibTeX RDF
16	M. Suresh, A. K. Panda, J. Sudhakar	Low power aware standard cells using dual rail multi threshold null convention logic methodology.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
16	Nikolay Ryzhenko, Steven M. Burns, Anton Sorokin, Mikhail Talalay	Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints.	ISPD	2019	DBLP DOI BibTeX RDF
16	Anton Sorokin, Nikolay Ryzhenko	SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
16	Rung-Bin Lin, Yu-Xiang Chiang	Impact of Double-Row Height Standard Cells on Placement and Routing.	ISQED	2019	DBLP DOI BibTeX RDF
16	Jun Liu 0038, Beomsoo Park, Marino De Jesus Guzman, Ahmed Fahmy, Taewook Kim, Nima Maghari	A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
16	Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui	Design of Low-Power High-Performance FinFET Standard Cells.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
16	I-Lun Tseng, Yongfu Li 0003, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong	An Automated System for Checking Lithography Friendliness of Standard Cells.	CoRR	2018	DBLP BibTeX RDF
16	Yongfu Li 0003, Chin Hui Lee, Wan Chia Ang, Kok Peng Chua, Yoong Seang Jonathan Ong, Chiu Wing Colin Hui	Constraining the Synopsys Pin Access Checker Utility for Improved Standard Cells Library Verification Flow.	CoRR	2018	DBLP BibTeX RDF
16	Yongfu Li 0003, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong	Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin	Designing and Benchmarking of Double-Row Height Standard Cells.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	A. V. Korshunov, S. A. Ilin	The Technique of Fast Power Analysis for FinFET Standard Cells.	EWDTS	2018	DBLP DOI BibTeX RDF
16	Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii	Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.	IRPS	2018	DBLP DOI BibTeX RDF
16	Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich, Stefan Heinen	AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cells.	DATE	2018	DBLP DOI BibTeX RDF
16	Longyang Lin, Saurabh Jain, Massimo Alioto	A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing.	ISSCC	2018	DBLP DOI BibTeX RDF
16	I-Lun Tseng, Yongfu Li 0003, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong	An Automated System for Checking Lithography Friendliness of Standard Cells.	APCCAS	2018	DBLP DOI BibTeX RDF
16	Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint	Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin	On Benchmarking Pin Access for Nanotechnology Standard Cells.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan	An effective legalization algorithm for mixed-cell-height standard cells.	ASP-DAC	2017	DBLP DOI BibTeX RDF
16	Daohang Shi, Azadeh Davoodi	Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells.	ISPD	2017	DBLP DOI BibTeX RDF
16	Ahmed Fahmy, Jun Liu 0038, Pavan Terdal, Ryan Madler, Rizwan Bashirullah, Nima Maghari	A synthesizable time-based LDO using digital standard cells and analog pass transistor.	ESSCIRC	2017	DBLP DOI BibTeX RDF
16	Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu	Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
16	Gang Wu 0002, Chris Chu	Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan	Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Meghna G. Mankalale, Sachin S. Sapatnekar	Optimized Standard Cells for All-Spin Logic.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann	FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
16	Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.	PATMOS	2016	DBLP DOI BibTeX RDF
16	Sergey Bykov, Nikolai Ryzhenko, Anton Sorokin	Automated solution for preventing design rules violations at abutment stage for standard cells synthesis flow.	EWDTS	2016	DBLP DOI BibTeX RDF
16	Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin	Practical ILP-based routing of standard cells.	DATE	2016	DBLP BibTeX RDF