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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 191 occurrences of 138 keywords
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Results
Found 321 publication records. Showing 321 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Nikhil Jayakumar, Sunil P. Khatri |
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 128-133, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
standby current, leakage current, standard cells, MTCMOS |
51 | Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz |
CMOS Standard Cells Characterization for Defect Based Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 384-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
standard cells characterization, VLSI circuits, critical area, spot defects, defect based testing |
48 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Shubhankar Basu, Ranga Vemuri |
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 291-298, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal |
Metal filling impact on standard cells: definition of the metal fill corner concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 16-21, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
metal filling, modelization, interconnect, design of experiment, dispersion, standard cells, capacitance, corners, ring oscillators |
45 | Ravi Arora, Sachin Shrivastava |
Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint! ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 805-807, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Alfred E. Dunlop |
Will Cell Generation Displace Standard Cells? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 528, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
42 | Peter Spindler, Ulf Schlichtmann, Frank M. Johannes |
Abacus: fast legalization of standard cell circuits with minimal movement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 47-53, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
minimal movement, standard cell circuits, dynamic programming, legalization |
40 | Jens Vygen |
Algorithms for Detailed Placement of Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 321-324, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
combinatorial optimization, standard cells, Detailed placement |
34 | Bingzhong Guan, Carl Sechen |
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 378-383, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
Architectures and algorithms for synthesizable embedded programmable logic cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 3-11, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
programmable logic cores, FPGA, standard cells, system-on-chip design |
30 | Glenn Holt, Akhilesh Tyagi |
EPNR: an energy-efficient automated layout synthesis package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing |
30 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 42-58, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
30 | Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel |
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 95-105, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Mely Chen Chi |
An Automatic Rectilinear Partitioning Procedure for Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 50-55, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
27 | Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw |
On the decreasing significance of large standard cells in technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 116-121, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Jonathan Rose |
LocusRoute: A Parallel Global Router for Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 189-195, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
26 | Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang |
An Automatic Layout Generator for I/O Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 295-300, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri |
A design flow to optimize circuit delay by using standard cells and PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 217-222, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
PLA, standard cell |
25 | Dan Hillman |
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 240-246, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Hans-Rudolf Heeb, Wolfgang Fichtner |
A module generator based on the PQ-tree algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7), pp. 876-884, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 148-151, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis |
24 | Shawn Phillips, Scott Hauck |
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 165-173, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
automatic layout generation, domain-specific FPGA, system-on a-chip, standard cells |
24 | Rob Roy, Debashis Bhattacharya, Vamsi Boppana |
Transistor-Level Optimization of Digital Designs with Flex Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(2), pp. 53-61, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design |
24 | Faizal Arya Samman, Rhiza S. Sadjad |
Analog MOS circuit design for reconfigurable fuzzy logic controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 151-156, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz |
CMOS Standard Cells Characterization for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 390-398, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Jonathan Rose |
Parallel global routing for standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10), pp. 1085-1095, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones |
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 327-332, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Saurabh N. Adya, Igor L. Markov |
Combinatorial techniques for mixed-size placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 58-90, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, placement, floorplanning |
21 | Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera |
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 195-200, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye |
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 107-108, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera |
Timing- / Power-Optimization for Digital Logic Based on Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 303-306, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson |
Yield Enhancement Methodology for CMOS Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 497-502, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Bruce F. Cockburn, Keith Boyle |
Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1214-1217, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa |
A routing procedure for mixed array of custom macros and standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 503-508, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
21 | Yongchan Ban, Savithri Sundareswaran, David Z. Pan |
Total sensitivity based dfm optimization of standard library cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 113-120, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, VLSI, sensitivity, DFM, lithography |
20 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Multilevel expansion-based VLSI placement with blockages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 558-564, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Dawei Liu, Qiang Zhou 0001, Jinian Bian, Yici Cai, Xianlong Hong |
Cell shifting aware of wirelength and overlap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 506-510, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima |
A Functional Unit with Small Variety of Highly Reliable Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 353-354, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Hwan Gue Cho, C. M. Kyung |
A heuristic standard cell placement algorithm using constrained multistage graph model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11), pp. 1205-1214, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
18 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 276-285, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace: an analytical placer for mixed-mode designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 221-223, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
mixed-mode placement, floorplanning, analytical placement |
17 | Michel Côté, Philippe Hurat |
Standard Cell Printability Grading and Hot Spot Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 264-269, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 12-17, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Daijoon Hyun, Wonjae Lee, JinHyeong Park, Youngsoo Shin |
Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2211-2215, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel 0001, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel |
Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 920, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
16 | Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez 0002, Rafael Castro-López, Elisenda Roca, Hussam Amrouch |
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim |
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kihwang Son, Seulki Park, Kyunghoon Jung, Jun-Gyu Kim, Younggun Ko, Keonyong Cheon, Changkeun Yoon, Jiho Kim, Jaehun Jeong, Taehun Myung, Changmin Hong, Weonwi Jang, Min-Chul Sun, Sungil Jo, Ju-Youn Kim, Byungmoo Song, Yuri Yasuda-Masuoka, Ja-Hum Ku, Gitae Jeong |
Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Pei-Sheng Lu, Rung-Bin Lin |
Improving Pin Accessibility of Standard Cells under Power/Ground Stripes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Christian Lanius, Jie Lou, Johnson Loh, Tobias Gemmeke |
Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1175-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shubham Yadav, André B. J. Kokkeler, Mark S. Oude Alink |
Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hwapyong Kim, Taewhan Kim |
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023, pp. 321-326, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula |
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(7), pp. 2968-2981, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula |
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.08070, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Suman Bhowmik |
Power reduction of standard cells by controlling leakage current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Aided Eng. Technol. ![In: Int. J. Comput. Aided Eng. Technol. 16(4), pp. 478-487, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jaehoon Jeong, JongHyun Ko, Taigon Song |
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022, pp. 16:1-16:6, 2022, ACM, 978-1-4503-9354-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Doyeon Won, Taewhan Kim |
Improving Pin Accessibility of Standard Cells Through Fin Depopulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2621-2622, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Kyungjoon Chang, Taewhan Kim |
Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 119-120, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Furkan Eris |
Leveraging machine learning for managing prefetchers and designing secure standard cells ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
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16 | Zhixuan Wang, Le Ye, Qianqian Huang, Kaixuan Du, Zhichao Tan, Yangyuan Wang, Ru Huang |
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(3), pp. 1160-1170, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Linan Cao, Simon J. Bale, Martin A. Trefzer |
Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(11), pp. 4660-4671, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Linan Cao, Simon J. Bale, Martin A. Trefzer |
Multi-objective Digital Design Optimisation via Improved Drive Granularity Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.11248, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
16 | Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula |
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.01699, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
16 | Aaron C.-W. Liang, Hsuan-Ming Huang, Charles H.-P. Wen |
Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1829-1834, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Prasenjit Saha, Salman Ahmed, Hema Sai Kalluru, Zia Abbas |
Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang |
A fully asynchronous QDI mesh router based on 28nm standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Jinliang Han, Yongzhong Wen, Yuejun Zhang, Pengjun Wang, Huihong Zhang |
A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Jay Pathak, Anand D. Darji |
Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar 0001 |
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 674-677, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula |
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020, pp. 433-440, 2020, IEEE, 978-1-7281-9710-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 65, pp. 201-210, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | M. Suresh, A. K. Panda, J. Sudhakar |
Low power aware standard cells using dual rail multi threshold null convention logic methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 68, pp. 28-33, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Nikolay Ryzhenko, Steven M. Burns, Anton Sorokin, Mikhail Talalay |
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2019 International Symposium on Physical Design, ISPD 2019, San Francisco, CA, USA, April 14-17, 2019, pp. 41-47, 2019, ACM, 978-1-4503-6253-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Anton Sorokin, Nikolay Ryzhenko |
SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 159-164, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Rung-Bin Lin, Yu-Xiang Chiang |
Impact of Double-Row Height Standard Cells on Placement and Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 317-322, 2019, IEEE, 978-1-7281-0392-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Jun Liu 0038, Beomsoo Park, Marino De Jesus Guzman, Ahmed Fahmy, Taewook Kim, Nima Maghari |
A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(6), pp. 1126-1138, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui |
Design of Low-Power High-Performance FinFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 37(5), pp. 1789-1806, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | I-Lun Tseng, Yongfu Li 0003, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong |
An Automated System for Checking Lithography Friendliness of Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1810.01446, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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16 | Yongfu Li 0003, Chin Hui Lee, Wan Chia Ang, Kok Peng Chua, Yoong Seang Jonathan Ong, Chiu Wing Colin Hui |
Constraining the Synopsys Pin Access Checker Utility for Improved Standard Cells Library Verification Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.10012, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Yongfu Li 0003, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong |
Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 417-422, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin |
Designing and Benchmarking of Double-Row Height Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 64-69, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | A. V. Korshunov, S. A. Ilin |
The Technique of Fast Power Analysis for FinFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2018 IEEE East-West Design & Test Symposium, EWDTS 2018, Kazan, Russia, September 14-17, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-5710-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii |
Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 1, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich, Stefan Heinen |
AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 633-636, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Longyang Lin, Saurabh Jain, Massimo Alioto |
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 44-46, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | I-Lun Tseng, Yongfu Li 0003, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong |
An Automated System for Checking Lithography Friendliness of Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 261-265, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint |
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 539-544, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin |
On Benchmarking Pin Access for Nanotechnology Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 237-242, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan |
An effective legalization algorithm for mixed-cell-height standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 450-455, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Daohang Shi, Azadeh Davoodi |
Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2017 ACM on International Symposium on Physical Design, ISDP 2017, Portland, OR, USA, March 19-22, 2017, pp. 107-112, 2017, ACM, 978-1-4503-4696-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Ahmed Fahmy, Jun Liu 0038, Pavan Terdal, Ryan Madler, Rizwan Bashirullah, Nima Maghari |
A synthesizable time-based LDO using digital standard cells and analog pass transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017, pp. 271-274, 2017, IEEE, 978-1-5090-5025-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu |
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(8), pp. 974-983, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Gang Wu 0002, Chris Chu |
Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9), pp. 1569-1573, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan |
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(4), pp. 38:1-38:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Meghna G. Mankalale, Sachin S. Sapatnekar |
Optimized Standard Cells for All-Spin Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(2), pp. 21:1-21:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann |
FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 61, pp. 30-34, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016, pp. 44-49, 2016, IEEE, 978-1-5090-0733-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Sergey Bykov, Nikolai Ryzhenko, Anton Sorokin |
Automated solution for preventing design rules violations at abutment stage for standard cells synthesis flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2016 IEEE East-West Design & Test Symposium, EWDTS 2016, Yerevan, Armenia, October 14-17, 2016, pp. 1-4, 2016, IEEE Computer Society, 978-1-5090-0693-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin |
Practical ILP-based routing of standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 245-248, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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