Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
169 | Chung-Ping Chen, D. F. Wong 0001 |
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 604-607, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
148 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Global interconnect sizing and spacing with consideration of coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 628-633, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance |
126 | Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001 |
Optimal non-uniform wire-sizing under the Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 38-43, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation |
125 | Narender Hanchate, Nagarajan Ranganathan |
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 711-739, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay |
122 | Chris C. N. Chu, Martin D. F. Wong |
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 787-798, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
119 | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay |
Interconnect synthesis without wire tapering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 90-104, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
116 | Chris C. N. Chu, D. F. Wong 0001 |
Greedy wire-sizing is linear time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 39-44, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
106 | Chris C. N. Chu, D. F. Wong 0001 |
A new approach to simultaneous buffer insertion and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 614-621, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing |
105 | Takumi Okamoto, Jason Cong |
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 44-49, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing |
103 | Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia |
Fast interconnect synthesis with layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 71-77, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
buffer insertion, wire sizing, layer assignment, interconnect synthesis |
103 | Chris C. N. Chu, D. F. Wong 0001 |
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 343-371, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing |
102 | Narender Hanchate, Nagarajan Ranganathan |
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 283-290, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
99 | Chris C. N. Chu, D. F. Wong 0001 |
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 479-485, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing |
96 | Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi |
Wire Sizing for Non-Tree Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 872-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
89 | Jason Cong, David Zhigang Pan |
Wire width planning for interconnect performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 319-329, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
83 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 565-572, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
82 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 113-116, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
80 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Is wire tapering worthwhile? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 430-436, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
79 | Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang |
Width and Timing-Constrained Wire Sizing for Critical Area Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1276-1279, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
78 | Jason Cong, Cheng-Kok Koh |
Simultaneous driver and wire sizing for performance and power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 408-425, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
78 | Jason Cong, Cheng-Kok Koh |
Simultaneous driver and wire sizing for performance and power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 206-212, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
78 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 78-85, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP) |
78 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 166-173, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew |
76 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1915-1924, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
73 | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |
Timing-constrained yield-driven wire sizing for critical area minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
69 | Youxin Gao, Martin D. F. Wong |
Wire-sizing optimization with inductance consideration using transmission-line model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1759-1767, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Min Ni, Seda Ogrenci Memik |
Self-heating-aware optimal wire sizing under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1373-1378, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis |
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 280-284, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Song-Ra Pan, Yao-Wen Chang |
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 581-584, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
66 | Zhaoyun Xing, Prithviraj Banerjee |
A parallel algorithm for zero skew clock tree routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 118-123, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
64 | Qing Zhu, Wayne Wei-Ming Dai |
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1106-1118, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
63 | Jason Cong, Lei He 0001 |
An efficient approach to simultaneous transistor and interconnect sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 181-186, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing |
61 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1332-1340, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Chris C. N. Chu, Martin D. F. Wong |
Greedy wire-sizing is linear time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 398-405, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
60 | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang |
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 523-528, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Interconnect-Driven Floorplanning, Performance Optimization |
60 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 581-587, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan |
Track Routing and Optimization for Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 872-882, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Chris C. N. Chu, Martin D. F. Wong |
An efficient and optimal algorithm for simultaneous buffer and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1297-1304, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong |
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 1014-1025, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 592-597, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 580-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
53 | Magdy A. El-Moursy, Eby G. Friedman |
Power characteristics of inductive interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(12), pp. 1295-1306, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Rony Kay, Lawrence T. Pileggi |
EWA: efficient wiring-sizing algorithm for signal nets and clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 40-49, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
51 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 27-32, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect |
49 | Rupak Samanta, Jiang Hu, Peng Li 0001 |
Discrete buffer and wire sizing for link-based non-tree clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 175-181, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-tree, buffer, clock, wire, svm |
49 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 845-857, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown |
Clock buffer and wire sizing using sequential programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1041-1046, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
skew, robust design, clock tree synthesis |
49 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 867-881, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
49 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 144-151, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RC interconnect, optimization, sequential quadratic programming |
48 | Jason Cong, David Zhigang Pan |
Interconnect performance estimation models for design planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), pp. 739-752, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
48 | Jason Cong, David Zhigang Pan |
Interconnect Delay Estimation Models for Synthesis and Design Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 97-100, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
48 | Fu-Wei Chen, Yi-Yu Liu |
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 796-799, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Youxin Gao, D. F. Wong 0001 |
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 512-516, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
45 | Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan |
TROY: Track Router with Yield-driven Wire Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 55-58, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Noel Menezes, Chung-Ping Chen |
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 476-, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Sachin S. Sapatnekar |
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 1001-1011, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | Dian Zhou, Ruiming Li |
Design and Verification of High-Speed VLSI Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 147-165, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing |
42 | Jason Cong, Cheng-Kok Koh |
Interconnect layout optimization under higher-order RLC model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 713-720, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization |
42 | Xiaopeng Ji, Long Ge, Xiaodong Han, Zhiquan Wang |
Wire-Sizing for Interconnect Performance Optimization Considering High Inductance Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNSC ![In: Proceedings of the IEEE International Conference on Networking, Sensing and Control, ICNSC 2008, Hainan, China, 6-8 April 2008, pp. 1114-1118, 2008, IEEE, 978-1-4244-1685-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 600-608, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 361-366, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
A methodology for the simultaneous design of supply and signal networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1614-1624, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Sean X. Shi, David Z. Pan |
Wire sizing with scattering effect for nanoscale interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 503-508, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi |
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2), pp. 210-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 138-143, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay |
35 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Interconnect sizing and spacing with consideration of couplingcapacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1164-1169, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj |
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 158-163, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli |
Efficient Wire Routing and Wire Sizing for Weight Minimization of Automotive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11), pp. 1730-1741, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
33 | Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli |
An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014, pp. 19:1-19:6, 2014, ACM, 978-1-4503-2730-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
33 | Jiang-An He, Hideaki Kobayashi |
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 373-378, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
33 | Yu-Yen Mo, Chris C. N. Chu |
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 680-686, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong |
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 15(3), pp. 587-594, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Chris C. N. Chu, D. F. Wong 0001 |
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, pp. 192-197, 1997, ACM, 0-89791-927-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
Congestion-driven codesign of power and signal networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 64-69, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
signal routing, wire congestion, codesign, power grid noise |
29 | I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang |
Statistical circuit optimization considering device andinterconnect process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 47-54, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate and wire sizing, statistical optimization |
29 | Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex |
Impact of interconnect resistance increase on system performance of low power and high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 85-90, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing |
29 | Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex |
Interconnect width selection for deep submicron designs using the table lookup method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 41-44, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect sizing, power-delay trade-off, wire sizing |
29 | Chris C. N. Chu, D. F. Wong 0001 |
VLSI Circuit Performance Optimization by Geometric Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 105(1-4), pp. 37-60, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
27 | Vani Prasad, Madhav P. Desai |
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 417-422, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj |
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 456-463, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
X-clock routing based on pattern matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 357-360, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Clock network sizing via sequential linear programming with time-domain analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 182-189, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew, time-domain analysis |
22 | Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
Performance-driven Wire Sizing for Analog Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 28(2), pp. 19:1-19:23, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Yoonsang Song, Gangmin Cho, Wonjae Lee, Youngsoo Shin |
Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLCAD ![In: 5th ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2023, Snowbird, UT, USA, September 10-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-0955-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang |
Optimization of clock mesh based on wire sizing variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017, pp. 129-130, 2017, IEEE, 978-1-5386-2285-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Chris Chu |
Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Algorithms ![In: Encyclopedia of Algorithms - 2016 Edition, pp. 2374-2378, 2016, Springer, 978-1-4939-2863-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Shikha Singh 0004, V. Sulochana Verma |
Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACITY (3) ![In: Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India - Volume 3, pp. 677-686, 2012, Springer, 978-3-642-31599-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Rupak Samanta, Jiang Hu, Peng Li 0001 |
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(7), pp. 1025-1035, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Zhi-Wei Chen, Jin-Tai Yan |
Width-constrained wire sizing for non-tree interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2586-2589, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Sanghamitra Roy, Charlie Chung-Ping Chen |
Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Chris Chu |
Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Algorithms ![In: Encyclopedia of Algorithms - 2008 Edition, 2008, Springer, 978-0-387-30770-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Vinita V. Deodhar, Jeffrey A. Davis |
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(4), pp. 1023-1030, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Narender Hanchate, Nagarajan Ranganathan |
Integrated Gate and Wire Sizing at Post Layout Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 225-232, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 717-720, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny |
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters . ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 38(2), pp. 205-225, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 433-441, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Shlomo Greenberg, Ido Bloch, Moti Horwitz, Avishay Maman |
Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, Tel Aviv, Israel, December 13-15, 2004, pp. 419-423, 2004, IEEE, 0-7803-8715-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ting-Yuan Wang, Charlie Chung-Ping Chen |
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 157-162, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|