Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	T. H. Manjula Devi, Pooja P. Shenoy, Swathi Saigali, Harsha Mathew, K. B. Raja, K. R. Venugopal 0001, Lalit M. Patnaik	Extracting hidden image using histogram, DFT and SVM.	Bangalore Compute Conf.	2009	DBLP DOI BibTeX RDF	SVM, DFT, histogram, steganalysis
36	M. Ramalingam, K. Ramasami, Ponnambalam Venuvanalingam, J. Swaminathan	Ab Initio and DFT Investigations of the Mechanistic Pathway of Singlet Bromocarbenes Insertion into C-H Bonds of Methane and Ethane.	International Conference on Computational Science (2)	2007	DBLP DOI BibTeX RDF	bromocarbenes, ab initio, DFT, insertions, IRC
36	Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell	A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	DFT, ADC, mixed-signal testing, SiP, DAC, system-in-package
36	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	A Unified DFT Approach for BIST and External Test.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	BIST, DFT, test point insertion, partial reset
35	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
35	Michel Renovell, Florence Azaïs, Yves Bertrand	The multi-configuration: A DFT technique for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	multi-configuration technique, diagnosis facilities, 8/sup th/ order band pass filter, integrated circuit testing, design for testability, integrated circuit design, analog circuits, analogue integrated circuits, band-pass filters, DFT technique
35	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
35	Nilanjan Mukherjee 0001	Targeting "Zero DPPM" - Can we ever get there?	DFT	2008	DBLP DOI BibTeX RDF
35	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.	DFT	2007	DBLP DOI BibTeX RDF
35	Cecilia Metra, Martin Omaña 0001, Daniele Rossi 0001, José Manuel Cazeaux, T. M. Mak	The Other Side of the Timing Equation: a Result of Clock Faults.	DFT	2005	DBLP DOI BibTeX RDF
35	Baosheng Wang, Yuejian Wu, André Ivanov	Designs for Reducing Test Time of Distributed Small Embedded SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
35	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
33	Sanjiv Taneja	DFT Aware Layout - Layout Aware DFT.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
32	Hichem Boudali, A. P. Nijmeijer, Mariëlle Stoelinga	DFTSim: a simulation tool for extended dynamic fault trees.	SpringSim	2009	DBLP DOI BibTeX RDF	reliability benchmark, dependability analysis, simulation tool, dynamic fault trees
32	Martin Rötteler, Thomas Beth	Representation-theoretical properties of the approximate quantum Fourier transform.	Appl. Algebra Eng. Commun. Comput.	2008	DBLP DOI BibTeX RDF	Quantum Fourier transform, Basefield transforms, Quantum computing
32	Soo-Chang Pei, Jian-Jiun Ding, Wen-Liang Hsue, Kuo-Wei Chang	Generalized Commuting Matrices and Their Eigenvectors for DFTs, Offset DFTs, and Other Periodic Operations.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
32	Shaohua Li 0001, Defeng Huang, Khaled Ben Letaief, Zucheng Zhou	Multi-Stage Beamforming for Coded OFDM with Multiple Transmit and Multiple Receive Antennas.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
32	Loganathan Lingappan, Niraj K. Jha	Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler	Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.	FCCM	2007	DBLP DOI BibTeX RDF
32	Andreas Bonelli, Franz Franchetti, Juergen Lorenz, Markus Püschel, Christoph W. Ueberhuber	Automatic Performance Optimization of the Discrete Fourier Transform on Distributed Memory Computers.	ISPA	2006	DBLP DOI BibTeX RDF
32	Ping Tak Peter Tang	DFTI---a new interface for fast fourier transform libraries.	ACM Trans. Math. Softw.	2005	DBLP DOI BibTeX RDF	interface, software, FFT, API
32	Xiaoming Yu, Miron Abramovici	Sequential circuit ATPG using combinational algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
32	Janusz Rajski	Embedded Test Technology - Brief History, Current Status, and Future Directions.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
32	Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel	Automatic generation of customized discrete fourier transform IPs.	DAC	2005	DBLP DOI BibTeX RDF	design generator, FPGA, IP, discrete fourier transform
32	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Fault secureness need for next generation high performance microprocessor design for testability structures.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	built in self test, design for testability, microprocessor, comparator, fault secureness
32	Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin	A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
32	Teresa L. McLaurin, Frank Frederick, Rich Slobodnik	The Testability Features of The ARM1026EJ Microprocessor Core.	ITC	2003	DBLP DOI BibTeX RDF
32	Normand Beaudoin, Steven S. Beauchemin	An Accurate Discrete Fourier Transform for Image Processing.	ICPR (3)	2002	DBLP DOI BibTeX RDF
32	Cheong Yiu Fung, S. C. Chan 0001	A multistage filterbank-based channelizer and its multiplier-less realization.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
32	Jiun-In Guo, Chien-Chang Lin	A new hardware efficient design for the one dimensional discrete Fourier transform.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
32	Normand Beaudoin, Steven S. Beauchemin	Accurate Numerical Fourier Transform in d-Dimensions.	SNSC	2001	DBLP DOI BibTeX RDF
32	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel	Sequential circuit testability enhancement using a nonscan approach.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
32	Srinivas Chellappa, Franz Franchetti, Markus Püschel	Computer generation of fast fourier transforms for the cell broadband engine.	ICS	2009	DBLP DOI BibTeX RDF	dft, multibuffering, performance library, parallelization, streaming, fast fourier transform, multicore, program generation, cell be, automatic performance tuning
32	Anna Amat, Antonio Sgamellotti, Simona Fantacci	Theoretical Study of the Structural and Electronic Properties of Luteolin and Apigenin Dyes.	ICCSA (1)	2008	DBLP DOI BibTeX RDF	MP2, flavones, flavonoids, apigenin, luteolin, electronic structure, DFT
32	Ahmed Mostayed, Mohammad Mynuddin Gani Mazumder, Sikyung Kim, Se Jin Park	Abnormal Gait Detection Using Discrete Fourier Transform.	MUE	2008	DBLP DOI BibTeX RDF	DFT, Detection, Gait, Abnormal
32	Salem Abdennadher, Saghir A. Shaikh	Practices in Mixed-Signal and RF IC Testing.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	I/O testing, SiP testing, wireless transceiver testing, DFT, built-in tests, ATE
32	Daniel J. Bernstein	The Tangent FFT.	AAECC	2007	DBLP DOI BibTeX RDF	Tangent FFT, split-radix FFT, modified split-radix FFT, scaled odd tail, DFT, communication complexity, convolution, polynomial multiplication, algebraic complexity
32	Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka	A Design for testability Method Using RTL Partitioning.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure
32	Krishna B. Rajan, David E. Long, Miron Abramovici	Increasing testability by clock transformation (getting rid of those darn states).	VTS	1996	DBLP DOI BibTeX RDF	clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
32	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
31	Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni	A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs)
31	Hakim Bederr, Michael Nicolaidis, Alain Guyot	Analytic approach for error masking elimination in on-line multipliers.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
28	Yu Wang 0019, Hongyi Wu, Ha Dang	Analytic study of Delay/Fault-Tolerant Mobile Sensor Networks (DFT-MSN's).	WOWMOM	2009	DBLP DOI BibTeX RDF
28	Nadia El Mrabet, Christophe Nègre	Finite Field Multiplication Combining AMNS and DFT Approach for Pairing Cryptography.	ACISP	2009	DBLP DOI BibTeX RDF	AMNS, discrete Fourrier transform, finite fields, Pairing
28	Satyender Goel, Artëm E. Masunov	Pairwise Spin-Contamination Correction Method and DFT Study of MnH and H2 Dissociation Curves.	ICCS (2)	2009	DBLP DOI BibTeX RDF
28	Meng-Lin Ku, Chia-Chi Huang	A derivation on the equivalence between newton's method and DF DFT-based method for channel estimation in OFDM systems.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
28	Hanguang Wu, Thomas Haustein	Radio Resource Management for the Multi-User Uplink Using DFT-Precoded OFDM.	ICC	2008	DBLP DOI BibTeX RDF
28	Stephan Jaeckel, Volker Jungnickel	On the Optimality of Frequency-Domain Equalization in DFT-Spread MIMO-OFDM Systems.	WCNC	2008	DBLP DOI BibTeX RDF
28	Chao Wang 0019, Chunyan Huang, Xiaoli Zhang, Huaxiang Wang	Mixing Frequency Bio-impedance Measurement Technology based on DFT and Virtual Reference Vector.	BMEI (2)	2008	DBLP DOI BibTeX RDF	Bio-impedance Measurement, Mixing frequency Excitation, Discrete Fourier Transform Demodulation, Virtual Preference Vector, Dynamic Information Detection
28	Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla	DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A General Class of Split-Radix FFT Algorithms for the Computation of the DFT of Length-2m.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
28	Salvatore Distefano, Antonio Puliafito	DFT and DRBD in Computing Systems Dependability Analysis.	SAFECOMP	2007	DBLP DOI BibTeX RDF
28	Ajmal H. Hamdani, S. Shahdin	DFT studies of closely bound ground state of (N2-N2)+1 ionic dimmer.	ICQNM	2007	DBLP DOI BibTeX RDF
28	Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla	A Novel RF Test Scheme Based on a DFT Method.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	RF design-for-testability, known-good-die, defects, low noise amplifier, RF test
28	Soumendu Bhattacharya, Abhijit Chatterjee	A DFT Approach for Testing Embedded Systems Using DC Sensors.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	computer-aided design, test generation, built-in tests, reliability and testing
28	Dong Li, Feng Guo, Guosong Li, Liyu Cai	Enhanced DFT Interpolation-based Channel Estimation for OFDM Systems with Virtual Subcarriers.	VTC Spring	2006	DBLP DOI BibTeX RDF
28	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
28	Andrew Naftel, Shehzad Khalid	Motion Trajectory Learning in the DFT-Coefficient Feature Space.	ICVS	2006	DBLP DOI BibTeX RDF
28	M. Ramalingam, K. Ramasami, Ponnambalam Venuvanalingam, V. Sethuraman	C-H Functionalisation Through Singlet Chlorocarbenes Insertions - MP2 and DFT Investigations.	International Conference on Computational Science (3)	2006	DBLP DOI BibTeX RDF
28	See-May Phoong, Yubing Chang, Chun-Yang Chen	DFT-modulated filterbank transceivers for multipath fading channels.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
28	Gagan Rath, Christine Guillemot	Subspace algorithms for error localization with quantized DFT codes.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
28	Yuan-Pei Lin, See-May Phoong	DFT based transceivers with-windowing.	ISCC	2004	DBLP DOI BibTeX RDF
28	David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher	An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor.	ITC	2004	DBLP DOI BibTeX RDF
28	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi	A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.	ITC	2004	DBLP DOI BibTeX RDF
28	Jeff Remmers, Moe Villalba, Richard Fisette	Hierarchical DFT Methodology - A Case Study.	ITC	2004	DBLP DOI BibTeX RDF
28	K. Nikila, Rubin A. Parekhji	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.	ITC	2004	DBLP DOI BibTeX RDF
28	Muhammad Nummer, Manoj Sachdev	A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, delay-fault testing, design for delay testability
28	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A split-radix algorithm for 2-D DFT.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
28	Kenneth E. Posse, Geir Eide	Key Impediments to DFT-Focused Test and How to Overcome Them.	ITC	2003	DBLP DOI BibTeX RDF
28	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
28	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	controller-datapath circuit, hierarchical test path, influence tables, transparency
28	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi	A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.	ITC	2002	DBLP DOI BibTeX RDF
28	Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead	Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .	ITC	2002	DBLP DOI BibTeX RDF
28	Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung	Re-Using DFT Logic for Functional and Silicon Debugging Test.	ITC	2002	DBLP DOI BibTeX RDF
28	Yaxiao Song, Minghao Cui, Hongxun Yao	A High Capacity Data Hiding Scheme Based on DFT.	IEEE Pacific Rim Conference on Multimedia	2002	DBLP DOI BibTeX RDF
28	Janusz Rajski	DFT for High-Quality Low Cost Manufacturing Test.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	N. Nakanishi, Yoshio Itoh, Yutaka Fukui, Kensaku Fujii	Noise reduction system using modified DFT pair.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
28	Antonio Zenteno, Víctor H. Champac	Resistive Opens in a Class of CMOS Latches: Analysis and DFT.	VTS	2001	DBLP DOI BibTeX RDF
28	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
28	Jae-Hwa Kim, Tae-Gyu Chang	Analytic derivation of the performance degradation in recursive implementation of sliding-DFT with the twiddle factors of finite-bit precision.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
28	Gadi Singer	The Future of Test and DFT.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
28	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	DfT Architecture for 3D-SICs with Multiple Towers.	ETS	2011	DBLP DOI BibTeX RDF	three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via
28	S. Saqib Khursheed, Sheng Yang 0003, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn	Improved DFT for Testing Power Switches.	ETS	2011	DBLP DOI BibTeX RDF	power switch, leakage power management, test time overhead, DFT, design for test, Sleep transistor
28	Jiancheng Zou, Xin Yang, Shaozhang Niu	A Novel Robust Watermarking Method for Certificates Based on DFT and Hough Transforms.	IIH-MSP	2010	DBLP DOI BibTeX RDF	certificate security, digital watermark, DFT, Hough transformations
28	Sandhya Seshadri, Michael S. Hsiao	Behavioral-Level DFT via Formal Operator Testability Measures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	behavioral level, operator testability, value range, SSA representation, DFT
28	Daniela De Venuto, Michael J. Ohletz, Bruno Riccò	Digital Window Comparator DfT Scheme for Mixed-Signal ICs.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	mixed-signal ASIC, window comparator, GO/NOGO test, signal level evaluation, DfT
28	Eduardo Fullea, José María Martínez Sanchez	Robust digital image watermarking using DWT, DFT and quality based average.	ACM Multimedia	2001	DBLP DOI BibTeX RDF	estimated quality based average, watermark, DFT, DWT, stirmark
28	Hsin-Po Wang 0002, Jon Turino	DFT and BIST techniques for the future.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multimillion gate system-on-chip, multinational design, logic testing, built-in self test, design for testability, quality, BIST, economics, DFT, integrated circuit design, time to market, production testing, IC design, integrated circuit economics
28	Diego Vázquez, José L. Huertas, Adoración Rueda	Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design.	VTS	1996	DBLP DOI BibTeX RDF	sw-op amp design, CMOS implementations, design efforts, cell design, integrated circuit testing, design for testability, DFT, integrated circuit design, power dissipation, operational amplifiers, area, analogue integrated circuits, IC testing, analog integrated circuits, CMOS analogue integrated circuits
28	Sandeep Pagey, Ajay Khoche, Erik Brunvand	DFT for fast testing of self-timed control circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software
27	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
27	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio (eds.)	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023	DFT	2023	DBLP DOI BibTeX RDF
27	Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai	A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage.	DFT	2023	DBLP DOI BibTeX RDF
27	Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann	An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.	DFT	2023	DBLP DOI BibTeX RDF
27	Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh	On Attacking Scan-based Logic Locking Schemes.	DFT	2023	DBLP DOI BibTeX RDF
27	S. Bouat, Stéphanie Anceau, Laurent Maingault, Jessy Clédière, Luc Salvo, Rémi Tucoulou	X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits.	DFT	2023	DBLP DOI BibTeX RDF
27	Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Ilias Golfos, Marko S. Andjelkovic, Christos P. Sotiriou, Milos Krstic	Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.	DFT	2023	DBLP DOI BibTeX RDF
27	Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi	Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis.	DFT	2023	DBLP DOI BibTeX RDF
27	Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba	Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder.	DFT	2023	DBLP DOI BibTeX RDF
27	Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura	An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing.	DFT	2023	DBLP DOI BibTeX RDF