Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková |
I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 92-93, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VLSI, Testing, Sensors, Iddq, Ultra-Low-Voltage, Current |
36 | Yiming Gong, Sreejit Chakravarty |
Using fault sampling to compute IDDQ diagnostic test set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 74-79, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults |
36 | Sreejit Chakravarty, Paul J. Thadikaran |
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(10), pp. 1131-1140, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
test generation, fault simulation, Bridging faults, IDDQ testing |
36 | Salvador Manich, Michael Nicolaidis, Joan Figueras |
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 124-129, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness |
31 | Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková |
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 259-262, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Phil Nigh, Anne E. Gattiker |
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 309-318, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | W. Robert Daasch, James McNames, Robert Madge, Kevin Cota |
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(5), pp. 74-81, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz |
CMOS Standard Cells Characterization for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 390-398, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Alessandro Bogliolo, Michele Favalli, Maurizio Damiani |
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 415-419, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Manoj Sachdev, Hans G. Kerkhoff |
Configurations for IDDQ-Testable PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(2), pp. 58-65, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Josep Rius 0001, Joan Figueras |
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 543-548, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 375-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Junichi Hirase, Naoki Shindou, Kouji Akahori |
Scan Chain Diagnosis Using IDDQ Current Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 153-157, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Kaamran Raahemifar, Majid Ahmadi |
On-line IDDQ fault testing for CMOS/BiCMOS logic families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 105-109, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Th. Calin, Lorena Anghel, Michael Nicolaidis |
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 135-142, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Robert C. Aitken |
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 128-134, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Eberhard Böhl, Thomas Lindenkreuz, Matthias Meerwein |
On-Chip IDDQ Testing in the AE11 Fail-Stop Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(4), pp. 57-65, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Phil Nigh, David P. Vallett, Atul Patel, Jason Wright |
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 43-52, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Anne E. Gattiker, Wojciech Maly |
Toward understanding "Iddq-only" fails. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 174-183, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Marcello Dalpasso, Michele Favalli |
A method for increasing the IDDQ testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1186-1188, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel |
Algorithms to compute bridging fault coverage of IDDQ test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(3), pp. 281-305, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | M. Svajda, B. Straka, Hans A. R. Manhaeve |
A monolithic off-chip IDDQ monitor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 629, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Viera Stopjaková, Hans A. R. Manhaeve |
CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 266-270, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Christopher G. Knight, Adit D. Singh, Victor P. Nelson |
An IDDQ Sensor for Concurrent Timing Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 281-289, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Paul J. Thadikaran, Sreejit Chakravarty |
Fast Algorithms for Computer IDDQ Tests for Combination Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 103-106, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Víctor H. Champac, Antonio Rubio 0001, Joan Figueras |
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 359-369, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel |
Defect Simulation Methodology for iDDT Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 255-272, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test |
29 | Scott Davidson 0001 |
Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 565, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics |
29 | Sagar S. Sabade, D. M. H. Walker |
IDDX-based test methods: A survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(2), pp. 159-198, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IDDT test, test, VLSI testing, IDDQ |
29 | Yukiya Miura, Shuichi Seno |
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 109-120, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis |
29 | Jonathan T.-Y. Chang, Edward J. McCluskey |
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 446-, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC |
29 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
29 | Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito |
A CMOS gate array with dynamic-termination GTL I/O circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 25-29, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays |
24 | Janusz Rajski, Kan Thapar |
Nanometer Design: What are the Requirements for Manufacturing Test? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 930-937, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Sagar S. Sabade, D. M. H. Walker |
CROWNE: Current Ratio Outliers with Neighbor Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 132-139, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Rajiv V. Joshi, Kaushik Roy 0001 |
Design of Deep Sub-Micron CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 15-16, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo |
CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 417-422, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Bartomeu Alorda, Ivan de Paúl, Jaume Segura 0001, T. Miller |
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 87-91, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Víctor H. Champac, Antonio Zenteno |
Detectability Conditions for Interconnection Open Defect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 305-312, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Haluk Konuk |
Voltage- and current-based fault simulation for interconnect open defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1768-1779, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | S. M. Aziz, Joarder Kamruzzaman |
Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 119-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy 0001 |
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 243-248, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDD Waveforms Analysis, Testing |
24 | Manoj Sachdev, Peter Janssen, Victor Zieren |
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 204, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Yukio Okuda, Isao Kubota, Masahiro Watanabe |
Defect level prediction for I_DDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 900-909, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs |
Circuit-level dictionaries of CMOS bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 596-603, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao |
CNN-Based Stochastic Regression for IDDQ Outlier Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 4282-4295, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao |
CNN-based Stochastic Regression for IDDQ Outlier Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5359-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal |
Two-Pattern ∆IDDQ Test for Recycled IC Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019, pp. 82-87, 2019, IEEE, 978-1-7281-0409-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Franco Stellari, Naigang Wang, Peilin Song |
Novel IC Sub-Threshold IDDQ Signature And Its Relationship To Aging During High Voltage Stress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 250-253, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis |
A current monitoring technique for IDDQ testing in digital integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 50, pp. 48-60, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Chia-Ling Lynn Chang, Charles H.-P. Wen |
Demystifying Iddq Data With Process Variation for Automatic Chip Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(6), pp. 1175-1179, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Yong Zhao, Hans G. Kerkhoff |
Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-5, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Michihiro Shintani, Takashi Sato |
IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(8), pp. 2095-2104, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Michihiro Shintani, Takashi Sato |
Device-Parameter Estimation through IDDQ Signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 96-D(2), pp. 303-313, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra |
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 454-457, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Michihiro Shintani, Takashi Sato |
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, pp. 614-619, 2013, IEEE, 978-1-4673-3029-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang |
An IDDQ-based source driver IC design-for-test technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013, pp. 393-398, 2013, IEEE, 978-1-4799-1069-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala |
An IDDQ BIST approach to characterize phase-locked loop parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4673-5542-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra |
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, pp. 163-168, 2012, IEEE, 978-1-4673-0770-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Michihiro Shintani, Takashi Sato |
A Bayesian-based process parameter estimation using IDDQ current signature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 86-91, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Claude Thibeault, Yassine Hariri |
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(1), pp. 130-141, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng |
Deterministic IDDQ diagnosis using a net activation based model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011, pp. 1-10, 2011, IEEE Computer Society, 978-1-4577-0153-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic |
Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 5(4), pp. 893-904, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Samed Maltabas, Osman Kubilay Ekekon, Martin Margala |
A new built-in IDDQ testing method using programmable BICS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 15th European Test Symposium, ETS 2010, Prague, Czech Republic, May 24-28, 2010, pp. 264, 2010, IEEE Computer Society, 978-1-4244-5833-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Yoshiyuki Nakamura, Masashi Tanaka |
A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 303-309, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin |
Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 58(7), pp. 2196-2208, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic |
Characterizing within-die variation from multiple supply port IDDQ measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, pp. 418-424, 2009, ACM, 978-1-60558-800-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Ricky Smith, Jiang Shi |
DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 270, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Junichi Hirase |
Defect Detection Rate through IDDQ for Production Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 199-205, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1245-1255, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Afzel Noore |
Improved IDDQ design-for-testability technique to detect CMOS stuck-open faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 4(3), pp. 94-99, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong |
IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007, pp. 211, 2007, IEEE, 0-7695-2890-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Michael Laisne, Triphuong Nguyen, Songlin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman |
Verification and debugging of IDDQ test of low power chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pp. 1-7, 2007, IEEE Computer Society, 1-4244-1128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy 0001 |
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pp. 1-10, 2007, IEEE Computer Society, 1-4244-1128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jeong Beom Kim, Seung Ho Hong |
A CMOS Built-In Current Sensor for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(6), pp. 868-870, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura |
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 69-74, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker 0001 |
Delta-IDDQ Testing of Resistive Short Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 63-68, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jeong Beom Kim |
Novel Current Sensing Circuit for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 375-378, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Doug Heaberlin |
The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Ashok K. Srivastava, Srinivas Rao Aluri, Anand Kumar Chamakura |
A simple built-in current sensor for IDDQ testing of CMOS data converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 38(4), pp. 579-596, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita |
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 88-D(4), pp. 703-710, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis |
An embedded IDDQ testing circuit and technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir |
A built-in IDDQ testing circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005, pp. 471-474, 2005, IEEE, 0-7803-9205-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Bin Xue, D. M. H. Walker |
IDDQ test using built-in current sensing of supply line voltage drop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 10, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada |
Test Sequence Generation for Test Time Reduction of IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 87-D(3), pp. 537-543, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Masaru Sanada |
Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 87-D(3), pp. 557-563, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Sagar S. Sabade, D. M. H. Walker |
IDDQ data analysis using neighbor current ratios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 50(5), pp. 287-294, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De |
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 863-870, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Claude Thibeault |
Replacing IDDQ Testing: With Variance Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 325-340, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
(Delta) I DDQ testing, HBTP, test, variance reduction |
19 | Claude Thibeault |
On Faster IDDQ Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(6), pp. 625-635, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASA-I DDQ, I DDQ |
19 | Oleg Semenov, Arman Vassighi, Manoj Sachdev |
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 341-352, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing |
19 | Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve |
A practical evaluation of IDDQ test strategies for deep submicron production test application. Experiences and targets from the field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 8th European Test Workshop, ETW 2003, Maastricht, The Netherlands, May 25-28, 2003, pp. 65-70, 2003, IEEE Computer Society, 0-7695-1908-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Terence Hook, Larry Wissel, David Mazgaj |
Estimation of Iddq for early chip and technology design decisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 627-630, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni |
A new technique for IDDQ testing in nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 31(2), pp. 183-194, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Franco Stellari, Peilin Song, James C. Tsang, Moyra K. McManus, Mark B. Ketchen |
Optical diagnosis of excess IDDQ in low power CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 42(9-11), pp. 1689-1694, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001 |
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(2), pp. 24-33, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Seok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo |
Studies of the SEMATECH IDDq test data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 47(10), pp. 831-846, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz |
A real world application used to implement a true IDDQ based test strategy (facts and figures). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002, pp. 81-86, 2002, IEEE Computer Society, 0-7695-1715-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Srdjan Dragic, Martin Margala |
Application-specific low-voltage current amplifier for system-on-chip IDDQ test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 397-400, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001 |
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 186-192, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|