Search results for "Iddq"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková	I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Testing, Sensors, Iddq, Ultra-Low-Voltage, Current
36	Yiming Gong, Sreejit Chakravarty	Using fault sampling to compute IDDQ diagnostic test set.	VTS	1997	DBLP DOI BibTeX RDF	fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults
36	Sreejit Chakravarty, Paul J. Thadikaran	Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	test generation, fault simulation, Bridging faults, IDDQ testing
36	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
31	Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková	Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.	DDECS	2008	DBLP DOI BibTeX RDF
31	Phil Nigh, Anne E. Gattiker	Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions.	ITC	2004	DBLP DOI BibTeX RDF
31	W. Robert Daasch, James McNames, Robert Madge, Kevin Cota	Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
31	Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz	CMOS Standard Cells Characterization for IDDQ Testing.	DFT	2002	DBLP DOI BibTeX RDF
31	Alessandro Bogliolo, Michele Favalli, Maurizio Damiani	Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
31	Manoj Sachdev, Hans G. Kerkhoff	Configurations for IDDQ-Testable PLAs.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
31	Josep Rius 0001, Joan Figueras	Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.	DATE	1999	DBLP DOI BibTeX RDF
31	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
31	Junichi Hirase, Naoki Shindou, Kouji Akahori	Scan Chain Diagnosis Using IDDQ Current Measurement.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
31	Kaamran Raahemifar, Majid Ahmadi	On-line IDDQ fault testing for CMOS/BiCMOS logic families.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
31	Th. Calin, Lorena Anghel, Michael Nicolaidis	Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS.	VTS	1999	DBLP DOI BibTeX RDF
31	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
31	Eberhard Böhl, Thomas Lindenkreuz, Matthias Meerwein	On-Chip IDDQ Testing in the AE11 Fail-Stop Controller.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
31	Phil Nigh, David P. Vallett, Atul Patel, Jason Wright	Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.	ITC	1998	DBLP DOI BibTeX RDF
31	Anne E. Gattiker, Wojciech Maly	Toward understanding "Iddq-only" fails.	ITC	1998	DBLP DOI BibTeX RDF
31	Marcello Dalpasso, Michele Favalli	A method for increasing the IDDQ testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel	Algorithms to compute bridging fault coverage of IDDQ test sets.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF
31	M. Svajda, B. Straka, Hans A. R. Manhaeve	A monolithic off-chip IDDQ monitor.	ED&TC	1997	DBLP DOI BibTeX RDF
31	Viera Stopjaková, Hans A. R. Manhaeve	CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
31	Christopher G. Knight, Adit D. Singh, Victor P. Nelson	An IDDQ Sensor for Concurrent Timing Error Detection.	DFT	1997	DBLP DOI BibTeX RDF
31	Paul J. Thadikaran, Sreejit Chakravarty	Fast Algorithms for Computer IDDQ Tests for Combination Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
31	Víctor H. Champac, Antonio Rubio 0001, Joan Figueras	Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
29	Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
29	Scott Davidson 0001	Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics
29	Sagar S. Sabade, D. M. H. Walker	IDDX-based test methods: A survey.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	IDDT test, test, VLSI testing, IDDQ
29	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
29	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
29	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
29	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits.	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
24	Janusz Rajski, Kan Thapar	Nanometer Design: What are the Requirements for Manufacturing Test?	DATE	2004	DBLP DOI BibTeX RDF
24	Sagar S. Sabade, D. M. H. Walker	CROWNE: Current Ratio Outliers with Neighbor Estimator.	DFT	2003	DBLP DOI BibTeX RDF
24	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
24	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo	CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
24	Bartomeu Alorda, Ivan de Paúl, Jaume Segura 0001, T. Miller	On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor.	IOLTW	2000	DBLP DOI BibTeX RDF
24	Víctor H. Champac, Antonio Zenteno	Detectability Conditions for Interconnection Open Defect.	VTS	2000	DBLP DOI BibTeX RDF
24	Haluk Konuk	Voltage- and current-based fault simulation for interconnect open defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
24	S. M. Aziz, Joarder Kamruzzaman	Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
24	Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy 0001	IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	IDD Waveforms Analysis, Testing
24	Manoj Sachdev, Peter Janssen, Victor Zieren	Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.	ITC	1998	DBLP DOI BibTeX RDF
24	Yukio Okuda, Isao Kubota, Masahiro Watanabe	Defect level prediction for I_DDQ testing.	ITC	1998	DBLP DOI BibTeX RDF
24	Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs	Circuit-level dictionaries of CMOS bridging faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
19	Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao	CNN-Based Stochastic Regression for IDDQ Outlier Identification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao	CNN-based Stochastic Regression for IDDQ Outlier Identification.	VTS	2020	DBLP DOI BibTeX RDF
19	Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal	Two-Pattern ∆IDDQ Test for Recycled IC Detection.	VLSID	2019	DBLP DOI BibTeX RDF
19	Franco Stellari, Naigang Wang, Peilin Song	Novel IC Sub-Threshold IDDQ Signature And Its Relationship To Aging During High Voltage Stress.	ESSDERC	2018	DBLP DOI BibTeX RDF
19	Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis	A current monitoring technique for IDDQ testing in digital integrated circuits.	Integr.	2015	DBLP DOI BibTeX RDF
19	Chia-Ling Lynn Chang, Charles H.-P. Wen	Demystifying Iddq Data With Process Variation for Automatic Chip Classification.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
19	Yong Zhao, Hans G. Kerkhoff	Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation.	DTIS	2015	DBLP DOI BibTeX RDF
19	Michihiro Shintani, Takashi Sato	IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
19	Michihiro Shintani, Takashi Sato	Device-Parameter Estimation through IDDQ Signatures.	IEICE Trans. Inf. Syst.	2013	DBLP DOI BibTeX RDF
19	Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra	Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step.	DATE	2013	DBLP DOI BibTeX RDF
19	Michihiro Shintani, Takashi Sato	An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation.	ASP-DAC	2013	DBLP DOI BibTeX RDF
19	S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang	An IDDQ-based source driver IC design-for-test technique.	ICCAD	2013	DBLP DOI BibTeX RDF
19	Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala	An IDDQ BIST approach to characterize phase-locked loop parameters.	VTS	2013	DBLP DOI BibTeX RDF
19	Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra	An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.	ASP-DAC	2012	DBLP DOI BibTeX RDF
19	Michihiro Shintani, Takashi Sato	A Bayesian-based process parameter estimation using IDDQ current signature.	VTS	2012	DBLP DOI BibTeX RDF
19	Claude Thibeault, Yassine Hariri	CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng	Deterministic IDDQ diagnosis using a net activation based model.	ITC	2011	DBLP DOI BibTeX RDF
19	Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic	Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s.	IEEE Trans. Inf. Forensics Secur.	2010	DBLP DOI BibTeX RDF
19	Samed Maltabas, Osman Kubilay Ekekon, Martin Margala	A new built-in IDDQ testing method using programmable BICS.	ETS	2010	DBLP DOI BibTeX RDF
19	Yoshiyuki Nakamura, Masashi Tanaka	A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance.	DFT	2010	DBLP DOI BibTeX RDF
19	Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin	Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits.	IEEE Trans. Instrum. Meas.	2009	DBLP DOI BibTeX RDF
19	Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic	Characterizing within-die variation from multiple supply port IDDQ measurements.	ICCAD	2009	DBLP DOI BibTeX RDF
19	Ricky Smith, Jiang Shi	DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits.	ATS	2008	DBLP DOI BibTeX RDF
19	Junichi Hirase	Defect Detection Rate through IDDQ for Production Testing.	ATS	2008	DBLP DOI BibTeX RDF
19	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Afzel Noore	Improved IDDQ design-for-testability technique to detect CMOS stuck-open faults.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
19	Yu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong	IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy.	ATS	2007	DBLP DOI BibTeX RDF
19	Michael Laisne, Triphuong Nguyen, Songlin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman	Verification and debugging of IDDQ test of low power chips.	ITC	2007	DBLP DOI BibTeX RDF
19	Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy 0001	Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ.	ITC	2007	DBLP DOI BibTeX RDF
19	Jeong Beom Kim, Seung Ho Hong	A CMOS Built-In Current Sensor for IDDQ Testing.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
19	Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura	A BIC Sensor Capable of Adjusting IDDQ Limit in Tests.	ATS	2006	DBLP DOI BibTeX RDF
19	Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker 0001	Delta-IDDQ Testing of Resistive Short Defects.	ATS	2006	DBLP DOI BibTeX RDF
19	Jeong Beom Kim	Novel Current Sensing Circuit for IDDQ Testing.	ICECS	2006	DBLP DOI BibTeX RDF
19	Doug Heaberlin	The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution.	ITC	2006	DBLP DOI BibTeX RDF
19	Ashok K. Srivastava, Srinivas Rao Aluri, Anand Kumar Chamakura	A simple built-in current sensor for IDDQ testing of CMOS data converters.	Integr.	2005	DBLP DOI BibTeX RDF
19	Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
19	Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis	An embedded IDDQ testing circuit and technique.	ICECS	2005	DBLP DOI BibTeX RDF
19	Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir	A built-in IDDQ testing circuit.	ESSCIRC	2005	DBLP DOI BibTeX RDF
19	Bin Xue, D. M. H. Walker	IDDQ test using built-in current sensing of supply line voltage drop.	ITC	2005	DBLP DOI BibTeX RDF
19	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada	Test Sequence Generation for Test Time Reduction of IDDQ Testing.	IEICE Trans. Inf. Syst.	2004	DBLP BibTeX RDF
19	Masaru Sanada	Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ.	IEICE Trans. Inf. Syst.	2004	DBLP BibTeX RDF
19	Sagar S. Sabade, D. M. H. Walker	IDDQ data analysis using neighbor current ratios.	J. Syst. Archit.	2004	DBLP DOI BibTeX RDF
19	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De	Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
19	Claude Thibeault	Replacing IDDQ Testing: With Variance Reduction.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	(Delta) I DDQ testing, HBTP, test, variance reduction
19	Claude Thibeault	On Faster IDDQ Measurements.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	ASA-I DDQ, I DDQ
19	Oleg Semenov, Arman Vassighi, Manoj Sachdev	Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing
19	Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve	A practical evaluation of IDDQ test strategies for deep submicron production test application. Experiences and targets from the field.	ETW	2003	DBLP DOI BibTeX RDF
19	Terence Hook, Larry Wissel, David Mazgaj	Estimation of Iddq for early chip and technology design decisions.	CICC	2003	DBLP DOI BibTeX RDF
19	Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni	A new technique for IDDQ testing in nanometer technologies.	Integr.	2002	DBLP DOI BibTeX RDF
19	Franco Stellari, Peilin Song, James C. Tsang, Moyra K. McManus, Mark B. Ketchen	Optical diagnosis of excess IDDQ in low power CMOS circuits.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
19	Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001	IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
19	Seok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo	Studies of the SEMATECH IDDq test data.	J. Syst. Archit.	2002	DBLP DOI BibTeX RDF
19	Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz	A real world application used to implement a true IDDQ based test strategy (facts and figures).	ETW	2002	DBLP DOI BibTeX RDF
19	Srdjan Dragic, Martin Margala	Application-specific low-voltage current amplifier for system-on-chip IDDQ test.	ICECS	2002	DBLP DOI BibTeX RDF
19	Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001	IDDQ Testing for Deep Submicron ICs: Challenges and Solutions.	LATW	2002	DBLP BibTeX RDF