Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Walker H. Land, Frances R. Anderson, Tom Smith, Stephen Fahlbusch, Robert Choma, Lut Wong	Applying knowledge engineering and representation methods to improve support vector machine and multivariate probabilistic neural network CAD performance.	Medical Imaging: Image Processing	2005	DBLP DOI BibTeX RDF
36	Walker H. Land Jr., Mark J. Embrechts, Frances R. Anderson, Tom Smith, Lut Wong, Stephen Fahlbusch, Robert Choma	Integrating knowledge representation/engineering, the multivariant PNN, and machine learning to improve breast cancer diagnosis.	Data Mining, Intrusion Detection, Information Assurance, and Data Networks Security	2005	DBLP DOI BibTeX RDF
36	Omowunmi Sadik, Walker H. Land Jr., Adam K. Wanekaya, Michiko Uematsu, Mark J. Embrechts, Lut Wong, Dale Leibensperger, Alex Volykin	Detection and Classification of Organophosphate Nerve Agent Simulants Using Support Vector Machines with Multiarray Sensors.	J. Chem. Inf. Model.	2004	DBLP DOI BibTeX RDF
36	Walker H. Land, Lut Wong, Daniel W. McKee, Timothy Masters, Frances R. Anderson, Anurag Raturi, Joseph Y. Lo	New results in computer-aided diagnosis (CAD) of breast cancer using a recently developed SVM/GRNN Oracle hybrid.	Medical Imaging: Image Processing	2004	DBLP DOI BibTeX RDF
36	Walker H. Land Jr., Lut Wong, Daniel W. McKee, Mark J. Embrechts, Rizly Salih, Frances R. Anderson	Applying Support Vector Machines to Breast Cancer Diagnosis using Screen Film Mammogram Data.	CBMS	2004	DBLP DOI BibTeX RDF
36	Walker H. Land, Daniel W. McKee, Roberto Velazquez, Lut Wong, Joseph Y. Lo, Frances R. Anderson	Application of support vector machines to breast cancer screening using mammogram and clinical history data.	Medical Imaging: Image Processing	2003	DBLP DOI BibTeX RDF
36	Walker H. Land Jr., Dale Leibensperger, Lut Wong, Omowunmi Sadik, A. Wanekeyab, Michiko Uematsu, Mark J. Embrechts	New results using multi array sensors and support vector machines for the detection and classification of organophosphate nerve agents.	SMC	2003	DBLP DOI BibTeX RDF
36	Walker H. Land Jr., Lut Wong, Daniel W. McKee, Timothy Masters, Frances R. Anderson	Breast cancer computer aided diagnosis (CAD) using a recently developed SVM/GRNN Oracle hybrid.	SMC	2003	DBLP DOI BibTeX RDF
33	Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan	LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.	CoRR	2018	DBLP BibTeX RDF
33	Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan	LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.	ISVLSI	2018	DBLP DOI BibTeX RDF
33	Francisco-Javier Veredas, Hans-Jörg Pfleiderer	Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.	FPL	2006	DBLP DOI BibTeX RDF
33	Van Viet Le	Optimisation temporelle des réseaux programmables à base de LUT. (Performance Optimization for LUT-based programmable devices).		1996	RDF
32	Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm
32	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
32	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
32	Tsutomu Sasao	Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions.	ISMVL	1999	DBLP DOI BibTeX RDF	LUT-based FPGA, Multiple-valued logic function, Functional decomposition, Symmetric function
32	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
32	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
31	Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton	SmartOpt: an industrial strength framework for logic synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	abc, blif, edge flow, smartopt, fpga, interface, technology mapping
31	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA technology mapping for improved routability.	FPGA	2008	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
31	Seydou-Nourou Ba, Khurram Waheed, Guo Tong Zhou	Efficient spacing scheme for a linearly interpolated lookup table predistorter.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Wen-Ching Lin, Jun-Hong Chen, Ming-Der Shieh	A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m).	ISCAS	2008	DBLP DOI BibTeX RDF
31	Dong Liang 0001, Edmund Y. Lam, George S. K. Fung	Direct Reconstruction of Spiral Mri Using Least Squares Quantization Table.	ISBI	2007	DBLP DOI BibTeX RDF
31	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
31	Guo Yu, Peng Li 0001	Lookup table based simulation and statistical modeling of Sigma-Delta ADCs.	DAC	2006	DBLP DOI BibTeX RDF	statistical modeling, lookup table, Sigma-Delta
31	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
31	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A function generator-based reconfigurable system.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit	Evaluating Alternative Implementations for LDPC Decoder Check Node Function.	ISVLSI	2004	DBLP DOI BibTeX RDF
31	Fatih Kocan, Jason Meyer	Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays.	FPL	2004	DBLP DOI BibTeX RDF
31	Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson	An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic.	FCCM	2004	DBLP DOI BibTeX RDF
31	D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao	Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
31	Jason Cong, Yizhou Lin, Wangning Long	SPFD-based global rewiring.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis
31	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping for k/m-macrocell based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
31	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
31	Christian Legl, Bernd Wurth, Klaus Eckl	Computing support-minimal subfunctions during functional decomposition.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
31	Jordan S. Swartz, Vaughn Betz, Jonathan Rose	A Fast Routability-Driven Router for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
31	Hiroshi Sawada, Takayuki Suyama, Akira Nagoya	Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.	ICCAD	1995	DBLP DOI BibTeX RDF	support minimization, Boolean resubstitution, functional decomposition, look-up table, ordered binary decision diagram
27	Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt	Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap
27	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
27	Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu	Buffer design and optimization for lut-based structured ASIC design styles.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	structured asic, interconnection, buffer insertion
27	Taiga Takata, Yusuke Matsunaga	An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	FPGA, logic synthesis, technology mapping
27	Jason Cong, Kirill Minkovich	Improved SAT-based Boolean matching using implicants for LUT-based FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	logic synthesis, SAT, implicant, boolean matching, FPGA lookup table
27	Roberto Gutierrez, Javier Valls	Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.	FPL	2007	DBLP DOI BibTeX RDF
27	Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.	ASP-DAC	2006	DBLP DOI BibTeX RDF
27	Tsutomu Sasao, Jon T. Butler	Implementation of Multiple-Valued CAM Functions by LUT Cascades.	ISMVL	2006	DBLP DOI BibTeX RDF
27	Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer	LUT-based MPGAs for fast turnaround time conversion flow.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu	An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS.	DSD	2005	DBLP DOI BibTeX RDF
27	Chul-hyung Ryu, Sung-Woong Ra	A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT.	IWSOC	2005	DBLP DOI BibTeX RDF
27	Hao Li, Srinivas Katkoori, Wai-Kei Mak	Power minimization algorithms for LUT-based FPGA technology mapping.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	FPGA, technology mapping, power optimization, Delay minimization
27	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.	FPGA	2004	DBLP DOI BibTeX RDF
27	Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai	Testing and Diagnosis Techniques for LUT-Based FPGA's.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
27	Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe	FPGA-Efficient Hybrid LUT/CORDIC Architecture.	FPL	2004	DBLP DOI BibTeX RDF
27	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.	ISMVL	2004	DBLP DOI BibTeX RDF
27	Andrzej Krasniewski	Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs.	DFT	2004	DBLP DOI BibTeX RDF
27	Francisco Cardells-Tormo, Javier Valls-Coquillat	Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
27	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
27	Dylan Carline, Paul Coulton	A Novel Watermarking Technique for LUT Based FPGA Designs.	FPL	2002	DBLP DOI BibTeX RDF
27	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
27	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
27	Dylan Carline, Paul Coulton	Internet Authentication of LUT-Based FPGA Configuration Files.	IPDPS	2002	DBLP DOI BibTeX RDF	Configuration Files, FPGA, Authentication, Bitstream
27	Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda	High density bit-serial FPGA with LUT embedding shift register function.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
27	Guy G. Lemieux, David M. Lewis	Using sparse crossbars within LUT.	FPGA	2001	DBLP DOI BibTeX RDF
27	Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang	Power minization in LUT-based FPGA technology mapping.	ASP-DAC	2001	DBLP DOI BibTeX RDF
27	Javad Yavand-Hassani, Mahmoud Kamarei	A flexible method of LUT indexing in digital predistortion linearization of RF power amplifiers.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
27	Jian Qiao, Makoto Ikeda, Kunihiro Asada	Optimum Functional Decomposition for LUT-Based FPGA Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
27	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs.	FPL	2000	DBLP DOI BibTeX RDF
27	Chi-Chou Kao, Yen-Tai Lai	A routability and performance driven technology mapping algorithm for LUT based FPGA designs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
27	Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu 0001	A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
27	Jason Cong, Chang Wu	An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.	ICCD	1996	DBLP DOI BibTeX RDF
27	Jason Cong, Yuzheng Ding	On area/depth trade-off in LUT-based FPGA technology mapping.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
23	Cui-Xia Li, Wei-Ming Liu 0003, Yi Tang	A New 12-channel Hand-Held GPS Accelerator Design.	NCM	2009	DBLP DOI BibTeX RDF	GPS accelerator, DCO, Correlator, PLL, LUT
23	Solmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz	Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation.	ReConFig	2009	DBLP DOI BibTeX RDF	MixColumns, FPGA, architecture, AES, LUT
23	Élvio Dutra, Leandro Soares Indrusiak, Manfred Glesner	Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator.	SBCCI	2005	DBLP DOI BibTeX RDF	addressing scheme, gauss, noise generator, noise, lookup-table, normal distribution, white noise, LUT, transformation function, probability distribution function
22	Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt	Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.	FPL	2011	DBLP DOI BibTeX RDF	Tunable LUT circuit, FPGA, Run-time Reconfiguration, SRL, ICAP
22	Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM
22	Chen Dong 0003, Scott Chilstedt, Deming Chen	FPCNA: a field programmable carbon nanotube array.	FPGA	2009	DBLP DOI BibTeX RDF	cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
22	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	look-up table (LUT), FPGA, test, delay fault
21	Daesun Oh, Keshab K. Parhi	Low Complexity Decoder Architecture for Low-Density Parity-Check Codes.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Quasi-cyclic (QC) LDPC codes, Finite precision, Variable quantization, Sum-product algorithm (SPA), Highly-parallel decoding, Low complexity decoder architecture, Low-density parity check (LDPC) codes
21	Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox	FPGA technology mapping with encoded libraries andstaged priority cuts.	FPGA	2009	DBLP DOI BibTeX RDF	priority cuts, fpga, synthesis, technology mapping
21	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, architecture, cad
21	Sanjeev Kumar 0001, Christian Micheloni, Claudio Piciarelli, Gian Luca Foresti	Stereo Localization Based on Network's Uncalibrated Camera Pairs.	AVSS	2009	DBLP DOI BibTeX RDF
21	Tobi Vaudrey, Reinhard Klette	Fast Trilateral Filtering.	CAIP	2009	DBLP DOI BibTeX RDF
21	Sanjeev Kumar 0001, Christian Micheloni, Claudio Piciarelli	Stereo Localization Using Dual PTZ Cameras.	CAIP	2009	DBLP DOI BibTeX RDF
21	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
21	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Efficient synthesis of compressor trees on FPGAs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	Xing Wei, Juanjuan Chen, Qiang Zhou 0001, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
21	Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee	Boolean factoring and decomposition of logic networks.	ICCAD	2008	DBLP DOI BibTeX RDF
21	Somnath Paul, Swarup Bhunia	Reconfigurable computing using content addressable memory for improved performance and resource usage.	DAC	2008	DBLP DOI BibTeX RDF	field programmable gate array (FPGA), content addressable memory, resource utilization
21	Heesang Shin, Napoleon H. Reyes	Variable Colour Depth Look-Up Table Based on Fuzzy Colour Processing.	ICONIP (1)	2008	DBLP DOI BibTeX RDF
21	T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls	Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Fast Fourier Transform, digital circuits, digital communications
21	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A CAM Emulator Using Look-Up Table Cascades.	IPDPS	2007	DBLP DOI BibTeX RDF
21	Che-Hua Yang	An automatic on-line thin-film thickness monitoring technique.	SMC	2007	DBLP DOI BibTeX RDF
21	Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton	Combinational and sequential mapping with priority cuts.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Yu Zhou, Shijo Thekkel, Swarup Bhunia	Low power FPGA design using hybrid CMOS-NEMS approach.	ISLPED	2007	DBLP DOI BibTeX RDF	hybrid CMOS-NEMS, low power, FPGA design
21	Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Abu Baker, Soumik Ghosh, Ashok Kumar 0001, Magdy A. Bayoumi, Rafic A. Ayoubi	Design and Realization of Analog Phi-Function for LDPC Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Tomasz S. Czajkowski, Stephen Dean Brown	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.	DAC	2007	DBLP DOI BibTeX RDF
21	Tsutomu Sasao	Analysis and synthesis of weighted-sum functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF