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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 465 occurrences of 241 keywords
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Results
Found 842 publication records. Showing 835 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Walker H. Land, Frances R. Anderson, Tom Smith, Stephen Fahlbusch, Robert Choma, Lut Wong |
Applying knowledge engineering and representation methods to improve support vector machine and multivariate probabilistic neural network CAD performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Imaging: Image Processing ![In: Medical Imaging 2005: Image Processing, San Diego, California, United States, 12-17 February 2005, 2005, SPIE, 9780819457219. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land Jr., Mark J. Embrechts, Frances R. Anderson, Tom Smith, Lut Wong, Stephen Fahlbusch, Robert Choma |
Integrating knowledge representation/engineering, the multivariant PNN, and machine learning to improve breast cancer diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Data Mining, Intrusion Detection, Information Assurance, and Data Networks Security ![In: Data Mining, Intrusion Detection, Information Assurance, and Data Networks Security 2005, Orlando, Florida, USA, March 28-29, 2005, pp. 226-231, 2005, SPIE, 978-0-81945797-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Omowunmi Sadik, Walker H. Land Jr., Adam K. Wanekaya, Michiko Uematsu, Mark J. Embrechts, Lut Wong, Dale Leibensperger, Alex Volykin |
Detection and Classification of Organophosphate Nerve Agent Simulants Using Support Vector Machines with Multiarray Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Chem. Inf. Model. ![In: J. Chem. Inf. Model. 44(2), pp. 499-507, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land, Lut Wong, Daniel W. McKee, Timothy Masters, Frances R. Anderson, Anurag Raturi, Joseph Y. Lo |
New results in computer-aided diagnosis (CAD) of breast cancer using a recently developed SVM/GRNN Oracle hybrid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Imaging: Image Processing ![In: Medical Imaging 2004: Image Processing, San Diego, California, United States, 14-19 February 2004, 2004, SPIE, 9780819452832. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land Jr., Lut Wong, Daniel W. McKee, Mark J. Embrechts, Rizly Salih, Frances R. Anderson |
Applying Support Vector Machines to Breast Cancer Diagnosis using Screen Film Mammogram Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBMS ![In: 17th IEEE Symposium on Computer-Based Medical Systems (CBMS 2004), 24-25 June 2004, Bethesda, MD, USA, pp. 224-, 2004, IEEE Computer Society, 0-7695-2104-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land, Daniel W. McKee, Roberto Velazquez, Lut Wong, Joseph Y. Lo, Frances R. Anderson |
Application of support vector machines to breast cancer screening using mammogram and clinical history data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Imaging: Image Processing ![In: Medical Imaging 2003: Image Processing, San Diego, California, United States, 15-20 February 2003, 2003, SPIE, 9780819448330. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land Jr., Dale Leibensperger, Lut Wong, Omowunmi Sadik, A. Wanekeyab, Michiko Uematsu, Mark J. Embrechts |
New results using multi array sensors and support vector machines for the detection and classification of organophosphate nerve agents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: Washington, D.C., USA, 5-8 October 2003, pp. 2883-2888, 2003, IEEE, 0-7803-7952-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Walker H. Land Jr., Lut Wong, Daniel W. McKee, Timothy Masters, Frances R. Anderson |
Breast cancer computer aided diagnosis (CAD) using a recently developed SVM/GRNN Oracle hybrid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: Washington, D.C., USA, 5-8 October 2003, pp. 4705-4711, 2003, IEEE, 0-7803-7952-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan |
LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1804.11275, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
33 | Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan |
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 405-410, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
33 | Francisco-Javier Veredas, Hans-Jörg Pfleiderer |
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-2, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Van Viet Le |
Optimisation temporelle des réseaux programmables à base de LUT. (Performance Optimization for LUT-based programmable devices). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
32 | Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera |
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 122-123, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm |
32 | Ehsan Atoofian, Zainalabedin Navabi |
A Test Approach for Look-Up Table Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(1), pp. 141-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LUT testing, TPG with LE, BIST, memory testing, FPGA testing |
32 | Amit Chowdhary, John P. Hayes |
General technology mapping for field-programmable gate arrays based on lookup tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 1-32, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis |
32 | Tsutomu Sasao |
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 59-65, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
LUT-based FPGA, Multiple-valued logic function, Functional decomposition, Symmetric function |
32 | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
A multiplier generator for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 322-323, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs |
32 | Uwe Hinsberger, Reiner Kolla |
Optimal technology mapping for single output cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 14-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table |
31 | Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton |
SmartOpt: an industrial strength framework for logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 237-240, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
abc, blif, edge flow, smartopt, fpga, interface, technology mapping |
31 | Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko |
WireMap: FPGA technology mapping for improved routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 47-55, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
area flow, cut enumeration, edge flow, FPGA, technology mapping |
31 | Seydou-Nourou Ba, Khurram Waheed, Guo Tong Zhou |
Efficient spacing scheme for a linearly interpolated lookup table predistorter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1512-1515, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Wen-Ching Lin, Jun-Hong Chen, Ming-Der Shieh |
A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 464-467, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Dong Liang 0001, Edmund Y. Lam, George S. K. Fung |
Direct Reconstruction of Spiral Mri Using Least Squares Quantization Table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: Proceedings of the 2007 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, Washington, DC, USA, April 12-16, 2007, pp. 105-108, 2007, IEEE, 1-4244-0672-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 161-172, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
BIST, delay faults, look-up table |
31 | Guo Yu, Peng Li 0001 |
Lookup table based simulation and statistical modeling of Sigma-Delta ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1035-1040, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
statistical modeling, lookup table, Sigma-Delta |
31 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 3-23, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, technology mapping, CPLD, PLD |
31 | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001 |
A function generator-based reconfigurable system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 905-909, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit |
Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 77-82, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Fatih Kocan, Jason Meyer |
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 289-300, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson |
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 324-325, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao |
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 128-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Jason Cong, Yizhou Lin, Wangning Long |
SPFD-based global rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 77-84, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis |
31 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping for k/m-macrocell based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 51-59, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-Based FPGAs: Testing the Embedded RAM Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 159-167, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, RAM, iterative testing |
31 | Christian Legl, Bernd Wurth, Klaus Eckl |
Computing support-minimal subfunctions during functional decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 354-363, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Jordan S. Swartz, Vaughn Betz, Jonathan Rose |
A Fast Routability-Driven Router for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 140-149, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Hiroshi Sawada, Takayuki Suyama, Akira Nagoya |
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 353-358, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
support minimization, Boolean resubstitution, functional decomposition, look-up table, ordered binary decision diagram |
27 | Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt |
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 287, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap |
27 | Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu |
N-port memory mapping for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 279, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logical-to-physical mapping, n-port memory, fpga, hierarchy |
27 | Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu |
Buffer design and optimization for lut-based structured ASIC design styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 377-380, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
structured asic, interconnection, buffer insertion |
27 | Taiga Takata, Yusuke Matsunaga |
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 351-356, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, logic synthesis, technology mapping |
27 | Jason Cong, Kirill Minkovich |
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 139-147, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic synthesis, SAT, implicant, boolean matching, FPGA lookup table |
27 | Roberto Gutierrez, Javier Valls |
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 472-475, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic |
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2331-2340, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera |
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 110-111, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Tsutomu Sasao, Jon T. Butler |
Implementation of Multiple-Valued CAM Functions by LUT Cascades. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 11, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer |
LUT-based MPGAs for fast turnaround time conversion flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu |
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 122-126, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Chul-hyung Ryu, Sung-Woong Ra |
A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 405-409, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Hao Li, Srinivas Katkoori, Wai-Kei Mak |
Power minimization algorithms for LUT-based FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(1), pp. 33-51, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, technology mapping, power optimization, Delay minimization |
27 | Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006 |
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 247, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai |
Testing and Diagnosis Techniques for LUT-Based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 414-419, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe |
FPGA-Efficient Hybrid LUT/CORDIC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 933-937, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 302-308, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Andrzej Krasniewski |
Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 487-495, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Francisco Cardells-Tormo, Javier Valls-Coquillat |
Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 260-263, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Navin Vemuri, Priyank Kalla, Russell Tessier |
BDD-based logic synthesis for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 501-525, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, decomposition, logic synthesis, BDD |
27 | Dylan Carline, Paul Coulton |
A Novel Watermarking Technique for LUT Based FPGA Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 1152-1155, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland |
Implementing Asynchronous Circuits on LUT Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 36-46, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Andrzej Krasniewski |
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 616-626, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Dylan Carline, Paul Coulton |
Internet Authentication of LUT-Based FPGA Configuration Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Configuration Files, FPGA, Authentication, Bitstream |
27 | Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda |
High density bit-serial FPGA with LUT embedding shift register function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 475-480, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Guy G. Lemieux, David M. Lewis |
Using sparse crossbars within LUT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 59-68, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang |
Power minization in LUT-based FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 635-640, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Javad Yavand-Hassani, Mahmoud Kamarei |
A flexible method of LUT indexing in digital predistortion linearization of RF power amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 53-56, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
Optimum Functional Decomposition for LUT-Based FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 555-564, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Andrzej Krasniewski |
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 675-684, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Chi-Chou Kao, Yen-Tai Lai |
A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 474-477, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu 0001 |
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. I ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume I, pp. 828-831, 1996, Springer, 3-540-61626-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Jason Cong, Chang Wu |
An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 572-578, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Jason Cong, Yuzheng Ding |
On area/depth trade-off in LUT-based FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 137-148, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Cui-Xia Li, Wei-Ming Liu 0003, Yi Tang |
A New 12-channel Hand-Held GPS Accelerator Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM ![In: International Conference on Networked Computing and Advanced Information Management, NCM 2009, Fifth International Joint Conference on INC, IMS and IDC: INC 2009: International Conference on Networked Computing, IMS 2009: International Conference on Advanced Information Management and Service, IDC 2009: International Conference on Digital Content, Multimedia Technology and its Applications, Seoul, Korea, August 25-27, 2009, pp. 1705-1708, 2009, IEEE Computer Society, 978-0-7695-3769-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
GPS accelerator, DCO, Correlator, PLL, LUT |
23 | Solmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz |
Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 219-224, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MixColumns, FPGA, architecture, AES, LUT |
23 | Élvio Dutra, Leandro Soares Indrusiak, Manfred Glesner |
Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 242-247, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
addressing scheme, gauss, noise generator, noise, lookup-table, normal distribution, white noise, LUT, transformation function, probability distribution function |
22 | Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt |
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 171-176, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Tunable LUT circuit, FPGA, Run-time Reconfiguration, SRL, ICAP |
22 | Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat |
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 8:1-8:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM |
22 | Chen Dong 0003, Scott Chilstedt, Deming Chen |
FPCNA: a field programmable carbon nanotube array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 161-170, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics |
22 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 43-55, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
look-up table (LUT), FPGA, test, delay fault |
21 | Daesun Oh, Keshab K. Parhi |
Low Complexity Decoder Architecture for Low-Density Parity-Check Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(2-3), pp. 217-228, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Quasi-cyclic (QC) LDPC codes, Finite precision, Variable quantization, Sum-product algorithm (SPA), Highly-parallel decoding, Low complexity decoder architecture, Low-density parity check (LDPC) codes |
21 | Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox |
FPGA technology mapping with encoded libraries andstaged priority cuts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 143-150, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
priority cuts, fpga, synthesis, technology mapping |
21 | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose |
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 133-142, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, architecture, cad |
21 | Sanjeev Kumar 0001, Christian Micheloni, Claudio Piciarelli, Gian Luca Foresti |
Stereo Localization Based on Network's Uncalibrated Camera Pairs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AVSS ![In: Sixth IEEE International Conference on Advanced Video and Signal Based Surveillance, AVSS 2009, 2-4 September 2009, Genova, Italy, pp. 502-507, 2009, IEEE Computer Society, 978-0-7695-3718-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Tobi Vaudrey, Reinhard Klette |
Fast Trilateral Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP ![In: Computer Analysis of Images and Patterns, 13th International Conference, CAIP 2009, Münster, Germany, September 2-4, 2009. Proceedings, pp. 541-548, 2009, Springer, 978-3-642-03766-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Sanjeev Kumar 0001, Christian Micheloni, Claudio Piciarelli |
Stereo Localization Using Dual PTZ Cameras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP ![In: Computer Analysis of Images and Patterns, 13th International Conference, CAIP 2009, Münster, Germany, September 2-4, 2009. Proceedings, pp. 1061-1069, 2009, Springer, 978-3-642-03766-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal |
Architecture-specific packing for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 5-13, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing |
21 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
Efficient synthesis of compressor trees on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 138-143, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Xing Wei, Juanjuan Chen, Qiang Zhou 0001, Yici Cai, Jinian Bian, Xianlong Hong |
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 559-562, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee |
Boolean factoring and decomposition of logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 38-44, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Somnath Paul, Swarup Bhunia |
Reconfigurable computing using content addressable memory for improved performance and resource usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 786-791, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
field programmable gate array (FPGA), content addressable memory, resource utilization |
21 | Heesang Shin, Napoleon H. Reyes |
Variable Colour Depth Look-Up Table Based on Fuzzy Colour Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (1) ![In: Advances in Neuro-Information Processing, 15th International Conference, ICONIP 2008, Auckland, New Zealand, November 25-28, 2008, Revised Selected Papers, Part I, pp. 1071-1078, 2008, Springer, 978-3-642-02489-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls |
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(2), pp. 183-187, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Fast Fourier Transform, digital circuits, digital communications |
21 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A CAM Emulator Using Look-Up Table Cascades. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Che-Hua Yang |
An automatic on-line thin-film thickness monitoring technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Montréal, Canada, 7-10 October 2007, pp. 3001-3005, 2007, IEEE, 978-1-4244-0990-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton |
Combinational and sequential mapping with priority cuts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 354-361, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Yu Zhou, Shijo Thekkel, Swarup Bhunia |
Low power FPGA design using hybrid CMOS-NEMS approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 14-19, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hybrid CMOS-NEMS, low power, FPGA design |
21 | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu |
Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1049-1052, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Abu Baker, Soumik Ghosh, Ashok Kumar 0001, Magdy A. Bayoumi, Rafic A. Ayoubi |
Design and Realization of Analog Phi-Function for LDPC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1661-1664, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Tomasz S. Czajkowski, Stephen Dean Brown |
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 324-329, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Tsutomu Sasao |
Analysis and synthesis of weighted-sum functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), pp. 789-796, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin |
State-holding in Look-Up Tables: application to asynchronous logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 12-17, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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