Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
41	E. M. Boehm, Thomas B. Steel Jr.	The Share 709 System: Machine Implementation of Symbolic Programming.	J. ACM	1959	DBLP DOI BibTeX RDF
40	Eren Küren, Akin Cellatoglu	Education Over Homogenous Network.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF	CBA, HCI, E-Learning
40	Ghassan Shobaki, Kent D. Wilken, Mark Heffernan	Optimal trace scheduling using enumeration.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	branch-and-bound enumeration, global instruction scheduling, optimal instruction scheduling, compiler optimizations, instruction-level parallelism, Instruction scheduling, trace scheduling
39	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
39	Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero	Evaluating kilo-instruction multiprocessors.	WMPI	2004	DBLP DOI BibTeX RDF	ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors
39	Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann 0002, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr	Instruction encoding synthesis for architecture exploration using hierarchical processor models.	DAC	2003	DBLP DOI BibTeX RDF	instruction set architectures, instruction encoding
39	Kanad Ghose	Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	instruction dispatching, instruction issue, window buffer, superscalar processor, power minimization
39	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
39	Toshinori Sato	Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.	EUROMICRO	1998	DBLP DOI BibTeX RDF	dynamic speculation of data dependence, instruction reissue, instruction level parallelism, out-of-order execution, address prediction
39	Nael B. Abu-Ghazaleh, Philip A. Wilsey, Xianzhi Fan, Debra A. Hensgen	Synthesizing Variable Instruction Issue Interpreters for Implementing Functional Parallelism on SIMD Computers.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	MIMD on SIMD, variable instruction issue, scheduling instruction execution, interpretation, SIMD computers
39	Tai M. Chung, Henry G. Dietz	Static scheduling of hard real-time code with instruction-level timing accuracy.	RTCSA	1996	DBLP DOI BibTeX RDF	timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
39	Frank Mueller 0001, David B. Whalley	Fast instruction cache analysis via static cache simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	instruction cache analysis, static cache simulation, cache configuration, instruction reference, cache hit, counter incrementation, code execution frequency, local state information updating, frequency counters, program exit, virtual machines, cache storage, program diagnostics, dynamic simulation, cache miss
39	Kjell Näckros	Learning Security through Computer Games: Studying user behavior in a real-world situation.	World Conference on Information Security Education	2007	DBLP DOI BibTeX RDF	ICT Security, Game-Based Instruction, GBI, GBL, Vital Security Functions, VSF, Linear instruction, Nonlinear instruction, Education, Computer Games, Knowledge, Game-Based Learning, Learning preferences
39	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS (1)	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
38	Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya	ReCode: the design and re-design of the instruction codes for embedded instruction-set processors.	ED&TC	1997	DBLP DOI BibTeX RDF
38	Yen-Jen Chang	Exploiting frequent opcode locality for power efficient instruction cache.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	frequent opcode locality, instruction cache, power-efficient
38	Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic	Application specific forwarding network and instruction encoding for multi-pipe ASIPs.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-pipe ASIP, VLIW, forwarding, instruction encoding
38	Wan-Chih Sun, Tsung-Ren Yang, Chih-Chin Liang, Ping-Yu Hsu 0001, Yuh-Wei Kung	The Effects of Computer Assisted Instruction to Train People with Reading Disabilities Recognizing Chinese Characters.	ICCPOL	2006	DBLP DOI BibTeX RDF	Reading Disabilities, Recognition of Chinese Characters, Stem-Deriving Instruction, Education, Interactive Learning Environment
38	Martha Mercaldi, Steven Swanson, Andrew Petersen 0001, Andrew Putnam, Andrew Schwerin, Mark Oskin, Susan J. Eggers	Instruction scheduling for a tiled dataflow architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	instruction scheduling, dataflow, tiled architectures
38	Mehrdad Reshadi, Prabhat Mishra 0001	Memory access optimizations in instruction-set simulators.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	memory address-space mapping, instruction-set simulator
38	Junwei Zhou, Andrew J. Mason	Increasing design space of the instruction queue with tag coding.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	instruction queue, wakeup/select loop
38	Bramha Allu, Wei Zhang 0002	Static next sub-bank prediction for drowsy instruction cache.	CASES	2004	DBLP DOI BibTeX RDF	compiler, instruction cache, leakage energy
38	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Tiny instruction caches for low power embedded systems.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	embedded systems., fixed program, low power, instruction cache, low energy, architecture tuning, Loop cache, filter cache
38	Haiyong Xie 0001, Li Zhao 0002, Laxmi N. Bhuyan	Architectural analysis and instruction-set optimization for design of network protocol processors.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	instruction optimization, architecture simulation, network processing, TCP/IP protocol
38	Alvin R. Lebeck, Tong Li 0003, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan	A Large, Fast Instruction Window for Tolerating Cache Misses.	ISCA	2002	DBLP DOI BibTeX RDF	Cache Memory, Memory Latency, Latency Tolerance, Instruction Window
38	Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon	Bounding Pipeline and Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache
38	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP DOI BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
37	Hai Lin 0004, Yunsi Fei	Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency.	DATE	2008	DBLP DOI BibTeX RDF
37	Newton Cheung, Sri Parameswaran, Jörg Henkel	Battery-aware instruction generation for embedded processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
37	Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang 0003, John Paul Shen	Hardware Support for Prescient Instruction Prefetch.	HPCA	2004	DBLP DOI BibTeX RDF
37	Jingren Zhou, Kenneth A. Ross	Buffering Database Operations for Enhanced Instruction Cache Performance.	SIGMOD Conference	2004	DBLP DOI BibTeX RDF
37	André Seznec, Antony Fraboulet	Effective ahead Pipelining of Instruction Block Address Generation.	ISCA	2003	DBLP DOI BibTeX RDF
37	Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak	Branch History Guided Instruction Prefetching.	HPCA	2001	DBLP DOI BibTeX RDF
37	Timothy Sherwood, Brad Calder	Patchable instruction ROM architecture.	CASES	2001	DBLP DOI BibTeX RDF
37	Juan E. Gilbert, Chia Y. Han 0001	Researching Adaptive Instruction.	AH	2000	DBLP DOI BibTeX RDF
37	Toshinori Sato, Itsujiro Arita	Comprehensive Evaluation of an Instruction Reissue Mechanism.	ISPAN	2000	DBLP DOI BibTeX RDF
37	Jim Pierce, Trevor N. Mudge	Wrong-path Instruction Prefetching.	MICRO	1996	DBLP DOI BibTeX RDF
37	Ing-Jer Huang, Alvin M. Despain	Synthesis of application specific instruction sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
37	Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer	Instruction Fetching: Coping with Code Bloat.	ISCA	1995	DBLP DOI BibTeX RDF
37	Matthew K. Farrens, Andrew R. Pleszkun	Improving Performance of Small On-Chip Instruction Caches.	ISCA	1989	DBLP DOI BibTeX RDF
37	Gurindar S. Sohi, Sriram Vajapeyam	Tradeoffs in Instruction Format Design for Horizontal Architectures.	ASPLOS	1989	DBLP DOI BibTeX RDF
37	Xianglong Huang, Stephen M. Blackburn, David Grove, Kathryn S. McKinley	Fast and efficient partial code reordering: taking advantage of dynamic recompilatior.	ISMM	2006	DBLP DOI BibTeX RDF	locality, dynamic, instruction, JIT compilation
37	Weiyu Tang, Rajesh K. Gupta 0001, Alexandru Nicolau	Power Savings in Embedded Processors through Decode Filer Cache.	DATE	2002	DBLP DOI BibTeX RDF
37	Michael C. Huang 0001, Jose Renau, Josep Torrellas	Energy-efficient hybrid wakeup logic.	ISLPED	2002	DBLP DOI BibTeX RDF	wakeup logic, low power, issue logic
37	Yi-Shin Tung, Chia-Chiang Ho, Ja-Ling Wu	MMX-Based DCT and MC Algorithms for Real-Time Pure Software MPEG Decoding.	ICMCS, Vol. 1	1999	DBLP DOI BibTeX RDF	Pattern-Based IDCT, MPEG, Video Compression, MMX
36	Conrad Mueller	Can Multicore Processing Learn from Arithmetic Concepts?.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
36	David C. Wyld	Blogging from the Top: A Survey of Higher Education Leaders' Use of Web 2.0 Technologies.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
36	Ioana Tuugalei Chan Mow	Issues and Difficulties in Teaching Novice Computer Programming.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
35	Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin	Instruction packing: Toward fast and energy-efficient instruction scheduling.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	instruction packing, low power, Issue queue
35	Yi Zhang, Steve Haga, Rajeev Barua	Execution History Guided Instruction Prefetching.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	hardware prefetching, instruction cache, memory latency, instruction prefetching
35	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez	Toward kilo-instruction processors.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors
35	Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.	DAC	2004	DBLP DOI BibTeX RDF	16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density
35	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
35	Nicola Zingirian, Massimo Maresca	Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures.	CAMP	2000	DBLP DOI BibTeX RDF	loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming
35	Hidehiko Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
35	Chandra Chekuri, Richard Johnson, Rajeev Motwani 0001, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.	MICRO	1996	DBLP DOI BibTeX RDF	linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling
35	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cache modeling for real-time software: beyond direct mapped instruction caches.	RTSS	1996	DBLP DOI BibTeX RDF	direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system
35	Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu	A study of the effects of compiler-controlled speculation on instruction and data caches.	HICSS (1)	1995	DBLP DOI BibTeX RDF	compiler-controlled speculation, nonnumeric programs, speculatively scheduled code, aggressive speculation models, scheduling, performance evaluation, parallel programming, time, instruction level parallelism, program compilers, data caches, cache storage, instruction cache, cache misses, performance results
35	Raymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu	Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution.	MICRO	1994	DBLP DOI BibTeX RDF	MIPS R8000, global instruction distribution, multiple-issue processors, processor resource utilization, MIPS R8000, instruction scheduling, code optimization
35	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors.	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
35	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
35	Guido Araujo, Sharad Malik	Optimal code generation for embedded memory non-homogeneous register architectures.	ISSS	1995	DBLP DOI BibTeX RDF	TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation
35	Chuan-Yu Wang, Kaushik Roy 0001	Control unit synthesis targeting low-power processors.	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
34	Hai Lin 0004, Yunsi Fei	Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives.	ISLPED	2010	DBLP DOI BibTeX RDF	asips, multi-objective design
34	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
34	Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt	Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures.	MICRO	1996	DBLP DOI BibTeX RDF
34	Hsiu-Ling Chen	Internet Self-efficacy and Behavior in Integrating the Internet into Instruction: A Study of Vocational High School Teachers in Taiwan.	EC-TEL	2009	DBLP DOI BibTeX RDF	Internet self-efficacy, integrating the Internet into instruction, vocational high school teachers
34	Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton	Instruction set simulator generation using HARMLESS, a new hardware architecture description language.	SimuTools	2009	DBLP DOI BibTeX RDF	hardware architecture description language, instruction set simulation
34	Chris Riley, Graham Johnson, Heather McCracken, Ahmed Al-Saffar	Instruction, Feedback and Biometrics: The User Interface for Fingerprint Authentication Systems.	INTERACT (2)	2009	DBLP DOI BibTeX RDF	Biometrics, Feedback, Fingerprint, Instruction
34	Sonja Stork, Christian Stößel, Anna Schubö	The Influence of Instruction Mode on Reaching Movements during Manual Assembly.	USAB	2008	DBLP DOI BibTeX RDF	Instruction presentation, motor behavior, augmented reality, human performance, information processing
34	Christoph Puttmann, Jamshid Shokrollahi, Mario Porrmann	Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography.	ITNG	2008	DBLP DOI BibTeX RDF	binary field multiplication, elliptic curve cryptography, instruction set extension, resource efficiency
34	Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham	Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems.	LCTES	2007	DBLP DOI BibTeX RDF	source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, customizable processors
34	Martha Mercaldi, Steven Swanson, Andrew Petersen 0001, Andrew Putnam, Andrew Schwerin, Mark Oskin, Susan J. Eggers	Modeling instruction placement on a spatial architecture.	SPAA	2006	DBLP DOI BibTeX RDF	instruction placement, dataflow, spatial computing
34	Aneesh Aggarwal, Manoj Franklin	Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	instruction replication, interconnection latency, load balancing, task assignment, Clustered processors
34	Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin	Instruction packing: reducing power and delay of the dynamic scheduling logic.	ISLPED	2005	DBLP DOI BibTeX RDF	instruction packing, low power, issue queue
34	Phillip A. Laplante, William Gilreath	One Instruction Set Computers for Image Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	OISC, one-instruction computing, FPGA, field programmable gate array, image processing, reconfigurable computing
34	Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies	Feedback driven instruction-set extension.	LCTES	2004	DBLP DOI BibTeX RDF	simulator generation, encryption, network processor, codesign, instruction-set extensions, compiler generation
34	Michael Scherger, Johnnie W. Baker, Jerry L. Potter	Multiple Instruction Stream Control for an Associative Model of Parallel Computation.	IPDPS	2003	DBLP DOI BibTeX RDF	Multiple instruction streams, associative computing, parallel processing, system software
34	Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt	A Scalable Instruction Queue Design Using Dependence Chains.	ISCA	2002	DBLP DOI BibTeX RDF	Instruction Queue, Dependence Chains, Variable-latency, Scheduling, Scalable, Segment
34	Chi-Keung Luk, Todd C. Mowry	Architectural and compiler support for effective instruction prefetching: a cooperative approach.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	compiler optimization, instruction prefetching
34	Francisco Barat, Rudy Lauwereins	Reconfigurable Instruction Set Processors: A Survey.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	dynamically reconfigurable instruction set processor, reconfigurable functional unit, application specific instructions, reconfigurable computing
34	Austin Kim, J. Morris Chang	Advanced POC Model-Based Java Instruction Folding Mechanism.	EUROMICRO	2000	DBLP DOI BibTeX RDF	Instruction Folding, Java Virtual Machine (JVM), Stack, Java processor, Java bytecode, Java programming language
34	Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang	Instruction selection using binate covering for code size optimization.	ICCAD	1995	DBLP DOI BibTeX RDF	code generation, digital signal processors, instruction selection
34	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
34	Andrei Sergeevich Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
34	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
34	Allen Leung, Krishna V. Palem, Amir Pnueli	A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
34	Heidrun Engel	Data flow transformations to detect results which are corrupted by hardware faults.	HASE	1996	DBLP DOI BibTeX RDF	data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection
33	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
33	Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato	Indirect Tag Search Mechanism for Instruction Window Energy Reduction.	CIT	2007	DBLP DOI BibTeX RDF
33	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
33	Subash Chandar G., Mahesh Mehendale, R. Govindarajan	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	embedded DSP systems, re-configurable architecture, code compression, energy reduction
33	Lawrence Spracklen, Yuan Chou, Santosh G. Abraham	Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications.	HPCA	2005	DBLP DOI BibTeX RDF
33	Shu Xiao 0001, Edmund Ming-Kit Lai	Instruction scheduling of VLIW architectures for balanced power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Custom-instruction synthesis for extensible-processor platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
33	Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu	Decomposition of Instruction Decoder for Low Power Design.	DATE	2004	DBLP DOI BibTeX RDF
33	Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin	Exploring Wakeup-Free Instruction Scheduling.	HPCA	2004	DBLP DOI BibTeX RDF
33	Matthias Grünewald, Dinh Khoi Le, Uwe Kastens, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert 0001, Adrian Slowik, Michael Thies	Network Application Driven Instruction Set Extensions for Embedded Processing Clusters.	PARELEC	2004	DBLP DOI BibTeX RDF
33	Miroslav N. Velev	Efficient formal verification of pipelined processors with instruction queues.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	logic of equality, positive equality, decomposition, SAT
33	Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Dz-Ching Ju	Efficient Resource Management during Instruction Scheduling for the EPIC Architecture.	IEEE PACT	2003	DBLP DOI BibTeX RDF