Search results for "memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Said Hamdioui, Ad J. van de Goor, Mike Rodgers	Detecting Intra-Word Faults in Word-Oriented Memories.	VTS	2003	DBLP DOI BibTeX RDF	Bit-oriented/word-oriented memories, fault models, memory tests, data backgrounds
29	Michael Neve, Eric Peeters, David Samyde, Jean-Jacques Quisquater	Memories: A Survey of Their Secure Uses in Smart Cards.	IEEE Security in Storage Workshop	2003	DBLP DOI BibTeX RDF	Secure memories, Smart cards, Tamper resistance, Side channels, Secure hardware
29	Piero Olivo, Marcello Dalpasso	A Bist Scheme for Non-Volatile Memories.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	off-line testing, built-in self-test, signature analysis, non-volatile memories
29	Gang-Min Park, Hoon Chang	An extended march test algorithm for embedded memories.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	efficient test algorithm, BIST architecture, neighborhood pattern sensitive fault, background data, word-oriented memory testing, extended march test algorithm, stuck-at fault, transition fault, embedded memories, integrated memory circuits, coupling fault
29	Anelise P. Braga, Marcelo Barros de Almeida, G. Pereita, Marcelo Azevedo Costa, C. Barbose	On the information storage of associative matrix memories.	SBRN	1997	DBLP DOI BibTeX RDF	associative matrix memories, Willshaw matrix model, linear matrix memory, autoassociative networks, heteroassociative networks, neural networks, neural nets, generalisation, network connectivity, information storage, storage capacity
28	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
28	Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha	Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.	DAC	2010	DBLP DOI BibTeX RDF	data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory
28	Israel Román-Godínez, Itzamá López-Yáñez, Cornelio Yáñez-Márquez	Classifying Patterns in Bioinformatics Databases by Using Alpha-Beta Associative Memories.	Biomedical Data and Applications	2009	DBLP DOI BibTeX RDF
28	Concepción Sanz, Manuel Prieto 0001, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor	System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.	ASP-DAC	2009	DBLP DOI BibTeX RDF
28	Zhigang Zeng, Jun Wang 0002	Design and Analysis of High-Capacity Associative Memories Based on a Class of Discrete-Time Recurrent Neural Networks.	IEEE Trans. Syst. Man Cybern. Part B	2008	DBLP DOI BibTeX RDF
28	Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang	A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC)
28	Tatsuyuki Kawamura, Tomohiro Fukuhara, Hideaki Takeda 0001, Yasuyuki Kono, Masatsugu Kidode	Ubiquitous Memories: a memory externalization system using physical objects.	Pers. Ubiquitous Comput.	2007	DBLP DOI BibTeX RDF
28	Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli	Evaluation of design for reliability techniques in embedded flash memories.	DATE	2007	DBLP DOI BibTeX RDF
28	Cornelio Yáñez-Márquez, María Elena Cruz-Meza, Flavio Arturo Sánchez-Garfias, Itzamá López-Yáñez	Using Alpha-Beta Associative Memories to Learn and Recall RGB Images.	ISNN (3)	2007	DBLP DOI BibTeX RDF
28	Zöhre Kara Kayikci, Heiner Markert, Günther Palm	Neural Associative Memories and Hidden Markov Models for Speech Recognition.	IJCNN	2007	DBLP DOI BibTeX RDF
28	Yasuaki Kuroe, Yuriko Taniguchi	Models of Orthogonal Type Complex-Valued Dynamic Associative Memories and Their Performance Comparison.	ICANN (1)	2007	DBLP DOI BibTeX RDF
28	Yasuaki Kuroe, Yuriko Taniguchi	Models of Self-Correlation Type Complex-Valued Associative Memories and Their Performance Comparison.	IJCNN	2006	DBLP DOI BibTeX RDF
28	Yasuaki Kuroe, Yuriko Taniguchi	Models of Self-correlation Type Complex-Valued Associative Memories and Their Dynamics.	ICANN (1)	2005	DBLP DOI BibTeX RDF
28	Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh	A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
28	Lars Wehmeyer, Urs Helmig, Peter Marwedel	Compiler-optimized usage of partitioned memories.	WMPI	2004	DBLP DOI BibTeX RDF
28	Masumi Shimizu, Mie Nakatani, Hirokazu Kato 0001, Shogo Nishida	Communication environment for sharing fond memories.	Advances in Computer Entertainment Technology	2004	DBLP DOI BibTeX RDF	joint-remenbering, popular music, reminiscence, park
28	Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke	Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.	ASAP	2004	DBLP DOI BibTeX RDF
28	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
28	Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee 0001	At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF
28	Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001	A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.	MTDT	2003	DBLP DOI BibTeX RDF
28	Max H. Garzon, Andrew Neel, Hui Chen	Efficiency and Reliability of DNA-Based Memories.	GECCO	2003	DBLP DOI BibTeX RDF
28	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
28	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
28	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
28	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne	Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.	MTDT	2000	DBLP DOI BibTeX RDF
28	Peter Sussner	Fixed Points of Autoassociative Morphological Memories.	IJCNN (5)	2000	DBLP DOI BibTeX RDF
28	Vivek Chickermane, Scott Richter, Carl Barnhart	Integrating Logic BIST in VLSI Designs with Embedded Memories.	VTS	2000	DBLP DOI BibTeX RDF
28	Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith	MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design.	ASPLOS	2000	DBLP DOI BibTeX RDF
28	Said Hamdioui, Ad J. van de Goor	March Tests for Word-Oriented Two-Port Memories.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
28	Ismail Salih, Stanley H. Smith, Derong Liu 0001	Design of bidirectional associative memories based on the perceptron training technique.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
28	E. Kofi Vida-Torku, George Joos	Designing for scan test of high performance embedded memories.	ITC	1998	DBLP DOI BibTeX RDF
28	Jos van Sas, Francky Catthoor, Hugo De Man	Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
27	Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante	Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
26	Joohee Kim, Marios C. Papaefthymiou	Constant-load energy recovery memory for efficient high-speed operation.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
26	Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Energy recovering static memory.	ISLPED	2002	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
26	P. Bruce Berra, Arif Ghafoor, Pericles A. Mitkas, Slawomir J. Marcinkowski, Mohsen Guizani	The Impact of Optics on Data and Knowledge Base Systems.	IEEE Trans. Knowl. Data Eng.	1989	DBLP DOI BibTeX RDF	optical database machines, optical knowledge base machines, optical disks, page-oriented holographic memories, optical content addressable memories, full text processing, optical processing, digital optical device development, knowledge base systems, knowledge based systems, database management systems, interconnection, processing, storage, database systems, optical interconnection, data communication, optics, optical information processing, optoelectronic, optical storage
26	Charles L. Seitz	Concurrent VLSI Architectures.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Computational arrays, logic-enhanced memories, microcomputer arrays, smart memories, parallel processing, VLSI, multiprocessors, systolic arrays, concurrent computation
26	Jeffrey J. Rothschild	Cache organizations.	ACM Southeast Regional Conference	1979	DBLP DOI BibTeX RDF	Buffer memories, computer architecture, cache memories, paging, memory organization
26	DeWitt Landis	Multiple-Response Resolution in Associative Systems.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Associative memories (AM's), associative processors (AP's), Fibonacci series, multiple-response resolution, priority determination, response resolution, content-addressed memories
25	Heiner Markert, Zöhre Kara Kayikci, Günther Palm	Sentence Understanding and Learning of New Words with Large-Scale Neural Networks.	ANNPR	2008	DBLP DOI BibTeX RDF	Hidden Markov Models, Speech Recognition, Associative Memories, Hebbian Learning, Language Understanding
25	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010	Thermal modeling and management of DRAM memory systems.	ISCA	2007	DBLP DOI BibTeX RDF	thermal management, thermal modeling, DRAM memories
25	Molly M. Stevens, Gregory D. Abowd, Khai N. Truong, Florian Vollmer	Getting into the Living Memory Box: Family archives & holistic design.	Pers. Ubiquitous Comput.	2003	DBLP DOI BibTeX RDF	Family memories, Multimedia organisation, Ubiquitous computing, Industrial design, Focus groups, Domestic technology, Ethnographic studies, Home appliances
25	Said Hamdioui, Ad J. van de Goor	Efficient Tests for Realistic Faults in Dual-Port SRAMs.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Multiport/single-port memories, weak faults, fault models, fault coverage, march tests
25	Nigel J. Duffy, Arun K. Jagota	Connectionist Password Quality Tester.	IEEE Trans. Knowl. Data Eng.	2002	DBLP DOI BibTeX RDF	spurious memories, edit distance, Hopfield networks, string searching
25	Emílio Del Moral Hernandez	Studying Neural Networks of Bifurcating Recursive Processing Elements - Quantitative Methods for Architecture Design and Performance Analysis.	IWANN (1)	2001	DBLP DOI BibTeX RDF	design of neural architectures, parametric recursive processing elements, bifurcation and chaos, associative memories, chaotic neural networks, non-linear dynamics
25	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
25	Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy	Built In Self Test for Ring Addressed FIFOs with Transparent Latches.	MTDT	1999	DBLP DOI BibTeX RDF	Built In Self Test, Memory testing, Embedded memories
25	Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
24	Shruti Vyas, Aswin Sreedhar, Sandip Kundu	TURBONFS: turbo nand flash search.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	signature, aliasing, NAND flash, MISR
24	Pedro Reviriego, Juan Antonio Maestro	Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	high-level protection technique, protection against radiation, error correcting codes, Fault tolerant memory
24	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
24	Ross McIlroy, Peter Dickman, Joe Sventek	Efficient dynamic heap allocation of scratch-pad memory.	ISMM	2008	DBLP DOI BibTeX RDF	on-core memory, concurrency, memory management
24	Torvald Riegel, Christof Fetzer, Pascal Felber	Time-based transactional memory with scalable time bases.	SPAA	2007	DBLP DOI BibTeX RDF	transactional memory
24	Alfred Kölbl, Jerry R. Burch, Carl Pixley	Memory Modeling in ESL-RTL Equivalence Checking.	DAC	2007	DBLP DOI BibTeX RDF
24	Fan R. K. Chung, Ronald L. Graham, Jia Mao, George Varghese	Parallelism versus Memory Allocation in Pipelined Router Forwarding Engines.	Theory Comput. Syst.	2006	DBLP DOI BibTeX RDF
24	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001	Automatic memory reductions for RTL model verification.	ICCAD	2006	DBLP DOI BibTeX RDF
24	Jana Stanclová	The Associative Recall of Spatial Correlated Patterns.	CIARP	2006	DBLP DOI BibTeX RDF
24	Akhil Garg 0001, Prashant Dubey	Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.	DFT	2006	DBLP DOI BibTeX RDF	Compression and Yield, Memory, Repair, Fuse
24	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Automatic March Tests Generation for Multi-Port SRAMs.	DELTA	2006	DBLP DOI BibTeX RDF
24	Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian	Challenges in Embedded Memory Design and Test.	DATE	2005	DBLP DOI BibTeX RDF
24	Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown	Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.	CGO	2005	DBLP DOI BibTeX RDF
24	R. Chandramouli	Managing Test and Repair of Embedded Memory Subsystem in SoC.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
24	Antonis Hondroulis, Costas Harizakis, Peter Triantafillou	Optimal Cache Memory Exploitation for Continuous Media: To Cache or to Prefetch?	Multim. Tools Appl.	2004	DBLP DOI BibTeX RDF	simulation, modeling, caching, statistical analysis, prefetching, video streams, multimedia servers
24	Dalia Dagher, Iyad Ouaiss	Storage Allocation for Diverse FPGA Memory Specifications.	FPL	2004	DBLP DOI BibTeX RDF
24	Fan R. K. Chung, Ronald L. Graham, George Varghese	Parallelism versus memory allocation in pipelined router forwarding engines.	SPAA	2004	DBLP DOI BibTeX RDF	approximation algorithm, memory allocation
24	Shyue-Kung Lu	A Novel Built-In Self-Repair Approach for Embedded RAMs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	divided word line, fault tolerance, redundancy, low power design, embedded memory
24	Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang 0002, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer	Compiler-Directed Management of Instruction Accesses.	DSD	2003	DBLP DOI BibTeX RDF
24	Adnan Aziz, Amit Prakash, Vijaya Ramachandran	A near optimal scheduler for switch-memory-switch routers.	SPAA	2003	DBLP DOI BibTeX RDF	schedulers, parallelism, matching, randomization, routers
24	Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu	Flash Memory Built-In Self-Test Using March-Like Algorithm.	DELTA	2002	DBLP DOI BibTeX RDF
24	Mohammad Gh. Mohammad, Kewal K. Saluja	Flash Memory Disturbances: Modeling and Test.	VTS	2001	DBLP DOI BibTeX RDF
24	Alain Gefflaut, Christine Morin, Michel Banâtre	Tolerating node failures in cache only memory architectures.	SC	1994	DBLP DOI BibTeX RDF
24	Om P. Agrawal, Arthur V. Pohm	Cache memory systems for multiprocessor architecture.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
23	Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli	Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories.	ETS	2008	DBLP DOI BibTeX RDF	NOR flash memories, reliabilty management, markov modeling
23	Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Applying March Tests to K-Way Set-Associative Cache Memories.	ETS	2008	DBLP DOI BibTeX RDF	cache memories, memory test, march test
23	Roberto Antonio Vázquez, Juan Humberto Sossa Azuela	Hetero-Associative Memories for Voice Signal and Image Processing.	CIARP	2008	DBLP DOI BibTeX RDF	voice signal processing, image processing, Associative memories
23	Albert Fornells, Eva Armengol, Elisabet Golobardes	Retrieval Based on Self-explicative Memories.	ECCBR	2008	DBLP DOI BibTeX RDF	Case Retrieval, Case Memory Organization, Self-Explicative Memories, Soft Case-Based Reasoning, Self-Organizing Map
23	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IEEE P1500, diagnosis, Hough transform, embedded memories
23	Tang-Ho Lê, Luc Lamontagne, Tho-Hau Nguyen	A Visual Tool for Structuring and Modeling Organizational Memories.	CIKM	2000	DBLP DOI BibTeX RDF	domain knowledge structure, knowledge layers, knowledge unit, multidimensional knowledge network, task-oriented modeling, organizational memories, dynamic display
23	Rita Cucchiara, Massimo Piccardi, Andrea Prati 0001	Hardware Prefetching Techniques for Cache Memories in Multimedia Applications.	CAMP	2000	DBLP DOI BibTeX RDF	hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories
23	Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé	Conflict-Free Access for Streams in Multimodule Memories.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	decoupled access, multimodule memories, out-of-order access, streams with constant strides, vector processors, Conflict-free access, storage schemes
23	Kewal K. Saluja	On-chip testing of random access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
23	Ram Raghavan, John P. Hayes	Reducing Inerference Among Vector Accesses in Interleaved Memories.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interference reduction, vector accesses, concurrent data requests, vector superconductors, vector data placement, computer architecture, system performance, memory bandwidth, vector data, memory interference, interleaved memories, vector processor systems
23	Gurindar S. Sohi	High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	high bandwidth interleaved memories, alternate interleaving schemes, vector processing systems, parallel processing, computer architecture, storage management, buffering, simulation study, access patterns, vector processors
23	Tao Wang, Xinhua Zhuang, Xiaoliang Xing, Xipeng Xiao	A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	neuron-weighted associative memory, NWAM, gradient descent rule, analog neural network, computer simulation experiments, learning (artificial intelligence), neural nets, associative memories, learning algorithm, hardware implementation, content-addressable storage, neural chips, global minimization
23	Dominique Thiébaut, Joel L. Wolf, Harold S. Stone	Synthetic Traces for Trace-Driven Simulation of Cache Memories.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	synthetic address traces, infinite address-space, synthetic traces, random walk, digital simulation, cache memories, memory architecture, trace-driven simulation, buffer storage, content-addressable storage
23	Masaru Takesue	Cache Memories for Data Flow Machines.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	data flow machines, dataflow caches, cache block replacement, cache memories, memory architecture, buffer storage, register transfer level simulator
23	Ingrid Y. Bucher, Donald A. Calahan	Models of Access Delays in Multiprocessor Memories.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	multiprocessor memories, interleaved common memory, multipleprocessors, access conflicts, pipelined accessoperations, performance evaluation, queueing theory, multiprocessing systems, memory architecture, random access, queuing model, access delays
23	Pinaki Mazumder, Janak H. Patel	An efficient design of embedded memories and their testability analysis using Markov chains.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Embedded random-access memories, random testing and testable design
23	Vladimir Cherkassky, Karen Fassett, Nikolaos Vassilas	Linear Algebra Approach to Neural Associative Memories and Noise Performance of Neural Classifiers.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	linear algebra approach, neural associative memories, noise performance, neural classifiers, generalized inverse memory construction rules, performance evaluation, neural nets, linear algebra, content-addressable storage, comparative analysis, saturation, analytic evaluation, correlation matrix memory
23	Jacob Savir, William H. McAnney, Salvatore R. Vecchio	Testing for Coupled Cells in Random-Access Memories.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	coupled-cell faults, address lines, read/write control, deterministic setting, fault tolerant computing, integrated circuit testing, automatic testing, memory testing, random-access storage, RAM, integrated memory circuits, random-access memories, address space
23	Manuel Blum 0001, William S. Evans, Peter Gemmell, Sampath Kannan, Moni Naor	Checking the Correctness of Memories	FOCS	1991	DBLP DOI BibTeX RDF	memories correctness checking, reliable memory, sequence of requests, data structure, lower bounds, probability, program checking
23	Pinaki Mazumder, Janak H. Patel	Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	semiconductor random-access memories, design-for-testability approach, MOS integrated circuits, reliability, integrated circuit testing, linear complexity, MOS, random-access storage, integrated memory circuits, pattern-sensitive faults, design strategy, parallel testing
23	Kieran T. Herley	Efficient Simulations of Small Shared Memories on Bounded Degree Networks (Preliminary Version)	FOCS	1989	DBLP DOI BibTeX RDF	small shared memories, bounded degree networks, PRAM algorithms, simulation, parallel random-access machine, PRAM
23	Mario Blaum, Rodney M. Goodman, Robert J. McEliece	The Reliability of Single-Error Protected Computer Memories.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	single-error correcting double-error detecting codes, SEC-DED codes, single-error protected computer memories, memory chip failure, Poisson assumption, life testing, semiconductor storage, reliability, statistical analysis, error correction codes, error detection codes, lifetimes, circuit reliability, closed-form expression, mean time to failure
23	Jois Malathi Char, Vladimir Cherkassky, Harry Wechsler, George Lee Zimmerman	Distributed and Fault-Tolerant Computation for Retrieval Tasks Using Distributed Associative Memories.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	retrieval tasks, input key data, image reconfiguration, database information retrieval, information retrieval, fault-tolerant computation, fault tolerant computing, distributed processing, database management systems, noise, content-addressable storage, distributed associative memories