Search results for "self-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
26	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Estimation of BIST Resources During High-Level Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	built-in self-test, high-level synthesis, estimation
26	José Luis Huertas	Test and design-for-test of mixed-signal integrated circuits.	SBCCI	2004	DBLP DOI BibTeX RDF
26	Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich	Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.	ETS	2009	DBLP DOI BibTeX RDF	Concurrent self test, test generation, BIST
26	Gladys Omayra Ducoudray, Jaime Ramírez-Angulo	Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	iDD analysis, built-in self-test, mixed-signal test
26	Samir Boubezari, Bozena Kaminska	A new reconfigurable Test Vector Generator for built-in self-test applications.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	rank order clustering, built-in self-test, cellular automata, test vector generator
26	Gary L. Craig, Charles R. Kime, Kewal K. Saluja	Test Scheduling and Control for VLSI Built-In Self-Test.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	test resource sharing, suboptimum algorithms, equal length test, unequal length test, scheduling, VLSI, VLSI, built-in self-test, integrated circuit testing, BIST, automatic testing, hierarchical model, test scheduling, algorithm performance
25	Andrew Diniz da Costa, Camila Nunes, Viviane Torres da Silva, Baldoino Fonseca dos Santos Neto, Carlos José Pereira de Lucena	JAAF+T: a framework to implement self-adaptive agents that apply self-test.	SAC	2010	DBLP DOI BibTeX RDF	self-adaptation, dynamic environment, self-testing, control loop
25	Jian Shen, Jacob A. Abraham	Native mode functional test generation for processors with applications to self test and design validation.	ITC	1998	DBLP DOI BibTeX RDF
25	Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda	Estimating testing effectiveness of the circular self-test path technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
25	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
25	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
24	Adrian E. Seigler, Gary A. Van Huben, Hari Mony	Formal Verification of Partial Good Self-Test Fencing Structures.	FMCAD	2007	DBLP DOI BibTeX RDF	fencing, formal verification, self test
24	Shiyi Xu	Build-In-Self-Test for Software.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Software Testing, Design for Testability, Build-In-Self-Test (BIST)
24	Y. Tsiatouhas, Th. Haniotakis	A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing.	DFT	1999	DBLP DOI BibTeX RDF	Built-In Self Test, Delay Fault Testing
24	Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller	Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	linear hybrid cellular automata, sequential fault, transition capability, built-in self-test, linear feedback shift register, linear finite state machine
24	Xiaoding Chen, Michael S. Hsiao	Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	built-in-self-test, System-on-a-chip, spectral analysis
24	Debaleena Das, Mark G. Karpovsky	Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	exhaustive codes, near-exhaustive codes, built-in self-test, memory testing, pattern sensitive faults
24	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
24	Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang 0002	A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
24	R. Frost, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus	A Configurable Modular Test Processor and Scan Controller Architecture.	IOLTS	2007	DBLP DOI BibTeX RDF
23	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	Designing Self Test Programs for Embedded DSP Cores.	DATE	2004	DBLP DOI BibTeX RDF
23	Dirk Niggemeyer, M. Rüffer	Parametric Built-In Self-Test of VLSI Systems.	DATE	1999	DBLP DOI BibTeX RDF
23	Jos van Sas, Francky Catthoor, Hugo De Man	Cellular automata based deterministic self-test strategies for programmable data paths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan	On efficient generation of instruction sequences to test for delay defects in a processor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	native-mode self-test, delay test, software based self-test
23	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
23	Nur A. Touba	Obtaining High Fault Coverage with Circular BIST Via State Skipping.	VTS	1997	DBLP DOI BibTeX RDF	Circular BIST, Circular Self-Test Path, Conflict Matrix, Column Covering, Built-In Self-Test (BIST), Linear Feedback Shift Register, Pseudo-Random Testing, Digital Testing
23	Janusz Rajski, Jerzy Tyszer	Recursive Pseudoexhaustive Test Pattern Generation.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive pseudoexhaustive test pattern generation, parallel pattern generator, exclusive-or array, serial generators, scan-based built-in self-test, logic testing, built-in self test, test vectors, characteristic functions
23	John Y. Sayah, Charles R. Kime	Test Scheduling in High Performance VLSI System Implementations.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high performance VLSI system, parallel test execution, organization level, test parallelism, schedulability criteria, suboptimum heuristic-based algorithms, VLSI, built-in self-test, built-in self test, time, integrated circuit testing, design for testability, automatic testing, space, heuristic programming, test scheduling, inherent parallelism
23	Rupsa Chakraborty, Dipanwita Roy Chowdhury	coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips.	ACRI	2008	DBLP DOI BibTeX RDF	Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
23	Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy	Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	output response compression, Built-in self-test, scan design
23	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
23	C. J. Clark	Tutorial IND2B: Structured Embedded Configuration and Test.	VLSI Design	2007	DBLP DOI BibTeX RDF
23	Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001	Systematic Software-Based Self-Test for Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
22	Kay Suenaga, Rodrigo Picos, Sebastià A. Bota, Miquel Roca 0001, Eugeni Isern 0001, Eugenio García	A Module for BiST of CMOS RF Receivers.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	RF-IC, Test, Built-in-self-test, MOS, Mixers
22	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	BIST for Network-on-Chip Interconnect Infrastructures.	VTS	2006	DBLP DOI BibTeX RDF	interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip
22	Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test library, RTL architecture, pre-computed testability, self-test
22	Kumar L. Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen 0001, Randall L. Geiger	BIST and production testing of ADCs using imprecise stimulus.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	ADC linearity, imprecision measurement, imprecision stimulus, built-in self-test, Analog and mixed-signal testing, production test
22	Gabriela Peretti, Eduardo Romero 0002, Franco Salvático, Carlos A. Marqués	A Functional Approach to Test Cascaded BCD Counters.	DELTA	2002	DBLP DOI BibTeX RDF	off-line built-in self-test, functional test, synchronous systems, digital testing
22	Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston	Effective diagnostics through interval unloads in a BIST environment.	DAC	2002	DBLP DOI BibTeX RDF	fault diagnosis, built-in self-test (BIST)
22	Paulo F. Flores, Horácio C. Neto, João P. Marques Silva	An exact solution to the minimum size test pattern problem.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	propositional satisfiability (SAT), verification and test, built-in self-test (BIST), Automatic test pattern generation (ATPG), integer linear programming (ILP)
22	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
22	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
22	Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee	Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
22	Jacob Savir	Module Level Weighted Random Patterns.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	weighted random test, self-test, detection probability, signal probability, pseudorandom test
22	Martin Rudolph	Feedback-testing by using multiple input signature registers.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR
22	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams	BIST hardware synthesis for RTL data paths based on testcompatibility classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
22	Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt	On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).	IOLTS	2005	DBLP DOI BibTeX RDF
22	Peter Böhlau	Zero Aliasing Compression Based on Groups of Weakly Independent Outputs in Circuits with High Complexity for Two Fault Models.	EDCC	1994	DBLP DOI BibTeX RDF	zero aliasing, self-testing circuits, functional properties, groupability, weakly independent outputs, built-in self-test
22	Slawomir Pilarski	Comments on "Test efficiency analysis of random self-test of sequential circuits".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Ken Batcher, Christos A. Papachristou	Instruction Randomization Self Test For Processor Cores.	VTS	1999	DBLP DOI BibTeX RDF
22	Dick L. Liu, Edward J. McCluskey	Design of large embedded CMOS PLAs for built-in self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
21	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
21	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
21	Aiman H. El-Maleh, Yahya E. Osais	A retiming-based test pattern generator design for built-in self test of data path architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
21	Sarma Sastry, Amitava Majumdar 0002	Test efficiency analysis of random self-test of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
21	Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin	Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.	PRDC	2004	DBLP DOI BibTeX RDF
21	Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
21	Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
21	Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
21	Chin-Long Wey	Built-in self-test (BIST) design of high-speed carry-free dividers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
21	Karim Arabi, Bozena Kaminska, Janusz Rzeszut	A new built-in self-test approach for digital-to-analog and analog-to-digital converters.	ICCAD	1994	DBLP DOI BibTeX RDF
21	Nilmoni Deb, R. D. (Shawn) Blanton	Built-In Self Test of CMOS-MEMS Accelerometers.	ITC	2002	DBLP DOI BibTeX RDF
21	Thomas Olbrich, Andrew Richardson 0001	Design and Self-Test for Switched-Current Building Blocks.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
21	André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin	A new march sequence to fit DDR SDRAM test in burst mode.	SBCCI	2008	DBLP DOI BibTeX RDF	DDR SDRAM, march algorithms, built-in self test, system on chip, memory test
21	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
21	Ioannis Voyiatzis, Constantin Halatsis	A Low-Cost Concurrent BIST Scheme for Increased Dependability.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	input vector monitoring concurrent BIST, Built-in self test, concurrent testing
21	Dirk Niggemeyer, Elizabeth M. Rudnick	A data acquisition methodology for on-chip repair of embedded memories.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	column failures, on-chip repair, built-in self-test, Diagnosis, memory test, march tests, embedded memory, coupling faults
21	Wei-Lun Wang, Kuen-Jong Lee	An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain
21	Muhammad Nummer, Manoj Sachdev	A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.	VTS	2001	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, Delay-fault testing, design for delay testability
21	Albrecht P. Stroele	Synthesis for Arithmetic Built-In Self-Tes.	VTS	2000	DBLP DOI BibTeX RDF	test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
21	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Scheduling and Module Assignment for Reducing Bist Resources.	DATE	1998	DBLP DOI BibTeX RDF	Built-in Self-test, High-level synthesis
21	Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande	Testing Network-on-Chip Communication Fabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A New ATPG Technique (ExpoTan) for Testing Analog Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Sandeep Koranne	Formulating SoC test scheduling as a network transportation problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
21	Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson 0001	An Evaluation of Pseudo Random Testing for Detecting Real Defects.	VTS	2001	DBLP DOI BibTeX RDF
21	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Kowen Lai, Christos A. Papachristou	BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
21	Wolfgang O. Budde	Modular testprocessor for VLSI chips and high-density PC boards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
21	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
20	Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbauwhede	Low Cost Built in Self Test for Public Key Crypto Cores.	FDTC	2010	DBLP DOI BibTeX RDF	Security, Built-In Self-Test, Public-Key Cryptography, Pseudorandom Testing
20	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Analog built-in self-test, Transient response analysis, FPAA
20	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
20	Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham	Native Mode Functional Self-Test Generation for Systems-on-Chip.	ISQED	2002	DBLP DOI BibTeX RDF	functional self-test, native-mode, signature compression, system-on-chip, at-speed
20	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Built-In Self-Test Scheme for Parallel Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	tree multipliers, Built-in self-test, array multipliers, cell fault model
20	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
20	T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian	Built-In Self-Test with an Alternating Output.	DATE	1998	DBLP DOI BibTeX RDF	cover circuit, Built-in self-test, circuit testing
20	Yuejian Wu, Sanjay Gupta	Built-In Self-Test for Multi-Port RAMs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
20	Kazuhiko Iwasaki, Shigeo Nakamura	Aliasing Error for a Mask ROM Built-In Self-Test.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	mask ROM, experimental faults analysis, Built-in self-test, aliasing probability, MISRs
20	Sandeep K. Gupta 0001, Dhiraj K. Pradhan	Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	concurrent checking, fault-escape probability, parity prediction, Built-in self-test, BIST
20	Samir Boubezari, Bozena Kaminska	A Deterministic Built-In-Self-Test Generator Based on Cellular Automata Structures.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	autonomous finite-state machine, built-in self-test, Cellular automata, programmable logic array, test vector generator
20	Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky	A Data Compression Technique for Built-In Self-Test.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	data compression technique, error-propagating space compression, Exclusive-NOR, logic testing, data compression, built-in self-test, BIST, automatic testing, self-testing, fault analysis, Exclusive-OR
20	William H. McAnney, Jacob Savir	Built-In Checking of the Correct Self-Test Signature.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	self-test signature, initial value, signature register, single observation, logic testing, automatic testing, built-in testing
20	Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara	A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	output response compression, parity bits, Built-in self test (BIST), fault models, fault coverage, VLSI design, test pattern generation, programmable logic array (PLA)
20	Alexander Miczo	A Self-Test Hardwired Control Section.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Control section, fault diagnosis, fault detection, self-test
20	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A System-layer Infrastructure for SoC Diagnosis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP
20	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF