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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1250 occurrences of 693 keywords
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Results
Found 3867 publication records. Showing 3867 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
40 | Sergei Chubanov, Mikhail Y. Kovalyov, Erwin Pesch |
An FPTAS for a single-item capacitated economic lot-sizing problem with monotone cost structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 106(3), pp. 453-466, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Capacitated economic lot-sizing problem, Dynamic programming, Fully polynomial time approximation scheme |
40 | Laurence A. Wolsey |
Lot-sizing with production and delivery time windows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 107(3), pp. 471-489, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Production time windows, Convex hull, Mixed integer programming, Lot-sizing |
40 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 78-85, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP) |
40 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Buffer sizing for clock power minimization subject to general skew constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 159-164, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew scheduling |
40 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 166-173, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew |
40 | Sunil Thulasidasan, Wu-chun Feng, Mark K. Gardner |
Optimizing GridFTP through Dynamic Right-Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: 12th International Symposium on High-Performance Distributed Computing (HPDC-12 2003), 22-24 June 2003, Seattle, WA, USA, pp. 14-23, 2003, IEEE Computer Society, 0-7695-1965-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dynamic right-sizing, DRS, drsFTP, computational grid, Globus, GridFTP, auto-tuning, bandwidth-delay product |
40 | Paul I. Pénzes, Mika Nyström, Alain J. Martin |
Transistor sizing of energy-delay--efficient circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 126-133, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy-delay optimization, transistor sizing |
40 | Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar |
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 486-491, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Dual-Vt design, multiple threshold, optimization, sizing |
40 | Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah |
Optimization of custom MOS circuits by transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 174-180, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation, optimization, Circuits, gradients, transistor sizing |
40 | Jatan C. Shah, Sachin S. Sapatnekar |
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 346-351, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
power-delay tradeoffs, dynamic programming, Interconnect, sensitivity, buffer, sizing, repeaters, drivers |
40 | Sachin S. Sapatnekar, Weitong Chuang |
Power vs. delay in gate sizing: conflicting objectives? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 463-466, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power |
38 | Bo Fu, Qiaoyan Yu, Paul Ampadu |
Energy-delay minimization in nanoscale domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 316-319, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay, energy, leakage, low voltage, domino |
38 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Fast comparisons of circuit implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(12), pp. 1329-1339, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Güntzel |
Incremental timing optimization for automatic layout generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3567-3570, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Tian-Li Yu 0001, David E. Goldberg, Kumara Sastry |
Optimal Sampling and Speed-Up for Genetic Algorithms on the Sampled OneMax Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation - GECCO 2003, Genetic and Evolutionary Computation Conference, Chicago, IL, USA, July 12-16, 2003. Proceedings, Part II, pp. 1554-1565, 2003, Springer, 3-540-40603-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Is wire tapering worthwhile? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 430-436, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 581-587, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Fernando G. Lobo, Cláudio F. Lima |
Revisiting evolutionary algorithms with on-the-fly population size adjustment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2006, Proceedings, Seattle, Washington, USA, July 8-12, 2006, pp. 1241-1248, 2006, ACM, 1-59593-186-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
population sizing, parameter control |
35 | Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex |
Interconnect width selection for deep submicron designs using the table lookup method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 41-44, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect sizing, power-delay trade-off, wire sizing |
34 | Yves Pochet, Laurence A. Wolsey |
Single item lot-sizing with non-decreasing capacities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 121(1), pp. 123-143, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 90C11, 90C57 |
34 | Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu |
Transistor sizing of custom high-performance digital circuits with parametric yield considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 781-786, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
custom circuits, optimization |
34 | Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani |
Application Specific Transistor Sizing for Low Power Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 195-198, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar |
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 295-308, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Yongpei Guan, Andrew Miller |
A Polynomial Time Algorithm for the Stochastic Uncapacitated Lot-Sizing Problem with Backlogging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCO ![In: Integer Programming and Combinatorial Optimization, 13th International Conference, IPCO 2008, Bertinoro, Italy, May 26-28, 2008, Proceedings, pp. 450-462, 2008, Springer, 978-3-540-68886-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Tao Luo 0002, David Newmark, David Z. Pan |
Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 352-357, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 188-193, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Neda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick McKeown, Geoff Salmon |
Experimental study of router buffer sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Measurement Conference ![In: Proceedings of the 8th ACM SIGCOMM Internet Measurement Conference, IMC 2008, Vouliagmeni, Greece, October 20-22, 2008, pp. 197-210, 2008, ACM, 978-1-60558-334-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network test-beds, router buffer size, tcp, netfpga |
34 | Vishal Khandelwal, Ankur Srivastava 0001 |
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1246-1255, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Vasant Patil, Rajeev Kumar |
A Fast Arbitrary Factor H.264/AVC Video Re-Sizing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (4) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 65-68, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram |
Sizing and placement of charge recycling transistors in MTCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 791-796, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
A novel approach for variation aware power minimization during gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 174-179, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard |
Circuit sizing method under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Narender Hanchate, Nagarajan Ranganathan |
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 92-97, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi |
Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1394-1398, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Venkataraman Mahalingam, N. Ranganathan |
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 180-185, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 423-426, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Noriyuki Miura, Naoki Kato, Tadahiro Kuroda |
Practical methodology of post-layout gate sizing for 15% more power saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 434-437, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Vishal Khandelwal, Ankur Srivastava 0001 |
Leakage control through fine-grained placement and sizing of sleep transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 533-536, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
Fast and exact transistor sizing based on iterative relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5), pp. 568-581, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Interconnect sizing and spacing with consideration of couplingcapacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1164-1169, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj |
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 158-163, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar |
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), pp. 779-788, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | E. T. A. F. Jacobs, Michel R. C. M. Berkelaar |
Gate Sizing Using a Statistical Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 283-290, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |
Convex delay models for transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 655-660, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
34 | Youxin Gao, Martin D. F. Wong |
Wire-sizing optimization with inductance consideration using transmission-line model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1759-1767, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Tong Xiao, Malgorzata Marek-Sadowska |
Crosstalk Reduction by Transistor Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 137-140, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim |
Interleaving buffer insertion and transistor sizing into a single optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 625-633, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Kerry S. Lowe, P. Glenn Gulak |
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 419-434, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
A power optimization method considering glitch reduction by gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 221-226, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Joe G. Xi, Wayne Wei-Ming Dai |
Useful-Skew Clock Routing with Gate Sizing for Low Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 163-179, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Transistor sizing for low power CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6), pp. 665-671, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski |
A new algorithm for transistor sizing in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 589-593, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
34 | William H. Kao, Nader Fathi, Chia-Hao Lee |
Algorithms for automatic transistor sizing in CMOS digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 781-784, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
32 | Jason E. Cook, Daniel R. Tauritz |
An exploration into dynamic population sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2010, Proceedings, Portland, Oregon, USA, July 7-11, 2010, pp. 807-814, 2010, ACM, 978-1-4503-0072-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parameterless evolutionary algorithm, optimization, evolutionary algorithm, population sizing, parameter control |
32 | Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma |
DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Glob. Optim. ![In: J. Glob. Optim. 44(1), pp. 53-77, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution |
32 | André Nwamba, Daniel R. Tauritz |
Futility-based offspring sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, pp. 1873-1874, 2009, ACM, 978-1-60558-325-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
offspring sizing, parameterless evolutionary algorithm, optimization, evolutionary algorithm, parameter control |
32 | Sanja Petrovic, Carole Fayad, Dobrila Petrovic, Edmund K. Burke, Graham Kendall |
Fuzzy job shop scheduling with lot-sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 159(1), pp. 275-292, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Fuzzy multi-objective genetic algorithm, Job shop scheduling, Batching, Real-world application, Lot-sizing, Fuzzy rule-based system, Dispatching rules |
32 | Guy Even, Retsef Levi, Dror Rawitz, Baruch Schieber, Shimon Shahar, Maxim Sviridenko |
Algorithms for capacitated rectangle stabbing and lot sizing with joint set-up costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Algorithms ![In: ACM Trans. Algorithms 4(3), pp. 34:1-34:17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
capacitated covering, rectangle stabbing, Approximation algorithms, lot sizing |
32 | Deisemara Ferreira, Paulo Morelato França, Alf Kimms, Reinaldo Morabito, Socorro Rangel, Claudio Fabiano Motta Toledo |
Heuristics and meta-heuristics for lot sizing and scheduling in the soft drinks industry: a comparison study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Metaheuristics for Scheduling in Industrial and Manufacturing Applications ![In: Metaheuristics for Scheduling in Industrial and Manufacturing Applications, pp. 169-210, 2008, Springer, 978-3-540-78984-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Two-level Production Planning, Soft Drinks Industry, Genetic Algorithm, Scheduling, Memetic Algorithm, Lot Sizing |
32 | Alexandre Dolgui, Mikhail Y. Kovalyov, Kseniya Shchamialiova |
Lot-Sizing and Sequencing on a Single Imperfect Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCO ![In: Modelling, Computation and Optimization in Information Systems and Management Sciences, Second International Conference, MCO 2008, Metz, France - Luxembourg, September 8-10, 2008. Proceedings, pp. 117-125, 2008, Springer, 978-3-540-87476-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Imperfect production, Sequencing, Lot-sizing |
32 | Ian Kuon, Jonathan Rose |
Automated transistor sizing for FPGA architecture exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 792-795, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, FPGA, transistor sizing |
32 | Silvio A. de Araujo, Marcos Nereu Arenales, Alistair R. Clark |
Joint rolling-horizon scheduling of materials processing and lot-sizing with sequence-dependent setups. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Heuristics ![In: J. Heuristics 13(4), pp. 337-358, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Sequence-dependent setup costs and times, Fix-and-relax, Scheduling, Local search, Lot-sizing |
32 | Mathieu Van Vyve |
Linear-programming extended formulations for the single-item lot-sizing problem with backlogging and constant capacity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 108(1), pp. 53-77, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Constant capacity, Backlogging, Extended formulation, Lot-sizing |
32 | Scott Hanson, Dennis Sylvester, David T. Blaauw |
A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 338-341, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
voltage scaling, gate sizing, subthreshold circuits |
32 | Azadeh Davoodi, Ankur Srivastava 0001 |
Variability driven gate sizing for binning yield optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 959-964, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
speed binning, process variations, gate sizing |
32 | Brian Swahn, Soha Hassoun |
Gate sizing: finFETs vs 32nm bulk MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 528-531, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate sizing, thermal modeling, FinFET |
32 | David G. Chinnery, Kurt Keutzer |
Linear programming for sizing, Vth and Vdd assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 149-154, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
linear program, delay, power, sizing |
32 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Clock network sizing via sequential linear programming with time-domain analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 182-189, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew, time-domain analysis |
32 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 27-32, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect |
32 | Hyewon Seo, Nadia Magnenat-Thalmann |
An automatic modeling of human bodies from sizing parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SI3D ![In: Proceedings of the 2003 Symposium on Interactive 3D Graphics, SI3D 2003, Monterey, California, USA, April 28-30, 2003, pp. 19-26, 2003, ACM, 1-58113-645-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
3D scan data, sizing parameters, PCA, interpolation, examples, human body modeling |
32 | Vincenzo Galdi, Lucio Ippolito, Antonio Piccolo, Alfredo Vaccaro |
A genetic-based methodology for hybrid electric vehicles sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 5(6), pp. 451-457, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Hybrid electric vehicles, Powertrain sizing, Genetic optimisation, Genetic algorithms |
32 | Sachin S. Sapatnekar, Weitong Chuang |
Power-delay optimizations in gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 98-114, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
optimization, power estimation, VLSI layout, transistor sizing |
32 | Eduardo Miranda |
An evaluation of the paired comparisons method for software sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Proceedings of the 22nd International Conference on on Software Engineering, ICSE 2000, Limerick Ireland, June 4-11, 2000., pp. 597-604, 2000, ACM, 1-58113-206-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
estimation methods, paired comparisons method, subjective estimates, software sizing, measurement methods |
32 | Abhijit Das |
On the Transistor Sizing Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 258-261, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint |
32 | Chris C. N. Chu, D. F. Wong 0001 |
A new approach to simultaneous buffer insertion and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 614-621, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing |
32 | Si-Hun Sung, Sung-Il Chien, Mun-Gab Kim, Joon-Nyun Kim |
Adaptive Window Algorithm with Four-Direction Sizing Factors for Robust Correlation-Based Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 9th International Conference on Tools with Artificial Intelligence, ICTAI '97, Newport Beach, CA, USA, November 3-8, 1997, pp. 208-215, 1997, IEEE Computer Society, 0-8186-8203-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Sizing Factors, PDOE and AWA-FSF, Tracking, Correlation, Adaptive Window |
30 | Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu |
Behavior-level yield enhancement approach for large-scaled analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 903-908, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
process variation, analog circuits, yield enhancement |
30 | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang |
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 523-528, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Interconnect-Driven Floorplanning, Performance Optimization |
30 | Jason Cong, David Zhigang Pan |
Interconnect performance estimation models for design planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), pp. 739-752, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Jason Cong, David Zhigang Pan |
Interconnect Delay Estimation Models for Synthesis and Design Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 97-100, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Zhaoyun Xing, Prithviraj Banerjee |
A parallel algorithm for zero skew clock tree routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 118-123, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Interconnect power and delay optimization by dynamic programming in gridded design rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 153-160, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization |
29 | Ying-Yu Chen, Chen Dong 0003, Deming Chen |
Clock tree synthesis under aggressive buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 86-89, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
slew, buffer insertion, buffer sizing, clock tree, maze routing |
29 | Bo Liu 0003, Francisco V. Fernández 0001, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca |
A memetic approach to the automatic design of high-performance analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 42:1-42:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm |
29 | Jui-Tsung Wong, Kuei-Hsien Chen, Chwen-Tzeng Su |
Replenishment Policy with Deteriorating Raw Material Under a Supply Chain: Complexity and the Use of Ant Colony Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UNISCON ![In: Information Systems: Modeling, Development, and Integration, Third International United Information Systems Conference, UNISCON 2009, Sydney, Australia, April 21-24, 2009. Proceedings, pp. 142-152, 2009, Springer, 978-3-642-01111-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic lot-sizing problem, deteriorating raw material, complexity, Ant colony optimization |
29 | Do Young Eun, Xinbing Wang |
Achieving 100% throughput in TCP/AQM under aggressive packet marking with small buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 16(4), pp. 945-956, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
router buffer sizing, small buffer, transmission control protocol, TCP/IP, stochastic modeling |
29 | Min Ni, Seda Ogrenci Memik |
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 610-613, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-Vth, leakage power optimization, gate sizing, clock skew scheduling |
29 | I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang |
Statistical circuit optimization considering device andinterconnect process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 47-54, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate and wire sizing, statistical optimization |
29 | Guoli Liu, Lixin Tang |
Model and Solution for the Multilevel Production-Inventory System Before Ironmaking in Shanghai Baoshan Iron and Steel Complex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2006, International Conference, Glasgow, UK, May 8-11, 2006, Proceedings, Part III, pp. 659-667, 2006, Springer, 3-540-34075-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
combinatorial optimization, lagrangian relaxation, Lot-sizing |
29 | Fred W. Glover, Hanif D. Sherali |
Some Classes of Valid Inequalities and Convex Hull Characterizations for Dynamic Fixed-Charge Problems under Nested Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 140(1), pp. 215-233, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic fixed-charge problems, capacitated lot-sizing, convex hull, valid inequalities, reformulation-linearization technique |
29 | Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen |
Efficient timing closure without timing driven placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 268-273, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
digital design flow, gate sizing, placement and routing, timing closure |
29 | Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang |
A methodology to improve timing yield in the presence of process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 448-453, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
timing analysis, gate sizing, timing yield |
29 | Arindam Mukherjee 0001, Krishna Reddy Dusety, Rajsaktish Sankaranarayan |
A practical CAD technique for reducing power/ground noise in DSM circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 96-99, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power/ground noise, low power, linear programming, timing analysis, gate sizing, simultaneous switching noise |
28 | Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex |
Impact of interconnect resistance increase on system performance of low power and high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 85-90, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing |
26 | Afzal Godil |
Facial Shape Analysis and Sizing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (11) ![In: Digital Human Modeling, Second International Conference, ICDHM 2009, Held as Part of HCI International 2009, San Diego, CA, USA, July 19-24, 2009. Proceedings, pp. 29-35, 2009, Springer, 978-3-642-02808-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
PCA, cluster analysis, shape descriptor, Anthropometry |
26 | Xiaohua Guan, Witawas Srisa-an, ChengHuan Jia |
Investigating the effects of using different nursery sizing policies on performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 8th International Symposium on Memory Management, ISMM 2009, Dublin, Ireland, June 19-20, 2009, pp. 59-68, 2009, ACM, 978-1-60558-347-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multithreaded applications, generational garbage collection |
26 | Weiguang Sheng, Liyi Xiao, Zhigang Mao |
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 502-507, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
genetic algorithm, optimization, soft error, multi-objective |
26 | Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow |
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 975-984, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 598-602, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Daniel Quadt, Heinrich Kuhn |
Capacitated lot-sizing with extensions: a review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
4OR ![In: 4OR 6(1), pp. 61-83, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MSC Classification (2000) 90B30, 90B35, 90C27, 90C90, 90C10, 90C59 |
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