Search results for "sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
40	Sergei Chubanov, Mikhail Y. Kovalyov, Erwin Pesch	An FPTAS for a single-item capacitated economic lot-sizing problem with monotone cost structure.	Math. Program.	2006	DBLP DOI BibTeX RDF	Capacitated economic lot-sizing problem, Dynamic programming, Fully polynomial time approximation scheme
40	Laurence A. Wolsey	Lot-sizing with production and delivery time windows.	Math. Program.	2006	DBLP DOI BibTeX RDF	Production time windows, Convex hull, Mixed integer programming, Lot-sizing
40	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
40	Kai Wang 0011, Malgorzata Marek-Sadowska	Buffer sizing for clock power minimization subject to general skew constraints.	DAC	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew scheduling
40	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
40	Sunil Thulasidasan, Wu-chun Feng, Mark K. Gardner	Optimizing GridFTP through Dynamic Right-Sizing.	HPDC	2003	DBLP DOI BibTeX RDF	dynamic right-sizing, DRS, drsFTP, computational grid, Globus, GridFTP, auto-tuning, bandwidth-delay product
40	Paul I. Pénzes, Mika Nyström, Alain J. Martin	Transistor sizing of energy-delay--efficient circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
40	Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.	DAC	2002	DBLP DOI BibTeX RDF	Dual-Vt design, multiple threshold, optimization, sizing
40	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing
40	Jatan C. Shah, Sachin S. Sapatnekar	Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.	VLSI Design	1996	DBLP DOI BibTeX RDF	power-delay tradeoffs, dynamic programming, Interconnect, sensitivity, buffer, sizing, repeaters, drivers
40	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
38	Bo Fu, Qiaoyan Yu, Paul Ampadu	Energy-delay minimization in nanoscale domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	delay, energy, leakage, low voltage, domino
38	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast comparisons of circuit implementations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
38	Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Güntzel	Incremental timing optimization for automatic layout generation.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
38	Tian-Li Yu 0001, David E. Goldberg, Kumara Sastry	Optimal Sampling and Speed-Up for Genetic Algorithms on the Sampled OneMax Problem.	GECCO	2003	DBLP DOI BibTeX RDF
38	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Is wire tapering worthwhile?	ICCAD	1999	DBLP DOI BibTeX RDF
37	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.	ICCAD	2003	DBLP DOI BibTeX RDF
37	Fernando G. Lobo, Cláudio F. Lima	Revisiting evolutionary algorithms with on-the-fly population size adjustment.	GECCO	2006	DBLP DOI BibTeX RDF	population sizing, parameter control
35	Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex	Interconnect width selection for deep submicron designs using the table lookup method.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect sizing, power-delay trade-off, wire sizing
34	Yves Pochet, Laurence A. Wolsey	Single item lot-sizing with non-decreasing capacities.	Math. Program.	2010	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 90C11, 90C57
34	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
34	Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani	Application Specific Transistor Sizing for Low Power Full Adders.	ASAP	2009	DBLP DOI BibTeX RDF
34	Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar	A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Yongpei Guan, Andrew Miller	A Polynomial Time Algorithm for the Stochastic Uncapacitated Lot-Sizing Problem with Backlogging.	IPCO	2008	DBLP DOI BibTeX RDF
34	Tao Luo 0002, David Newmark, David Z. Pan	Total power optimization combining placement, sizing and multi-Vt through slack distribution management.	ASP-DAC	2008	DBLP DOI BibTeX RDF
34	Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.	ICCD	2008	DBLP DOI BibTeX RDF
34	Neda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick McKeown, Geoff Salmon	Experimental study of router buffer sizing.	Internet Measurement Conference	2008	DBLP DOI BibTeX RDF	network test-beds, router buffer size, tcp, netfpga
34	Vishal Khandelwal, Ankur Srivastava 0001	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Vasant Patil, Rajeev Kumar	A Fast Arbitrary Factor H.264/AVC Video Re-Sizing Algorithm.	ICIP (4)	2007	DBLP DOI BibTeX RDF
34	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
34	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III	A novel approach for variation aware power minimization during gate sizing.	ISLPED	2006	DBLP DOI BibTeX RDF
34	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard	Circuit sizing method under delay constraint.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Narender Hanchate, Nagarajan Ranganathan	Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
34	M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
34	Venkataraman Mahalingam, N. Ranganathan	A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.	ISVLSI	2005	DBLP DOI BibTeX RDF
34	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	False Path and Clock Scheduling Based Yield-Aware Gate Sizing.	VLSI Design	2005	DBLP DOI BibTeX RDF
34	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
34	Vishal Khandelwal, Ankur Srivastava 0001	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
34	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	Fast and exact transistor sizing based on iterative relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
34	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Interconnect sizing and spacing with consideration of couplingcapacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
34	Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj	A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.	ISQED	2001	DBLP DOI BibTeX RDF
34	Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar	A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
34	E. T. A. F. Jacobs, Michel R. C. M. Berkelaar	Gate Sizing Using a Statistical Delay Model.	DATE	2000	DBLP DOI BibTeX RDF
34	Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar	Convex delay models for transistor sizing.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
34	Youxin Gao, Martin D. F. Wong	Wire-sizing optimization with inductance consideration using transmission-line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
34	Tong Xiao, Malgorzata Marek-Sadowska	Crosstalk Reduction by Transistor Sizing.	ASP-DAC	1999	DBLP DOI BibTeX RDF
34	Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim	Interleaving buffer insertion and transistor sizing into a single optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
34	Kerry S. Lowe, P. Glenn Gulak	A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
34	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF
34	Joe G. Xi, Wayne Wei-Ming Dai	Useful-Skew Clock Routing with Gate Sizing for Low Power Design.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
34	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for low power CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
34	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
34	William H. Kao, Nader Fathi, Chia-Hao Lee	Algorithms for automatic transistor sizing in CMOS digital circuits.	DAC	1985	DBLP DOI BibTeX RDF
32	Jason E. Cook, Daniel R. Tauritz	An exploration into dynamic population sizing.	GECCO	2010	DBLP DOI BibTeX RDF	parameterless evolutionary algorithm, optimization, evolutionary algorithm, population sizing, parameter control
32	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Glob. Optim.	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
32	André Nwamba, Daniel R. Tauritz	Futility-based offspring sizing.	GECCO	2009	DBLP DOI BibTeX RDF	offspring sizing, parameterless evolutionary algorithm, optimization, evolutionary algorithm, parameter control
32	Sanja Petrovic, Carole Fayad, Dobrila Petrovic, Edmund K. Burke, Graham Kendall	Fuzzy job shop scheduling with lot-sizing.	Ann. Oper. Res.	2008	DBLP DOI BibTeX RDF	Fuzzy multi-objective genetic algorithm, Job shop scheduling, Batching, Real-world application, Lot-sizing, Fuzzy rule-based system, Dispatching rules
32	Guy Even, Retsef Levi, Dror Rawitz, Baruch Schieber, Shimon Shahar, Maxim Sviridenko	Algorithms for capacitated rectangle stabbing and lot sizing with joint set-up costs.	ACM Trans. Algorithms	2008	DBLP DOI BibTeX RDF	capacitated covering, rectangle stabbing, Approximation algorithms, lot sizing
32	Deisemara Ferreira, Paulo Morelato França, Alf Kimms, Reinaldo Morabito, Socorro Rangel, Claudio Fabiano Motta Toledo	Heuristics and meta-heuristics for lot sizing and scheduling in the soft drinks industry: a comparison study.	Metaheuristics for Scheduling in Industrial and Manufacturing Applications	2008	DBLP DOI BibTeX RDF	Two-level Production Planning, Soft Drinks Industry, Genetic Algorithm, Scheduling, Memetic Algorithm, Lot Sizing
32	Alexandre Dolgui, Mikhail Y. Kovalyov, Kseniya Shchamialiova	Lot-Sizing and Sequencing on a Single Imperfect Machine.	MCO	2008	DBLP DOI BibTeX RDF	Imperfect production, Sequencing, Lot-sizing
32	Ian Kuon, Jonathan Rose	Automated transistor sizing for FPGA architecture exploration.	DAC	2008	DBLP DOI BibTeX RDF	optimization, FPGA, transistor sizing
32	Silvio A. de Araujo, Marcos Nereu Arenales, Alistair R. Clark	Joint rolling-horizon scheduling of materials processing and lot-sizing with sequence-dependent setups.	J. Heuristics	2007	DBLP DOI BibTeX RDF	Sequence-dependent setup costs and times, Fix-and-relax, Scheduling, Local search, Lot-sizing
32	Mathieu Van Vyve	Linear-programming extended formulations for the single-item lot-sizing problem with backlogging and constant capacity.	Math. Program.	2006	DBLP DOI BibTeX RDF	Constant capacity, Backlogging, Extended formulation, Lot-sizing
32	Scott Hanson, Dennis Sylvester, David T. Blaauw	A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	voltage scaling, gate sizing, subthreshold circuits
32	Azadeh Davoodi, Ankur Srivastava 0001	Variability driven gate sizing for binning yield optimization.	DAC	2006	DBLP DOI BibTeX RDF	speed binning, process variations, gate sizing
32	Brian Swahn, Soha Hassoun	Gate sizing: finFETs vs 32nm bulk MOSFETs.	DAC	2006	DBLP DOI BibTeX RDF	gate sizing, thermal modeling, FinFET
32	David G. Chinnery, Kurt Keutzer	Linear programming for sizing, Vth and Vdd assignment.	ISLPED	2005	DBLP DOI BibTeX RDF	linear program, delay, power, sizing
32	Kai Wang 0011, Malgorzata Marek-Sadowska	Clock network sizing via sequential linear programming with time-domain analysis.	ISPD	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew, time-domain analysis
32	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
32	Hyewon Seo, Nadia Magnenat-Thalmann	An automatic modeling of human bodies from sizing parameters.	SI3D	2003	DBLP DOI BibTeX RDF	3D scan data, sizing parameters, PCA, interpolation, examples, human body modeling
32	Vincenzo Galdi, Lucio Ippolito, Antonio Piccolo, Alfredo Vaccaro	A genetic-based methodology for hybrid electric vehicles sizing.	Soft Comput.	2001	DBLP DOI BibTeX RDF	Hybrid electric vehicles, Powertrain sizing, Genetic optimisation, Genetic algorithms
32	Sachin S. Sapatnekar, Weitong Chuang	Power-delay optimizations in gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	optimization, power estimation, VLSI layout, transistor sizing
32	Eduardo Miranda	An evaluation of the paired comparisons method for software sizing.	ICSE	2000	DBLP DOI BibTeX RDF	estimation methods, paired comparisons method, subjective estimates, software sizing, measurement methods
32	Abhijit Das	On the Transistor Sizing Problem.	VLSI Design	2000	DBLP DOI BibTeX RDF	Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint
32	Chris C. N. Chu, D. F. Wong 0001	A new approach to simultaneous buffer insertion and wire sizing.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
32	Si-Hun Sung, Sung-Il Chien, Mun-Gab Kim, Joon-Nyun Kim	Adaptive Window Algorithm with Four-Direction Sizing Factors for Robust Correlation-Based Tracking.	ICTAI	1997	DBLP DOI BibTeX RDF	Sizing Factors, PDOE and AWA-FSF, Tracking, Correlation, Adaptive Window
30	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
30	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
30	Jason Cong, David Zhigang Pan	Interconnect performance estimation models for design planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
30	Jason Cong, David Zhigang Pan	Interconnect Delay Estimation Models for Synthesis and Design Planning.	ASP-DAC	1999	DBLP DOI BibTeX RDF
30	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
29	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
29	Ying-Yu Chen, Chen Dong 0003, Deming Chen	Clock tree synthesis under aggressive buffer insertion.	DAC	2010	DBLP DOI BibTeX RDF	slew, buffer insertion, buffer sizing, clock tree, maze routing
29	Bo Liu 0003, Francisco V. Fernández 0001, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca	A memetic approach to the automatic design of high-performance analog integrated circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm
29	Jui-Tsung Wong, Kuei-Hsien Chen, Chwen-Tzeng Su	Replenishment Policy with Deteriorating Raw Material Under a Supply Chain: Complexity and the Use of Ant Colony Optimization.	UNISCON	2009	DBLP DOI BibTeX RDF	dynamic lot-sizing problem, deteriorating raw material, complexity, Ant colony optimization
29	Do Young Eun, Xinbing Wang	Achieving 100% throughput in TCP/AQM under aggressive packet marking with small buffer.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	router buffer sizing, small buffer, transmission control protocol, TCP/IP, stochastic modeling
29	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
29	I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang	Statistical circuit optimization considering device andinterconnect process variations.	SLIP	2007	DBLP DOI BibTeX RDF	gate and wire sizing, statistical optimization
29	Guoli Liu, Lixin Tang	Model and Solution for the Multilevel Production-Inventory System Before Ironmaking in Shanghai Baoshan Iron and Steel Complex.	ICCSA (3)	2006	DBLP DOI BibTeX RDF	combinatorial optimization, lagrangian relaxation, Lot-sizing
29	Fred W. Glover, Hanif D. Sherali	Some Classes of Valid Inequalities and Convex Hull Characterizations for Dynamic Fixed-Charge Problems under Nested Constraints.	Ann. Oper. Res.	2005	DBLP DOI BibTeX RDF	dynamic fixed-charge problems, capacitated lot-sizing, convex hull, valid inequalities, reformulation-linearization technique
29	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
29	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
29	Arindam Mukherjee 0001, Krishna Reddy Dusety, Rajsaktish Sankaranarayan	A practical CAD technique for reducing power/ground noise in DSM circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power/ground noise, low power, linear programming, timing analysis, gate sizing, simultaneous switching noise
28	Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex	Impact of interconnect resistance increase on system performance of low power and high performance designs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
26	Afzal Godil	Facial Shape Analysis and Sizing System.	HCI (11)	2009	DBLP DOI BibTeX RDF	PCA, cluster analysis, shape descriptor, Anthropometry
26	Xiaohua Guan, Witawas Srisa-an, ChengHuan Jia	Investigating the effects of using different nursery sizing policies on performance.	ISMM	2009	DBLP DOI BibTeX RDF	multithreaded applications, generational garbage collection
26	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
26	Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow	A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
26	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
26	Daniel Quadt, Heinrich Kuhn	Capacitated lot-sizing with extensions: a review.	4OR	2008	DBLP DOI BibTeX RDF	MSC Classification (2000) 90B30, 90B35, 90C27, 90C90, 90C10, 90C59