Search results for "Capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae	A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
23	Haoxing Ren, David Zhigang Pan, Paul Villarrubia	True crosstalk aware incremental placement with noise map.	ICCAD	2004	DBLP DOI BibTeX RDF
23	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
23	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices.	VTS	2004	DBLP DOI BibTeX RDF
23	Emmanuel Zervakis, Dimitris Loukas, Nikos Haralabidis, Arximidis Pavlidis	Development of a CMOS low-noise analog front-end ASIC for X-ray imaging applications.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
23	Philipp Häfliger, Håvard Kolle Riis	A multi-level static memory cell.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
23	Yonghee Im, Kaushik Roy 0001	O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
23	Suvodeep Gupta, Srinivas Katkoori	Force-Directed Scheduling for Dynamic Power Optimization.	ISVLSI	2002	DBLP DOI BibTeX RDF
23	Koichi Nose, Takayasu Sakurai	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.	ISLPED	2002	DBLP DOI BibTeX RDF
23	Youxin Gao, D. F. Wong 0001	A fast and accurate delay estimation method for buffered interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
23	Danielle Moraes, Francis Anghinolfi, Philippe Deval, Pierre Jarron, Werner Riegler, Angelo Rivetti, Burkhard Schmidt 0003	CARIOCA-0.25 Sigma-Delta CMOS fast binary front-end for sensor interface using a novel current-mode feedback technique.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
23	Vasily G. Moshnyaga, Hiroshi Tsuji	Cache energy reduction by dual voltage supply.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Sung-Woo Hur, Ashok Jagannathan, John Lillis	Timing-driven maze routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
23	Jason Cong, Lei He 0001	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
23	Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu 0001	Logic Transformation for Low Power Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
23	Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon	A new approach to analyze interconnect delays in RC wire models.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
23	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
23	John P. Fishburn	Shaping a VLSI wire to minimize Elmore delay.	ED&TC	1997	DBLP DOI BibTeX RDF
23	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Post-processing of clock trees via wiresizing and buffering for robust design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
23	Ahmed S. Desouki, Young-June Park, Hong-Shick Min	A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Mehmet A. Cirit	The Meyer model revisited: why is charge not conserved? [MOS transistor].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
20	Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan	Statistical decoupling capacitance allocation by efficient numerical quadrature method.	ISQED	2009	DBLP DOI BibTeX RDF
20	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	Alexander Heldring, Juan Manuel Rius, José Maria Tamayo, Josep Parrón	Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti	Differential Capacitance Analysis.	PATMOS	2008	DBLP DOI BibTeX RDF	security, cryptography, side-channel attacks, power analysis, DCA
20	Markus Bingesser, Teddy Loeliger, Werner Hinn, Johann Hauer, Stefan Modl, Robert Dorn, Matthias Völker	Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement.	DATE	2008	DBLP DOI BibTeX RDF
20	Takashi Enami, Masanori Hashimoto, Takashi Sato	Decoupling capacitance allocation for timing with statistical noise model and timing analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
20	Somashekar Bangalore Prakash, Pamela Abshire	A fully differential CMOS capacitance sensor design, testing and array architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Majid Jalalifar, Mohammad Yavari, Farshid Raissi	A novel topology in reversed nested miller compensation using dual-active capacitance.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Sanjay Pant, David T. Blaauw	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
20	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
20	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Nancy Ying Zhou, Zhuo Li 0001, Weiping Shi	Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.	DAC	2007	DBLP DOI BibTeX RDF
20	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.	DAC	2007	DBLP DOI BibTeX RDF
20	Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan	On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.	DAC	2007	DBLP DOI BibTeX RDF
20	Kazutaka Honda, Masanori Furuta, Shoji Kawahito	A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo	Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Tadashi Suetsugu, Marian K. Kazimierczuk	Sub-optimum operation of class E amplifier with nonlinear shunt capacitance at any duty cycle.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Jon Alfredsson, Bengt Oelmann	Capacitance selection for digital floating-gate circuits operating in subthreshold.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
20	Rohit Ananthakrishna, Shabbir H. Batterywala	MoM - A Process Variation Aware Statistical Capacitance Extractor.	VLSI Design	2006	DBLP DOI BibTeX RDF
20	Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada	Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	S. A. Moghaddam, Nasser Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
20	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
20	Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee	A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array.	ISQED	2004	DBLP DOI BibTeX RDF
20	Xiaoyan Wang, Pietro Andreani	Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
20	Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	opamp, feedback, CMOS, compensation, operational amplifier, slew rate
20	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell	Benchmarks for Interconnect Parasitic Resistance and Capacitance.	ISQED	2003	DBLP DOI BibTeX RDF
20	Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong	Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling.	ISQED	2003	DBLP DOI BibTeX RDF
20	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez	A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
20	Zhaozhi Yang, Zeyi Wang, Shuzhou Fang	A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance.	ASP-DAC	2001	DBLP DOI BibTeX RDF
20	Rachid Bouchakour, Nadia Harabech, Pierre Canet, Philippe Boivin, Jean Michel Mirable	Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
20	Hoan H. Pham, Arokia Nathan	An integral equation of the second kind for computation of capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
20	Armen H. Zemanian, Victor A. Chang	Exterior templates for capacitance computations [interconnections].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
20	G. Xu, Sherif H. K. Embabi, P. Hao, Edgar Sánchez-Sinencio	A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
20	Raymond S. Winton, William R. Bandy	A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
20	S. M. Aziz, Joarder Kamruzzaman	Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
20	U. Geigenmüller, N. P. van der Meijs	Cartesian multipole based numerical integration for 3D capacitance extraction.	ED&TC	1997	DBLP DOI BibTeX RDF
20	Jason Cong, Lei He 0001, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen	Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.	DAC	1997	DBLP DOI BibTeX RDF
20	Zeyi Wang, Yanhong Yuan, Qiming Wu	A parallel multipole accelerated 3-D capacitance simulator based on an improved model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
20	Akira Ito	A voltage dependent capacitance model including effects of manufacturing process variabilities on voltage coefficients.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
20	V. Radhakrishnan, N. Achutan, S. Verghese, R. Santoshkumar	A new approach to the measurement of surface roughness using the pulse-jet capacitance method.	Electronic Technology Directions	1995	DBLP DOI BibTeX RDF
20	Joel R. Phillips, Jacob K. White 0001	A precorrected-FFT method for capacitance extraction of complicated 3-D structures.	ICCAD	1994	DBLP DOI BibTeX RDF
20	Shiuh-Wuu Lee	A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
20	Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg	A first-order charge conserving MOS capacitance model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
20	Steve Shao-Shiun Chung	A charge-based capacitance model of short-channel MOSFETs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
20	Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen	Three-dimensional capacitance computations for VLSI/ULSI interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
20	Çetin Kaya Koç, P. F. Ordung	Schwarz-Christoffel transformation for the simulation of two-dimensional capacitance [VLSI circuits].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
20	Zhen-qiu Ning, Patrick M. Dewilde	SPIDER: capacitance modelling for VLSI interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
20	Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner	CAPCAL-a 3-D capacitance solver for support of CAD systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
20	Roberto Guerrieri, Alberto L. Sangiovanni-Vincentelli	Three-dimensional capacitance evaluation on a Connection Machine.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
17	Kei Nakatsuma, Hiroyuki Shinoda	High accuracy position and orientation detection in two-dimensional communication network.	CHI	2010	DBLP DOI BibTeX RDF	device localization, surface-like device, two-dimensional communication (2dc), ubiquitous computing, capacitance sensing
17	Nan Xie, Haibo Zhang, Shenyong Gao, Yan Ma, Weimin Chen	Development of Online Measuring Instrument for Water-in-Oil percentage Based on MCU.	IFITA (3)	2009	DBLP DOI BibTeX RDF	water-in-oil percentage, XE2004, capacitance to voltage convention, online measurement, MCU
17	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar 0002	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
17	Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal	Metal filling impact on standard cells: definition of the metal fill corner concept.	SBCCI	2008	DBLP DOI BibTeX RDF	metal filling, modelization, interconnect, design of experiment, dispersion, standard cells, capacitance, corners, ring oscillators
17	Jingyuan Cheng, David Bannach, Kurt Adamer, Thomas Bernreiter, Paul Lukowicz	A Wearable, Conductive Textile Based User Interface for Hospital Ward Rounds Document Access.	EuroSSC	2008	DBLP DOI BibTeX RDF	capacitance measuring, wearable sensing
17	Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta	Driver waveform computation for timing analysis with multiple voltage threshold driver models.	DAC	2008	DBLP DOI BibTeX RDF	current source model, effective capacitance
17	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
17	Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti	Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation
17	Lakshmi Kalpana Vakati, Janet Meiling Wang	A new multi-ramp driver model with RLC interconnect load.	ISPD	2004	DBLP DOI BibTeX RDF	inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance
17	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
17	Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano	Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment.	ISLPED	2003	DBLP DOI BibTeX RDF	variable capacitance, vibration energy, resonance, power generation
17	Jiang Xu 0001, Wayne H. Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
17	Seung Hoon Choi, Kaushik Roy 0001	Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Crosstalk, Inductance, Capacitance, Noise Analysis, Noise Margin, High Speed Circuit
17	Bernard N. Sheehan	Osculating Thevenin model for predicting delay and slew of capacitively characterized cells.	DAC	2002	DBLP DOI BibTeX RDF	static timing analysis, effective capacitance
17	Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa	Architecture-level power estimation and design experiments.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	architecture tradeoff, architecture-level power estimation, control unit, energy table, instruction format transition, output signal transition, power analysis and estimation, switch capacitance, low power design, hardware/software codesign, energy model, functional unit, computer-aided design of VLSI
17	Jouko Marjonen, Markku Åberg	A Single Clocked Adiabatic Static Logic - A Proposal for Digital Low Power Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	sinisoidal power source, non-existing DC-path, load capacitance, LC-oscillator, charge recycling
17	Dennis Sylvester	Measurement techniques and interconnect estimation.	SLIP	2000	DBLP DOI BibTeX RDF	capacitance measurement, interconnect characterization, noise measurement, process variation, interconnect estimation
17	Kavel M. Büyüksahin, Farid N. Najm	High-level power estimation with interconnect effects.	ISLPED	2000	DBLP DOI BibTeX RDF	high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
17	Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal	Inductance Characterization of Small Interconnects Using Test-Signal Method.	VLSI Design	2000	DBLP DOI BibTeX RDF	Test-Signal Injection Method, Differential Circuit, Short Interconnects, Self and Mutual-Inductance, High Frequency Test Signal, Displacement Current, Lumped Package Models, Inductance, Characterization, Transmission Lines, Capacitance, Substrate
17	Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking	A Robust Solution to the Timing Convergence Problem in High-Performance Design.	ICCD	1999	DBLP DOI BibTeX RDF	timing convergence, maximum capacitance, synthesis, placement, design-rules
17	Shannon V. Morton	On-Chip Inductance Issues in Multiconductor Systems.	DAC	1999	DBLP DOI BibTeX RDF	alpha microprocessor, cross-talk, interconnect, noise, inductance, transmission line, capacitance, resistance, buses, semiconductor, RLC
17	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
17	Massoud Pedram	Power minimization in IC design: principles and applications.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product
17	Josep Rius 0001, Joan Figueras	Detecting IDDQ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
17	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
15	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
15	P. V. Ratna Kumar, Kaushik Bhattacharyya, Tamal Das, Pradip Mandal	Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination.	ISLPED	2009	DBLP DOI BibTeX RDF	shoot-through current, switched capacitor converter, time interleaving
15	Vasilis F. Pavlidis, Giovanni De Micheli	Power distribution paths in 3-D ICS.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power distribution network, 3-D ICS, 3-D integration, through silicon vias