Search results for "Interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
33	Liang Song, Dimitrios Hatzinakos	A cross-layer architecture of wireless sensor networks for target tracking.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	embedded wireless interconnect, open systems interconnect, wireless sensor networks, medium access control, target tracking, application layer
33	T. Boggess, F. Shirley	High-performance scalable computing for real-time applications.	ICCCN	1997	DBLP DOI BibTeX RDF	high-performance scalable computing, interconnect technologies, high-performance computing technologies, embedded military applications, heterogeneous computer nodes, high-throughput system area network, standardized intelligent node-to-network interface, LANai, Sanders, Ptolemy environment, high density interconnect packaging, avionics applications, PacketWay, Internet Engineering Task Force proposed standard, high speed inter-SAN encryption, simulation, modeling, real-time systems, reconfigurable computing, real-time applications, RISC, switched network, digital signal processor, Myrinet
32	Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones	Interconnect customization for a hardware fabric.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	hardware fabric, architecture, computer-aided design, Reconfigurable, low-energy, demonstrable
32	Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong	A scalable micro wireless interconnect structure for CMPs.	MobiCom	2009	DBLP DOI BibTeX RDF	on-chip wireless interconnection network, chip multiprocessors
32	Andreas Hansson 0001, Kees Goossens	An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, programming model, protocol stack
32	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
32	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
32	Jun-Kuei Zeng, Chung-Ping Chen	Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis.	DATE	2008	DBLP DOI BibTeX RDF
32	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing non-monotonic interconnect using functional simulation and logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF
32	Siyuan Liu, Lei Li, Yiyang Zhao, Jianping Fan 0002	GMIP: A Novel Optical Interconnect Gridded Memory Service Protocol.	ICPADS	2008	DBLP DOI BibTeX RDF
32	Yehea I. Ismail	Interconnect design and limitations in nanoscale technologies.	ISCAS	2008	DBLP DOI BibTeX RDF
32	Wu Jigang, Thambipillai Srikanthan, Kai Wang	Finding minimum interconnect sub-arrays in reconfigurable VLSI arrays.	ISCAS	2008	DBLP DOI BibTeX RDF
32	Yehia Massoud, Arthur Nieuwoudt	Performance analysis of optimized carbon nanotube interconnect.	ISCAS	2008	DBLP DOI BibTeX RDF
32	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	design for manufacturability, dummy fill
32	Xiaopeng Ji, Long Ge, Xiaodong Han, Zhiquan Wang	Wire-Sizing for Interconnect Performance Optimization Considering High Inductance Effects.	ICNSC	2008	DBLP DOI BibTeX RDF
32	Magnus Själander, Per Larsson-Edefors, Magnus Björk	A Flexible Datapath Interconnect for Embedded Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
32	PariVallal Kannan, Dinesh Bhatia	Interconnect estimation for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
32	Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.	ISQED	2006	DBLP DOI BibTeX RDF
32	Andrew Havlir, David Z. Pan	Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.	ISQED	2006	DBLP DOI BibTeX RDF
32	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
32	Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis	Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.	VLSI Design	2006	DBLP DOI BibTeX RDF
32	Guoqing Chen, Eby G. Friedman	An RLC interconnect model based on fourier analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
32	Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong	Microarchitecture evaluation with floorplanning and interconnect pipelining.	ASP-DAC	2005	DBLP DOI BibTeX RDF
32	Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu	ULSI Interconnect Length Distribution Model Considering Core Utilization.	DATE	2004	DBLP DOI BibTeX RDF
32	Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko	BIST Based Interconnect Fault Location for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
32	Zhijian Lu, Wei Huang 0004, John C. Lach, Mircea R. Stan, Kevin Skadron	Interconnect lifetime prediction under dynamic stress for reliability-aware design.	ICCAD	2004	DBLP DOI BibTeX RDF
32	Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi	A power aware system level interconnect design methodology for latency-insensitive systems.	ICCAD	2004	DBLP DOI BibTeX RDF
32	Janet Meiling Wang, Omar Hafiz	Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method.	ISQED	2004	DBLP DOI BibTeX RDF
32	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Routability and Fault Tolerance of FPGA Interconnect Architectures.	ITC	2004	DBLP DOI BibTeX RDF
32	Janet Meiling Wang, Omar Hafiz, Jun Li 0066	A linear fractional transform (LFT) based model for interconnect parametric uncertainty.	DAC	2004	DBLP DOI BibTeX RDF	linear fractional transform, parametric uncertainty
32	Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel	Interconnect Driven Low Power High-Level Synthesis.	PATMOS	2003	DBLP DOI BibTeX RDF
32	Andrew B. Kahng, Bao Liu 0001	Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.	ISVLSI	2003	DBLP DOI BibTeX RDF
32	Pallav Gupta, Lin Zhong 0001, Niraj K. Jha	A High-level Interconnect Power Model for Design Space Exploration.	ICCAD	2003	DBLP DOI BibTeX RDF
32	Traianos V. Yioultsis, Anne Woo, Andreas C. Cangellaris	Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules.	ICCAD	2003	DBLP DOI BibTeX RDF	Transmission-line modeling of interconnects, interconnects with frequency-dependent losses, passive reduced- order synthesis
32	Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
32	Chung-Seok (Andy) Seo, Abhijit Chatterjee	A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect.	ICCD	2002	DBLP DOI BibTeX RDF
32	Kaustav Banerjee, Amit Mehrotra	Inductance Aware Interconnect Scaling.	ISQED	2002	DBLP DOI BibTeX RDF
32	Lisa Noordergraaf, Robert Zak	SMP system interconnect instrumentation for performance analysis.	SC	2002	DBLP DOI BibTeX RDF
32	Jason Cong, David Zhigang Pan	Interconnect performance estimation models for design planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
32	Minghorng Lai, D. F. Wong 0001	Memory-efficient interconnect optimization.	ASP-DAC	2001	DBLP DOI BibTeX RDF
32	Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell	Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations.	VLSI Design	2001	DBLP DOI BibTeX RDF
32	Yue Liu	VCSEL Based Smart Pixel Array Technology Enables Chip-to-Chip Optical Interconnect.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
32	Hung-Ming Chen, Hai Zhou 0001, Fung Yu Young, D. F. Wong 0001, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning and interconnect planning.	ICCAD	1999	DBLP DOI BibTeX RDF
32	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Repeater insertion in tree structured inductive interconnect.	ICCAD	1999	DBLP DOI BibTeX RDF
32	Debaleena Das, Nur A. Touba	A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.	VLSI Design	1999	DBLP DOI BibTeX RDF
32	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
32	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
32	Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer	SACI: statistical static timing analysis of coupled interconnects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	coupled interconnect, sources of variation, crosstalk noise, statistical timing analysis
32	Vineet Wason, Kaustav Banerjee	A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer-interconnect system, statistical delay and power models, sensitivity analysis, parameter variations, statistical optimization
32	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.	DAC	2004	DBLP DOI BibTeX RDF	piecewise-linear, performance, pipeline, interconnect, floorplanning
32	Min Ni, Seda Ogrenci Memik	Self-heating-aware optimal wire sizing under Elmore delay model.	DATE	2007	DBLP DOI BibTeX RDF
32	Guoqing Chen, Eby G. Friedman	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
32	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Electrical and optical on-chip interconnects in scaled microprocessors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
32	Keoncheol Shin, Taewhan Kim	Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Andrey V. Mezhiba, Eby G. Friedman	Impedance characteristics of power distribution grids in nanoscale integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao	Simultaneous floor plan and buffer-block optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
32	Andrew B. Kahng, Sudhakar Muddu	An analytical delay model for RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
32	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Recent Developments in Performance Driven Steiner Routing: An Overview.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
28	J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Package level interconnect options.	SLIP	2005	DBLP DOI BibTeX RDF	performance metrics, package, transmission lines, global interconnects
28	Ron Ho	High-performance ULSI: the real limiter to interconnect scaling.	SLIP	2005	DBLP DOI BibTeX RDF	VLSI, wireless, 3D, scaling, proximity, repeaters, wires
28	Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng	Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.	SLIP	2002	DBLP DOI BibTeX RDF	rectilinear steiner tree algorithm, refined single trunk tree, routing estimation, VLSI CAD
28	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
28	Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer	On improving optimization effectiveness in interconnect-driven physical synthesis.	ISPD	2009	DBLP DOI BibTeX RDF	routing, interconnect, physical synthesis, circuit optimization, vlsi
28	Mackenzie R. Scott, Rajeevan Amirtharajah	Pulse width modulation for reduced peak power full-swing on-chip interconnect.	ISLPED	2009	DBLP DOI BibTeX RDF	low power interconnect, peak power, pulse width modulation
28	Joseph Nayfach-Battilana, Jose Renau	SOI, interconnect, package, and mainboard thermal characterization.	ISLPED	2009	DBLP DOI BibTeX RDF	SOI modeling, package modeling, thermal modeling, interconnect modeling
28	Ge Chen, Saeid Nooshabadi, Steven G. Duvall	An optimization strategy for low energy and high performance for the on-chip interconnect signalling.	ISLPED	2009	DBLP DOI BibTeX RDF	interconnect signaling, low energy
28	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
28	Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker 0001, Martin Keim, Wu-Tung Cheng	Automatic Test Pattern Generation for Interconnect Open Defects.	VTS	2008	DBLP DOI BibTeX RDF	Interconnect opens, Open-via defects, ATPG
28	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar	Parallel vs. serial on-chip communication.	SLIP	2008	DBLP DOI BibTeX RDF	dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
28	Thomas William Ainsworth, Timothy Mark Pinkston	On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus.	NOCS	2007	DBLP DOI BibTeX RDF	Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck
28	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua	Performance Evaluation of Fully Adaptive Routing for the Torus Interconnect Networks.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	adaptive routing algorithm, parallel computer network, torus Interconnect Networks
28	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
28	Jonggab Kil, Jie Gu 0003, Chris H. Kim	A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.	ISLPED	2006	DBLP DOI BibTeX RDF	capacitive boosting, sub-threshold circuit, clock skew, global interconnect, variation tolerance
28	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen	Optimal Interconnect ATPG Under a Ground-Bounce Constraint.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	testing, interconnect, Hamming distance, wires, ground bounce
28	James D. Z. Ma, Rob A. Rutenbar	Fast interval-valued statistical interconnect modeling and reduction.	ISPD	2005	DBLP DOI BibTeX RDF	interval-valued statistical interconnect analysis, manufacturing variation, affine arithmetic
28	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	FPGA, low power, interconnect, encoding
28	David Goren, Michael Zelikson, Rachel Gordin, Israel A. Wagner, Anastasia Barger, Alon Amir, Betty Livshitz, Anatoly Sherman, Youri Tretiakov, Robert A. Groves, J. Park, Donald L. Jordan, Sue E. Strang, Raminderpal Singh, Carl E. Dickey, David L. Harame	On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices.	DAC	2003	DBLP DOI BibTeX RDF	modeling, interconnect, vlsi
28	Joachim Pistorius, Mike Hutton	Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation.	SLIP	2003	DBLP DOI BibTeX RDF	FPGA architecture, interconnect prediction, SLIP, rent
28	Li Chen, Xiaoliang Bai, Sujit Dey	Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	interconnect, crosstalk, processor, self-test
28	Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob K. White 0001	Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect.	ICCAD	2002	DBLP DOI BibTeX RDF	Proximity Effect, interconnect analysis, Skin Effect, parasitic extraction
28	Payam Heydari, Massoud Pedram	Interconnect Energy Dissipation in High-Speed ULSI Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines
28	Srikanth Venkataraman, Scott Brady Drummonds	A Technique for Logic Fault Diagnosis of Interconnect Open Defects.	VTS	2000	DBLP DOI BibTeX RDF	Diagnosis and Debugging, Logic Fault Diagnosis, Interconnect Open Defects, Fault Modeling and Simulation, Dynamic Diagnosis
28	Jens Mache	An Assessment of Gigabit Ethernet as Cluster Interconnect.	IWCC	1999	DBLP DOI BibTeX RDF	cluster interconnect, performance evaluation, communication network, Gigabit Ethernet, NAS parallel benchmarks
28	B. E. Duewer, John M. Wilson 0002, D. A. Winick, Paul D. Franzon	MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.	ARVLSI	1999	DBLP DOI BibTeX RDF	Variable Capacitors, Programable Interconnect, RF Switching, Digital Switching, Bistable Devices, MEMS, Crossbar, Capacitive Coupling
28	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Novel Control Pattern Generators for Interconnect Testing with Boundary Scan.	DFT	1999	DBLP DOI BibTeX RDF	BIST, boundary scan, Interconnect testing
28	José T. de Sousa, Peter Y. K. Cheung	Diagnosis of Boards for Realistic Interconnect Shorts.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	interconnect diagnosis, board testing, board diagnosis
28	Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng	Global harmony: coupled noise analysis for full-chip RC interconnect networks.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect, noise, static timing analysis
28	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
28	Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	On the Fault Coverage of Interconnect Diagnosis.	VTS	1997	DBLP DOI BibTeX RDF	diagnose, interconnect testing, adjacency graph
28	Michel Renovell, Joan Figueras, Yervant Zorian	Test of RAM-based FPGA: methodology and application to the interconnect.	VTS	1997	DBLP DOI BibTeX RDF	RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
28	Jason Cong, Lei He 0001	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
28	Steven M. P. Yip, Nicholas Bambos	Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect.	ICPADS	1996	DBLP DOI BibTeX RDF	scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing
28	Haifang Liao, Wayne Wei-Ming Dai	Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.	ICCAD	1995	DBLP DOI BibTeX RDF	circuit reduction, scattering parameter, interconnect network, macromodel, Circuit partitioning, circuit synthesis
28	Jens Kargaard Madsen, Stephen I. Long	A High-Speed Interconnect Network Using Ternary Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication
28	Jens Lienig	introduction to electromigration-aware physical design.	ISPD	2006	DBLP DOI BibTeX RDF	interconnect, layout, physical design, electromigration, current density, interconnect reliability
28	Mehrdad Nourani, Amir Attarha	Signal Integrity: Fault Modeling and Testing in High-Speed SoCs.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	integrity fault, integrity loss, transfer function matrix, built-in self-test, system-on-chip, test pattern generation, signal integrity, model order reduction, interconnect testing, skew detection, noise detection, high-speed interconnect
28	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
28	Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, Kenneth K. O	Wireless interconnects for clock distribution.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	integrated antenna, wireless interconnect, wireless communication, interconnect, clock distribution, RF CMOS