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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 455 occurrences of 313 keywords
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Results
Found 754 publication records. Showing 754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Daeun Heo, Daejin Park |
Asynchronous Interaction Framework for Verilog Simulation Virtualization on Node.js. |
ICEIC |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Jie Liu, Yu Ban |
A parametric model for a high speed heterogeneous current-steering digital-to-analog converter based on compiled Verilog-A and SPICE. |
ICTA |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers |
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. |
ICCD |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Jisu Kwon, Sejong Oh, Daejin Park |
Metamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Lööw |
Lutsig: a verified Verilog compiler for verified circuit development. |
CPP |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Jaekyung Im, Seokhyeong Kang |
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Md Azmot Ullah Khan, Naheem Olakunle Adesina, Jian Xu |
Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design. |
CCECE |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su |
Implement 32-bit RISC-V Architecture Processor using Verilog HDL. |
ISPACS |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang |
Simulation of serial RRAM cell based on a Verilog-A compact model. |
DCIS |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann |
Verilog HDL and its ancestors and descendants. |
Proc. ACM Program. Lang. |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Hammond Pearce, Benjamin Tan 0001, Ramesh Karri |
DAVE: Deriving Automatically Verilog from English. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
18 | Junya Miura, Hiromu Miyazaki, Kenji Kise |
A portable and Linux capable RISC-V computer system in Verilog HDL. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
18 | David M. Russinoff |
Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2. |
ACL2 |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Md Jubayer Shawon, Vishal Saxena |
Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models. |
IEEE Trans. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Conor Ryan, Michael Kwaku Tetteh, Douglas Mota Dias |
Behavioural Modelling of Digital Circuits in System Verilog using Grammatical Evolution. |
IJCCI |
2020 |
DBLP DOI BibTeX RDF |
|
18 | James F. Power, John Waldron |
Calibration and Analysis of Source Code Similarity Measures for Verilog Hardware Description Language Projects. |
SIGCSE |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen |
IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL. |
SMC |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Hammond Pearce, Benjamin Tan 0001, Ramesh Karri |
DAVE: Deriving Automatically Verilog from English. |
MLCAD |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot |
(System)Verilog to Chisel Translation for Faster Hardware Design. |
RSP |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Fernando Passe, Michael Canesche, Omar Paranaiba Vilela Neto, José Augusto Miranda Nacif, Ricardo S. Ferreira 0001 |
Mind the Gap: Bridging Verilog and Computer Architecture. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Juan Manuel López-Martínez, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez |
Photon-Detection Timing-Jitter Model in Verilog-A. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Renzo Nicolas Alsim, Anastacia Ballesil-Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, John Richard E. Hizon |
A Top-Down Approach for Low Noise Amplifier Design using Verilog-A. |
ISOCC |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Arriel Ting, Anastacia B. Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, John Richard E. Hizon, Christopher Santos |
Designing a Class E Power Amplifier through Modeling in Verilog-A. |
ISOCC |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Nicola Dall'Ora, Sara Vinco, Franco Fummi |
Functionality and Fault Modeling of a DC Motor with Verilog-AMS. |
INDIN |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Bo Li 0056, Yonglei Zhao, Guoyong Shi |
A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS. |
Neurocomputing |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Zoltan Huszka, Kund Molnar |
Suppressing derivatives of selected variables in Verilog-A. |
Int. J. Circuit Theory Appl. |
2019 |
DBLP DOI BibTeX RDF |
|
18 | David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic |
Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
18 | Saraju P. Mohanty, Elias Kougianos |
iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
18 | Alok Joshi, Dewansh Aditya Gupta, Pravriti Jaipuriyar |
Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog. |
J. Inf. Process. Syst. |
2019 |
DBLP BibTeX RDF |
|
18 | Nicola Lupo, Eduardo Pérez, Christian Wenger, Franco Maloberti, Edoardo Bonizzoni |
Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Wladek Grabinski, Ahmed Abo-Elhadid, Marek Mierzwinski, Laurent Lemaitre, Mike Brinson, Christophe Lallement, Jean-Michel Sallese, Sadayuki Yoshitomi, Paul Malisse, Henri Oguey, Stefan Cserveny, Marcelo Antonio Pavanello, Christian C. Enz, François Krummenacher, Eric A. Vittoz, Michelly de Souza, Daniel Tomaszewski, Jolanta Malesinska, Grzegorz Gluszko, Matthias Bucher, Nikolaos Makris, Aristeidis Nikolaou |
FOSS EKV2.6 Verilog-A Compact MOSFET Model. |
ESSDERC |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Faten Ouaja Rziga, Khaoula Mbarek, Sami Ghedira, Kamel Besbes |
A Verilog-A based RRAM Switching Model for Simulation and Analysis. |
ICCAD |
2019 |
DBLP DOI BibTeX RDF |
|
18 | David J. Greaves |
Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog. |
MEMOCODE |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Md Jubayer Shawon, Vishal Saxena |
Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models. |
MWSCAS |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Aman Goel, Karem A. Sakallah |
Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs. |
DATE |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Panagiotis Giounanlis, Elena Blokhina, Imran Bashir, Dirk Leipold, Mike Asker, Robert Bogdan Staszewski |
A Python-Verilog Toolbox for Modeling of a Hadamard Gate Based on Position-Based CMOS Qubits. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
18 | David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic |
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. |
FCCM |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Patrick Döll, Oner Hanay, Erkan Bayram, Renato Negra |
Verilog-A based Behavioral Modeling of an FBMC Transmitter. |
SMACD |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Imran Bashir, Panagiotis Giounanlis, Elena Blokhina, Dirk Leipold, Krzysztof Pomorski, Robert Bogdan Staszewski |
A Verilog-A Model of the Shuttle of an Electron in a Two Quantum-Dot System. |
NEWCAS |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Muhammad Amjad Hafiz, Kai Hu 0004, Jianwei Niu 0002, Noor Khan, Loïc Besnard, Jean-Pierre Talpin |
Translation Validation of Code Generation from the SIGNAL Data-Flow Language to Verilog. |
SKG |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Valery Salauyou, Lukasz Zabrocki |
Coding Techniques in Verilog for Finite State Machine Designs in FPGA. |
CISIM |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Scott Young, Alexandrea Demmings, Nasrin Eshraghi Ivari, Jean-Philippe Legault, Kenneth B. Kent |
Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II. |
RSP |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, Yier Jin |
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment. |
HOST |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Aman Goel, Karem A. Sakallah |
Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction. |
NFM |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Lööw, Magnus O. Myreen |
A proof-producing translator for verilog development in HOL. |
FormaliSE@ICSE |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Marek Materzok |
DigitalJS: a Visual Verilog Simulator for Teaching. |
CSERC |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Mike Brinson |
FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD). |
MIXDES |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Eric Schkufza, Michael Wei, Christopher J. Rossbach |
Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience. |
ASPLOS |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Tze Sin Tan, Bakhtiar Affendi Rosdi |
Hardware-assisted Verilog simulation system using an application specific microprocessor. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Ailin Zhang, Guoyong Shi |
A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Ioannis Messaris, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis 0001, Themistoklis Prodromakis |
A Data-Driven Verilog-A ReRAM Model. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Steven F. Hoover, Ahmed Salman |
Top-Down Transaction-Level Design with TL-Verilog. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
18 | Steven F. Hoover, Ákos Hadnagy |
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
18 | David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez |
VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC. |
PATMOS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Slimane Boutobza, Sorin Popa, Andrea Costa |
A Journey from STIL to Verilog. |
EWDTS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Juan Manuel Lopez-Martinez, Ion Vornicu, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez |
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation. |
ICECS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Charly Meyer, Andre Chanthbouala, Soren Boyn, Jean Tomas, Vincent Garcia, Manuel Bibes, Stephane Fusil, Julie Grollier, Sylvain Saïghi |
Verilog-A model of ferroelectric memristors dedicated to neuromorphic design. |
ICECS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz |
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS. |
SMACD |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Nicola Lupo, Edoardo Bonizzoni, Eduardo Pérez, Christian Wenger, Franco Maloberti |
An Approximated Verilog-A Model for Memristive Devices. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Gleb Krylov, Eby G. Friedman |
Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Sang Un Park, Tae Pyeong Kim, Mee Zee Lee, Yong Beom Cho |
Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL. |
ISOCC |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Abdul Rafay Khatri, Ali Hayek, Josef Börcsök |
Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool. |
DASC/PiCom/DataCom/CyberSciTech |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Zbigniew Mudza |
Using Verilog-to-Routing Framework for Coarse-Grained Reconfigurable Architecture Routing. |
MIXDES |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Jin Hee Kim, Jason Helge Anderson |
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. |
ACM Trans. Reconfigurable Technol. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi |
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2017 |
DBLP DOI BibTeX RDF |
|
18 | An-Sam Peng, Lin-Kun Wu |
An Improved EEHEMT RF Noise Model for 0.25 µm InGaP pHEMT Transistor Using Verilog-A Language. |
IEICE Trans. Electron. |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin |
Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. |
Int. J. Bifurc. Chaos |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Shubhankar Majumdar, Dhrubes Biswas |
Evaluating substrate's effect on RF switch performance via Verilog-A GaN HEMT model. |
Microelectron. J. |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Ioannis Messaris, Alexander Serb, Ali Khiat, Spyridon Nikolaidis 0001, Themistoklis Prodromakis |
A compact Verilog-A ReRAM switching model. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
18 | Jesús M. Muñoz-Pacheco, Víctor R. González-Díaz, Luz del Carmen Gómez-Pavón, Sergio Romero-Camacho, Francisco Sánchez-Guzmán, J. Mateo-Juárez, L. Delgado-Toral, José Arturo Cocoma-Ortega, Arnulfo Luis-Ramos, Plácido Zaca-Morán, Esteban Tlelo-Cuautle |
Behavioral Modeling of Chaos-Based Applications by Using Verilog-A. |
Fractional Order Control and Synchronization of Chaotic Systems |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Colin C. McAndrew |
SPICE modeling in Verilog-A: Successes and challenges: Invited paper. |
ESSDERC |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Francesco Maria Puglisi, Nicolo Zagni, Luca Larcher, Paolo Pavan |
A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design. |
ESSDERC |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Ahmed Zaky, Mohamed Shehata, Yehea Ismail, Hassan Mostafa |
Characterization and model validation of triboelectric nanogenerators using Verilog-A. |
MWSCAS |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Nivasan Yogeswaran, Z. Tang, Vincenzo Vinciguerra, Ravinder Dahiya |
Bending effects in a flexible dual gated graphene FET: A Verilog-A model implementation. |
ECCTD |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Abdul Rafay Khatri, Ali Hayek, Josef Börcsök |
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Nishtha Sharma, Andrew Marshall, Jonathan Bird |
Verilog - A compact model of a ME-MTJ based XNOR/NOR gate. |
NANOARCH |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Steven F. Hoover |
Timing-Abstract Circuit Design in Transaction-Level Verilog. |
ICCD |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Bei Cao, Tianliang Xu, Pengfei Wu |
RSA Encryption Algorithm Design and Verification Based on Verilog HDL. |
MLICOM (1) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi |
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. |
ICICDT |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Satish Maheshwaram, Om. Prakash, Mohit Sharma 0003, Anand Bulusu, Sanjeev Manhas |
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
18 | P. Sideris, Stilianos Siskos, George G. Malliaras |
Verilog-A modeling of Organic Electrochemical Transistors. |
MOCAST |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Ryohei Kobayashi, Tomohiro Misono, Kenji Kise |
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Steven Meyer |
CVC Verilog Compiler - Fast Complex Language Compilers Can be Simple. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
18 | Poorna Marthi, Nazir Hossain, Huan Wang 0009, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González |
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Omar Amin, Youssef Ramzy, Omar Ibrahem, Ahmed Fouad 0001, Khaled Mohamed, Mohamed Abdelsalam |
System Verilog Assertions Synthesis Based Compiler. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Vibarajan Viswanathan, Juliet Runhaar, Doug Reed, Jun Zhao |
Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Anindya Mukherjee, Andreas Pawlak, Michael Schröter, Didier Céli, Zoltan Huszka |
Implementation and quality testing for compact models implemented in Verilog-A. |
DATE |
2016 |
DBLP BibTeX RDF |
|
18 | Davide Lena, Michelangelo Grosso, Alberto Bocca, Alberto Macii, Salvatore Rinaudo |
A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation. |
IECON |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Nil Franch, Oscar Alonso, Ángel Diéguez, Salvador Hidalgo, Iván Vila |
A Verilog-A model of a silicon resistive strip for particle detectors. |
SMACD |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Raimon Casanova, Sebastian Grinstein |
A Verilog-A model of a charge sensitive amplifier for a HV-CMOS pixel sensor. |
SMACD |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Rajdeep Mukherjee, Michael Tautschnig, Daniel Kroening |
v2c - A Verilog to C Translator. |
TACAS |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo |
Verilog-a modeling of Silicon Photo-Multipliers. |
ISCAS |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Md. Fahad, Zhou Zhao, Ashok Srivastava, Lu Peng 0001 |
Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design. |
iNIS |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Khaled Khalifa, Khaled Salah 0001 |
An RTL power optimization technique based on System Verilog assertions. |
UEMCON |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Maria Helena Fino |
Verilog-A compact model of integrated tapered spiral inductors. |
MIXDES |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Zbigniew Jaworski |
Verilog HDL model based thermometer-to-binary encoder with bubble error correction. |
MIXDES |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Om. Prakash, Satish Maheshwaram, Mohit Sharma 0003, Anand Bulusu, A. K. Saxena, S. K. Manhas |
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Oana Moldovan, François Lime, Benjamín Iñíguez |
A complete and Verilog-A compatible Gate-All-Around long-channel junctionless MOSFET model implemented in CMOS inverters. |
Microelectron. J. |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Anders Jakobsson, Adriana Serban, Shaofang Gong |
Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Bipin Kumar Badri Narayanan, Lucas Cambuim, Konstantin Nasartschuk, Kenneth B. Kent, Paul G. Ploeger |
Improved language support for Verilog elaboration in Odin II and FPGA architecture benchmarking in the VTR CAD tool. |
PACRIM |
2015 |
DBLP DOI BibTeX RDF |
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