Search results for "compaction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Baptiste Saint-Cyr	Modélisation des matériaux granulaires cohésifs à particules non convexes : Application à la compaction des poudres d'UO2. (Numerical study of cohesive granular materials composed of nonconvex particles applied to UO2 powder compaction).		2011	RDF
29	Irith Pomeranz, Sudhakar M. Reddy	Sequence reordering to improve the levels of compaction achievable by static compaction procedures.	DATE	2001	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy	COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.	ICCD	2001	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy	Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.	FTCS	1996	DBLP DOI BibTeX RDF
28	Chi-Man Pun, Ning-Yu An, Miao Cheng	A Region-Based Image Segmentation by Watershed Partition and DCT Energy Compaction.	CGIV	2011	DBLP DOI BibTeX RDF	energy compaction, Image segmentation, watershed, cosine transform
28	Upavan Gupta, Nagarajan Ranganathan	A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets.	IEEE Trans. Knowl. Data Eng.	2010	DBLP DOI BibTeX RDF	Equipartitioning, clustering, game theory, Nash equilibrium, compaction
28	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.	VLSI Design	2010	DBLP DOI BibTeX RDF	Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults
28	Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich	Test Encoding for Extreme Response Compaction.	ETS	2009	DBLP DOI BibTeX RDF	Embedded Diagnosis, Design for Test, Test Compression, Response Compaction
28	Martin Hilscher, Michael Braun, Michael Richter 0002, Andreas Leininger, Michael Gössel	Accelerated Shift Registers for X-tolerant Test Data Compaction.	ETS	2008	DBLP DOI BibTeX RDF	X-tolerant, Test Compaction, MISR
28	Sounil Biswas, R. D. (Shawn) Blanton	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	VTS	2008	DBLP DOI BibTeX RDF	pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
28	Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Bruno De Bus, Koen De Bosschere	Link-time compaction and optimization of ARM executables.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	linker, optimization, Performance, compaction
28	Haifeng He, Saumya K. Debray, Gregory R. Andrews	The revenge of the overlay: automatic compaction of OS kernel code via on-demand code loading.	EMSOFT	2007	DBLP DOI BibTeX RDF	code clustering, embedded systems, code compaction, binary rewriting
28	Christoforos N. Hadjicostis	Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	fault activation probabilities, random testing, compaction, Aliasing probability
28	Sheng Zhang 0008, Sharad C. Seth, Bhargab B. Bhattacharya	Efficient Test Compaction for Pseudo-Random Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	built-in testing, test-data compression, Test compaction, pseudo-random testing
28	Ismet Bayraktaroglu, Alex Orailoglu	Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Test pattern compression, test pattern compaction, on-chip decompression, deterministic decompression, scan chains
28	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Fast Static Compaction Algorithms for Sequential Circuit Test Vectors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Static test set compaction, recurrence subsequence, test generation, fault simulation
28	Albrecht P. Stroele	Test response compaction using arithmetic functions.	VTS	1996	DBLP DOI BibTeX RDF	arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units
28	Slawomir Pilarski, Kevin James Wiebe	Counter-Based Compaction: Delay and Stuck-Open Faults.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	edge counting, ones counting, transition counting, built-in self-test, Aliasing probability, test response compaction
28	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
28	Joseph A. Fisher	Trace Scheduling: A Technique for Global Microcode Compaction.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	global microcode optimization, microcode compaction, parallel instruction scheduling, parallel processing, Data dependency, resource conflict
28	Seongmoon Wang, Kedarnath J. Balakrishnan, Wenlong Wei	X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	output compaction, temporal compactor, blocking unknown values, LFSR reseeding, Built-in Self-Test, BIST, test data compression, MISR, response compaction
28	André Ivanov, Barry K. Tsuji, Yervant Zorian	Programmable BIST Space Compactors.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	BIST methodologies, BIST space compaction, parity tree, BIST compaction, genetic algorithms, Testing, Built-In Self-Test (BIST), design for testability
28	Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang 0046	Foresighted Instruction Scheduling Under Timing Constraints.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	foresighted instruction scheduling, minimum timing information, foresighted compaction, data dependency graph arcs, data dependency information, maximum timing information, greedy compaction algorithms, scheduling, parallel algorithms, parallel programming, graph theory, timing constraints, programming theory, list scheduling, look ahead
26	Li-Yi Wei, Jianwei Han, Kun Zhou 0001, Hujun Bao, Baining Guo, Heung-Yeung Shum	Inverse texture synthesis.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	GPU techniques, texture mapping, texture synthesis
26	Thong Hang, Leonard B. Collard, Mark A. Phifer	Subsidence study for non-crushable containers in slit trenches at the Savannah River site.	SpringSim	2008	DBLP DOI BibTeX RDF	contaminant transport, radioactive waste, radionuclides, environmental science
26	Anshuman Chandra, Rohit Kapur	Interval Based X-Masking for Scan Compression Architectures.	ISQED	2008	DBLP DOI BibTeX RDF	X masking, test, compression, DFT, scan
26	Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch	Design Space Exploration of Media Processors: A Parameterized Scheduler.	ICSAMOS	2007	DBLP DOI BibTeX RDF
26	Weixing Ji, Feng Shi 0009, Baojun Qiao, Qi Zuo, Caixia Liu	Performance Evaluation of a Self-Maintained Memory Module.	RTSS	2007	DBLP DOI BibTeX RDF
26	Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris	Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Nagita Mehrseresht, David S. Taubman	A flexible structure for fully scalable motion-compensated 3-D DWT with emphasis on the impact of spatial scalability.	IEEE Trans. Image Process.	2006	DBLP DOI BibTeX RDF
26	Janusz Rajski, Jerzy Tyszer, Chen Wang 0014, Sudhakar M. Reddy	Finite memory test response compactors for embedded test applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Jianwen Zhu, Fang Fang, Qianying Tang	Calligrapher: a new layout-migration engine for hard intellectual property libraries.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Ondrej Novák, Jirí Zahrádka, Zdenek Plíva	COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits.	EDCC	2005	DBLP DOI BibTeX RDF
26	Naresh Neelapala, Romil Mittal, Jayant R. Haritsa	SPINE: Putting Backbone into String Indexing.	ICDE	2004	DBLP DOI BibTeX RDF
26	Aiman El-Maleh, Ali Al-Suwaiyan	An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits.	VTS	2002	DBLP DOI BibTeX RDF
26	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita	Chip size estimation based on wiring area.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
26	Markus Eiglsperger, Sándor P. Fekete, Gunnar W. Klau	Orthogonal Graph Drawing.	Drawing Graphs	1999	DBLP DOI BibTeX RDF
26	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
26	Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy	Vector Restoration Using Accelerated Validation and Refinement.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
26	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	Compact test sets for high defect coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
26	Onur G. Guleryuz, Michael T. Orchard	Optimized nonorthogonal transforms for image compression.	IEEE Trans. Image Process.	1997	DBLP DOI BibTeX RDF
26	D. Lambidonis, André Ivanov, Vinod K. Agarwal	Fast signature computation for BIST linear compactors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
26	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
26	Roshan A. Gidwani, Naveed A. Sherwani	MISER: An Integrated Three Layer Gridless Channel Router and Compactor.	DAC	1990	DBLP DOI BibTeX RDF
23	Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere	Linux Kernel Compaction through Cold Code Swapping.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	Dynamic test compaction for a random test generation procedure with input cube avoidance.	ASP-DAC	2009	DBLP DOI BibTeX RDF
23	Ju-Yueh Lee, Yu Hu 0002, Rupak Majumdar, Lei He 0001	Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.	ISQED	2009	DBLP DOI BibTeX RDF
23	Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala	Efficient Analog/RF Layout Closure with Compaction Based Legalization.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Kolin Paul, Joël Porquet, Josep Llosa	Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.	DSD	2007	DBLP DOI BibTeX RDF
23	Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian	Trace Compaction using SAT-based Reachability Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF
23	Henry H. Y. Chan, Zeljko Zilic	A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Ali Iranli, Massoud Pedram	Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
23	Suresh Kumar Devanathan, Michael L. Bushnell	Sequential Spectral ATPG Using the Wavelet Transform and Compaction.	VLSI Design	2006	DBLP DOI BibTeX RDF
23	Sounil Biswas, Peng Li 0001, R. D. (Shawn) Blanton, Larry T. Pileggi	Specification Test Compaction for Analog Circuits and MEMS.	DATE	2005	DBLP DOI BibTeX RDF
23	Feng Shi 0010, Yiorgos Makris	SPIN-PAC: test compaction for speed-independent circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Erik H. Volkerink, Subhasish Mitra	Response compaction with any number of unknowns using a new LFSR architecture.	DAC	2005	DBLP DOI BibTeX RDF	LFS, x-compact, compression, BIST, VLSI test
23	Tezaswi Raja, Manish Parashar	Using a Jini based desktop Grid for test vector compaction and a refined economic model.	CCGRID	2004	DBLP DOI BibTeX RDF
23	Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris	Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction.	ISQED	2004	DBLP DOI BibTeX RDF
23	Michael G. Dimopoulos, Panagiotis Linardis	Accelerating the compaction of test sequences in sequential circuits through problem size reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
23	Andrea Di Blas, Arun Jagota, Richard Hughey	A Range-Compaction Heuristic for Graph Coloring.	J. Heuristics	2003	DBLP DOI BibTeX RDF	iterative-greedy algorithm, DIMACS benchmarks, graph coloring
23	Petros Drineas, Yiorgos Makris	Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees.	DATE	2003	DBLP DOI BibTeX RDF
23	Warren Cheung, William S. Evans, Jeremy Moses	Predicated Instructions for Code Compaction.	SCOPES	2003	DBLP DOI BibTeX RDF
23	Ileana Streinu, Sue Whitesides	Rectangle Visibility Graphs: Characterization, Construction, and Compaction.	STACS	2003	DBLP DOI BibTeX RDF
23	Janusz Rajski, Jerzy Tyszer	Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs.	ICCD	2003	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
23	Ismet Bayraktaroglu, Alex Orailoglu	Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.	VTS	2003	DBLP DOI BibTeX RDF
23	Ozgur Sinanoglu, Alex Orailoglu	Efficient Construction of Aliasing-Free Compaction Circuitry.	IEEE Micro	2002	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
23	Subhasish Mitra, Kee Sup Kim	X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.	ITC	2002	DBLP DOI BibTeX RDF
23	Yinyi Lin, Y. J. Wang, T. H. Fan	Compaction of ordered dithered images with arithmetic coding.	IEEE Trans. Image Process.	2001	DBLP DOI BibTeX RDF
23	Markus Eiglsperger, Michael Kaufmann 0001	Fast Compaction for Orthogonal Drawings with Vertices of Prescribed Size.	GD	2001	DBLP DOI BibTeX RDF
23	Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen	Grouped input power sensitive transition an input sequence compaction technique for power estimation.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
23	Ilker Hamzaoglu, Janak H. Patel	Test set compaction algorithms for combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
23	Radu Marculescu, Diana Marculescu, Massoud Pedram	Sequence compaction for power estimation: theory and practice.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
23	Markus Seuring, Michael Gössel	A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits.	WIA	1999	DBLP DOI BibTeX RDF
23	Sony Akkarakaran, P. P. Vaidyanathan	The best basis problem, compaction problem and PCFB design problems [filter banks].	ISCAS (3)	1999	DBLP DOI BibTeX RDF
23	Markus Seuring, Michael Gössel	A Structural Approach for Space Compaction for Sequential Circuits.	DFT	1999	DBLP DOI BibTeX RDF
23	Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti 0001	Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.	VLSI Design	1999	DBLP DOI BibTeX RDF
23	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
23	Diana Marculescu, Radu Marculescu, Massoud Pedram	Sequence Compaction for Probabilistic Analysis of Finite-State Machines.	DAC	1997	DBLP DOI BibTeX RDF
23	Radu Marculescu, Diana Marculescu, Massoud Pedram	Hierarchical Sequence Compaction for Power Estimation.	DAC	1997	DBLP DOI BibTeX RDF
23	Guy Bois, Eduard Cerny	Efficient generation of diagonal constraints for 2-D mask compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
23	Anand Raghunathan, Srimat T. Chakradhar	Dynamic test Sequence compaction for Sequential Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
23	Bechir Ayari, Bozena Kaminska	A new dynamic test vector compaction for automatic test pattern generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Vamsi Boppana, W. Kent Fuchs	Fault dictionary compaction by output sequence removal.	ICCAD	1994	DBLP DOI BibTeX RDF
23	Wolfgang Rülling, Thomas Schilz	A new method for hierarchical compaction [VLSI].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Yang Cai 0003, Martin D. F. Wong	Efficient via shifting algorithms in channel compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Toshio Nakatani, Kemal Ebcioglu	Using a lookahead window in a compaction-based parallelizing compiler.	MICRO	1990	DBLP BibTeX RDF
23	Philip H. Sweany, Steven J. Beaty	Post-compaction register assignment in a retargetable compiler.	MICRO	1990	DBLP BibTeX RDF
23	Yang Cai 0003, D. F. Wong 0001	Optimal via-shifting in channel compaction.	EURO-DAC	1990	DBLP DOI BibTeX RDF
23	Akira Onozawa	Layout Compaction with Attractive and Repulsive Constraints.	DAC	1990	DBLP DOI BibTeX RDF
23	Chi-Yuan Lo, Ravi Varadarajan	An O(n1.5logn) 1-d Compaction Algorithm.	DAC	1990	DBLP DOI BibTeX RDF
23	Pantung Wijaya, Vicki H. Allan	Incremental foresighted local compaction.	MICRO	1989	DBLP DOI BibTeX RDF
23	Richard Anderson, Simon Kahan, Martine D. F. Schlag	An O(n log n) Algorithm for 1-D Tile Compaction.	WG	1989	DBLP DOI BibTeX RDF
23	Chi-Yuan Lo	Automatic Tub Region Generation for Symbolic Layout Compaction.	DAC	1989	DBLP DOI BibTeX RDF
23	Jin-Fuw Lee	A new framework of design rules for compaction of VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Dov Harel, Balakrishnan Krishnamurthy	A Graph Compaction Approach to Fault Simulation.	DAC	1988	DBLP BibTeX RDF
23	Bogong Su, Shiyuan Ding, Jian Wang 0046, Jinshi Xia	Microcode compaction with timing constraints.	MICRO	1987	DBLP DOI BibTeX RDF