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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 4313 publication records. Showing 4313 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | L. F. Fuller, C. Kraaijenvanger |
Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 238-241, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education |
24 | Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli |
Measurement and modeling of MOS transistor current mismatch in analog IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 272-277, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
24 | Wing Ning Li, Sartaj Sahni |
Pull up transistor folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5), pp. 512-521, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Richard Booth 0003, Marvin White |
Simulation of a MOS transistor with spatially nonuniform channel parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12), pp. 1354-1357, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Corrado Pedron, André Stauffer |
Analysis and synthesis of combinational pass transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(7), pp. 775-786, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Christer Svensson, Robert Tjärnström |
Switch-level simulation and the pass transistor EXOR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 994-997, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Chidchanok Lursinsap, Daniel D. Gajski |
A technique for pull-up transistor folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 887-896, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Wen-Jeng Lue, Lawrence P. McNamee |
PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 659-665, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
24 | Hsi-Ching Shih, Jacob A. Abraham |
Transistor-level test generation for physical failures in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 243-249, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
23 | Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Chen Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li 0002, Jingheng Meng, Kai Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaoping Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, Dh Han, Ted Park, Deyuan Xiao, Chao Zhao, Abraham Yoo |
Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMW ![In: IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-7459-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Umer Farooq 0001, M. Hassan Aslam, Muhammad Usman |
On the comparison of memristor-transistor hybrid and transistor-only heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. King Saud Univ. Comput. Inf. Sci. ![In: J. King Saud Univ. Comput. Inf. Sci. 31(4), pp. 514-527, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Getenet Tesega Ayele, Stéphane Monfray, Frédéric Boeuf, Jean-Pierre Cloarec, Serge Ecoffey, Dominique Drouin, Etienne Puyoo, Abdelkader Souifi |
Development of ultrasensitive extended-gate Ion-sensitive-field-effect-transistor based on industrial UTBB FDSOI transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, pp. 264-267, 2017, IEEE, 978-1-5090-5978-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski |
A carbon nanotube transistor based RISC-V processor using pass transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Kumar Prasannajit Pradhan, Prasanna Kumar Sahu |
Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 10(5), pp. 441-447, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Rekha Chaudhary, Amit Sharma, Soumendu Sinha, Jyoti Yadav, Rishi Sharma 0002, Ravindra Mukhiya, Vinod K. Khanna |
Fabrication and characterisation of Al gate n-metal-oxide-semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 10(5), pp. 268-272, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low power 10-transistor full adder design based on degenerate pass transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 496-499, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Dakshina Murthy-Bellur, Marian K. Kazimierczuk |
Isolated Two-Transistor Zeta Converter With Reduced Transistor Voltage Stress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 58-II(1), pp. 41-45, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Surya Shankar Dan, Santanu Mahapatra |
Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 4(5), pp. 449-457, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Alp Arslan Bayrakci |
Fast and accurate statistical timing analysis of digital circuits for timing yield estimation based on transistor level simulations (Transistör düzeyi simülasyonlara dayanan zamanlama verimi tahmini için sayısal devrelerin hızlı ve doğru istatiksel zamanlama analizi) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
23 | Seok Gyu Choi, Jung Hun Oh, Bok-Hyung Lee, Byeong Ok Lim, Sung Woon Moon, Dong-Hoon Shin, Sam-Dong Kim, Jin Koo Rhee |
Comparative Study on Breakdown Characteristics for InGaAs Metamorphic High Electron Mobility Transistor and InGaAs/InP-Composite Channel Metamorphic High Electron Mobility Transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(5), pp. 616-621, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown |
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 89-93, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | James W. Easley |
Transistor characteristics for direct-coupled transistor logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 7(1), pp. 6-16, 1958. The full citation details ...](Pics/full.jpeg) |
1958 |
DBLP DOI BibTeX RDF |
|
21 | Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita |
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 291, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dopant-segregated schottky transistor, nonvolatile configurable memory |
21 | Dennis Huo, Qiaoyan Yu, David Wolpert 0001, Paul Ampadu |
A simulator for ballistic nanostructures in a 2-D electron gas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(1), pp. 5:1-5:21, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
2DEG, Ballistic transport, nanoelectronic device, transistor |
21 | Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw |
Low power circuit design based on heterojunction tunneling transistors (HETTs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 219-224, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SRAM design, low power applications, tunneling transistor |
21 | Suman Datta, Vijaykrishnan Narayanan |
Green transistors to green architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 429-430, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, design, transistor |
21 | Lang Lin, Wayne P. Burleson |
Analysis and mitigation of process variation impacts on Power-Attack Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 238-243, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variation, differential power analysis, Monte Carlo simulation, transistor sizing |
21 | Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito |
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 11-19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch |
21 | Paul Tarau, Brenda Luderman |
Revisiting exact combinational circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1758-1759, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis |
21 | Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr. |
Encountering gate oxide breakdown with shadow transistors to increase reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 111-116, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gate oxide breakdown, modeling, redundancy, logic design, nanotechnology, organic computing, transistor |
21 | Paul Tarau, Brenda Luderman |
A Logic Programming Framework for Combinational Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 23rd International Conference, ICLP 2007, Porto, Portugal, September 8-13, 2007, Proceedings, pp. 180-194, 2007, Springer, 978-3-540-74608-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis |
21 | Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty |
Managing standby and active mode leakage power in deep sub-micron design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 274-279, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS |
21 | Hiroaki Yoshida, Kaushik De, Vamsi Boppana |
Accurate pre-layout estimation of standard cell characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 208-211, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cell characterization, transistor-level optimization, standard cell |
21 | Paul I. Pénzes, Alain J. Martin |
Energy-delay efficiency of VLSI computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 104-111, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy-delay optimization, transistor sizing |
21 | Geun Rae Cho, Tom Chen 0001 |
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 458-463, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic |
21 | Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski |
Uncertainty-aware circuit optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 58-63, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
small uncertainty, optimization, process variation, nonlinear, performance optimization, transistor sizing, circuit tuning |
21 | Richard Martel, V. Derycke, Jörg Appenzeller, Shalom J. Wind, Phaedon Avouris |
Carbon nanotube field-effect transistors and logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 94-98, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FET, SWNT, Schottky barrier, field-effect transistor, circuits, carbon nanotube, nanoelectronics, logic gate, inverter, semiconductor |
21 | Yuriy Makhlin, Gerd Schön, Alexander Shnirman |
Josephson Junction based Quantum Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Algebra Eng. Commun. Comput. ![In: Appl. Algebra Eng. Commun. Comput. 10(4/5), pp. 375-382, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Quantum bit, Josephson junction, Single-electron transistor, Quantum measurement |
21 | Avaneendra Gupta, John P. Hayes |
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 510-547, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation |
21 | Sachin S. Sapatnekar, Weitong Chuang |
Power-delay optimizations in gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 98-114, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
optimization, power estimation, VLSI layout, transistor sizing |
21 | Arabi Keshk, Yukiya Miura, Kozo Kinoshita |
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 120-124, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector |
21 | Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram |
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 505-512, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
simulation, VLSI, timing, Crosstalk, DSM, static, transistor |
21 | Sek M. Chai, Antonio Gentile, D. Scott Wills |
Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 57-71, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
billion-transistor, image processing, technology, SIMD, system modeling, parallel computer architecture, Power density, focal plane |
21 | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
CMOS Combinational Circuit Sizing by Stage-wise Tapering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 985-986, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
tapering, Transistor sizing, resynthesis |
21 | Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw |
Library-less synthesis for static CMOS combinational logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 658-662, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance |
21 | Jonathan T.-Y. Chang, Edward J. McCluskey |
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 446-, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC |
21 | Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien |
A Method for Synthesizing Area Efficient Multilevel PTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 516-519, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multilevel logic synthesis, logic synthesis, Pass transistor logic |
21 | Ayman I. Kayssi |
Macromodeling C- and RC-loaded CMOS inverters for timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 272-276, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling |
21 | S. K. Gupta, M. M. Hasan |
KANSYS: a CAD tool for analog circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 333-334, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications |
21 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 29-32, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
21 | Rik van de Wiel |
High-level test evaluation of asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 63-71, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes |
21 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 187-193, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
21 | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama |
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 92-97, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models |
21 | Sanjay Rekhi, J. Donald Trotter |
HAL: heuristic algorithms for layout synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 185-199, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area |
21 | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 192-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation |
21 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 305-309, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
21 | Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli |
A new switching-level approach to multiple-output functions synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 125-129, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit |
18 | Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha |
GARNET: A detailed on-chip network model inside a full-system simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 33-42, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías |
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design methodology, power consumption, VCO, radio-frequency |
18 | Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya |
Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 247-252, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu |
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(2), pp. 127-135, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
data transition detection, CLA, pipeline, power-aware, ANT |
18 | Munir Ahmad Tarar, Zhizhang (David) Chen |
A Simple Low-Noise Subharmonically Injection-Locked Oscillator for Low-Cost RF Synthesizers and Front-Ends for Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CNSR ![In: Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 5-8 May 2008, Halifax, Nova Scotia, Canada, pp. 217-221, 2008, IEEE Computer Society, 978-0-7695-3135-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Injection locked oscillators, low phase noise, simple frequency synthesizers, wireless communication transceivers |
18 | Ian Kuon, Jonathan Rose |
Area and delay trade-offs in the circuit and architecture design of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 149-158, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, FPGA, architecture |
18 | Victoria Wang, Dejan Markovic |
Linear analysis of random process variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 292-296, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu |
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 14-19, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
differential-pair circuit, radix-2 signed-digit adder, reliability |
18 | Nilesh Modi, Malgorzata Marek-Sadowska |
ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 652-657, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel |
Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1850-1853, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 243-246, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yajie Chen, Liam McDaid, Steve Hall, Peter M. Kelly |
A programmable facilitating synapse device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 1615-1620, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 576-581, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Tarun Sairam, Wei Zhao, Yu Cao 0001 |
Optimizing finfet technology for high-speed and low-power design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 73-77, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power, energy, variations, speed, threshold voltage, FinFET, noise margin |
18 | Tamer Cakici, Keejong Kim, Kaushik Roy 0001 |
FinFET Based SRAM Design for Low Standby Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 127-132, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Kaijian Shi, Zhian Lin, Yi-Min Jiang |
A Power Network Synthesis Method for Industrial Power Gating Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 362-367, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike |
Evaluation of granularity on threshold voltage control in flex power FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 223, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Chunyan Wang 0004 |
Implementation of space-efficient voltage-insensitive capacitances in integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Sergei P. Skorobogatov |
Optically Enhanced Position-Locked Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 61-75, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
semi-invasive attacks, optical probing, side-channel attacks, power analysis |
18 | David Fitrio, Aleksandar Stojcevski, Jugdutt Singh |
Ultra Low Power Weak Inversion Current Steered Digital to Analog Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1543-1546, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 983-986, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
18 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Low-power scan design using first-level supply gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 384-395, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Ilya Obridko, Ran Ginosar |
Low energy asynchronous architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5238-5241, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Olivier Thomas, Amara Amara |
Ultra low voltage design considerations of SOI SRAM memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4094-4097, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Di Long, Xianlong Hong, Sheqin Dong |
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2999-3002, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Geoff V. Merrett, Bashir M. Al-Hashimi |
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 198-207, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Sandrine Bernardini, Jean-Michel Portal, Pascal Masson |
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1404-1405, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Fast Comparisons of Circuit Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 910-915, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 149-154, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Enrico Macii |
Leakage power optimization in standard-cell designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 7, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Changbo Long, Jinjun Xiong, Lei He 0001 |
On optimal physical synthesis of sleep transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 156-161, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
18 | Jörg Langeheine, Martin Trefzer, Daniel Brüderle, Karlheinz Meier, Johannes Schemmel |
On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (1) ![In: Genetic and Evolutionary Computation - GECCO 2004, Genetic and Evolutionary Computation Conference, Seattle, WA, USA, June 26-30, 2004, Proceedings, Part I, pp. 1316-1327, 2004, Springer, 3-540-22344-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy 0001 |
A Novel Low-Power Scan Design Technique Using Supply Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 60-65, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky |
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 52-57, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong |
Low Power 260 k Color TFT LCD One-Chip Driver IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 126-130, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Timing constraints for domino logic gates with timing-dependent keepers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 96-103, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ricardo Augusto da Luz Reis |
Power and Timing Driven Physical Design Automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 348-357, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi |
Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 280-282, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh |
Precomputation-based Guarding for Dynamic and Leakage Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 90-97, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Rafik S. Guindi, Farid N. Najm |
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 61-65, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Piotr R. Sidorowicz, Janusz A. Brzozowski |
A framework for testing special-purpose memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1459-1468, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hajime Shibata, Soji Mori, Nobuo Fujii |
Automated Design of Analog Circuits Using Cell-Based Structure . ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 15-18 July 2002, Alexandria, VA, USA, pp. 85-92, 2002, IEEE Computer Society, 0-7695-1718-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Felix Lustenberger, Hans-Andrea Loeliger |
On mismatch errors in analog-VLSI error correcting decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 198-201, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
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