Search results for "transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
24	Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli	Measurement and modeling of MOS transistor current mismatch in analog IC's.	ICCAD	1994	DBLP DOI BibTeX RDF
24	Wing Ning Li, Sartaj Sahni	Pull up transistor folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
24	Richard Booth 0003, Marvin White	Simulation of a MOS transistor with spatially nonuniform channel parameters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
24	Corrado Pedron, André Stauffer	Analysis and synthesis of combinational pass transistor circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Christer Svensson, Robert Tjärnström	Switch-level simulation and the pass transistor EXOR gate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Chidchanok Lursinsap, Daniel D. Gajski	A technique for pull-up transistor folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Wen-Jeng Lue, Lawrence P. McNamee	PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement.	DAC	1987	DBLP DOI BibTeX RDF
24	Hsi-Ching Shih, Jacob A. Abraham	Transistor-level test generation for physical failures in CMOS circuits.	DAC	1986	DBLP DOI BibTeX RDF
23	Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Chen Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li 0002, Jingheng Meng, Kai Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaoping Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, Dh Han, Ted Park, Deyuan Xiao, Chao Zhao, Abraham Yoo	Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture.	IMW	2023	DBLP DOI BibTeX RDF
23	Umer Farooq 0001, M. Hassan Aslam, Muhammad Usman	On the comparison of memristor-transistor hybrid and transistor-only heterogeneous FPGAs.	J. King Saud Univ. Comput. Inf. Sci.	2019	DBLP DOI BibTeX RDF
23	Getenet Tesega Ayele, Stéphane Monfray, Frédéric Boeuf, Jean-Pierre Cloarec, Serge Ecoffey, Dominique Drouin, Etienne Puyoo, Abdelkader Souifi	Development of ultrasensitive extended-gate Ion-sensitive-field-effect-transistor based on industrial UTBB FDSOI transistor.	ESSDERC	2017	DBLP DOI BibTeX RDF
23	Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski	A carbon nanotube transistor based RISC-V processor using pass transistor logic.	ISLPED	2017	DBLP DOI BibTeX RDF
23	Kumar Prasannajit Pradhan, Prasanna Kumar Sahu	Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor.	IET Circuits Devices Syst.	2016	DBLP DOI BibTeX RDF
23	Rekha Chaudhary, Amit Sharma, Soumendu Sinha, Jyoti Yadav, Rishi Sharma 0002, Ravindra Mukhiya, Vinod K. Khanna	Fabrication and characterisation of Al gate n-metal-oxide-semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor.	IET Comput. Digit. Tech.	2016	DBLP DOI BibTeX RDF
23	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu	Low power 10-transistor full adder design based on degenerate pass transistor logic.	ISCAS	2012	DBLP DOI BibTeX RDF
23	Dakshina Murthy-Bellur, Marian K. Kazimierczuk	Isolated Two-Transistor Zeta Converter With Reduced Transistor Voltage Stress.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
23	Surya Shankar Dan, Santanu Mahapatra	Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuits.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
23	Alp Arslan Bayrakci	Fast and accurate statistical timing analysis of digital circuits for timing yield estimation based on transistor level simulations (Transistör düzeyi simülasyonlara dayanan zamanlama verimi tahmini için sayısal devrelerin hızlı ve doğru istatiksel zamanlama analizi)		2010	RDF
23	Seok Gyu Choi, Jung Hun Oh, Bok-Hyung Lee, Byeong Ok Lim, Sung Woon Moon, Dong-Hoon Shin, Sam-Dong Kim, Jin Koo Rhee	Comparative Study on Breakdown Characteristics for InGaAs Metamorphic High Electron Mobility Transistor and InGaAs/InP-Composite Channel Metamorphic High Electron Mobility Transistor.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
23	Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown	Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.	VLSI Design	2006	DBLP DOI BibTeX RDF
23	James W. Easley	Transistor characteristics for direct-coupled transistor logic circuits.	IRE Trans. Electron. Comput.	1958	DBLP DOI BibTeX RDF
21	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
21	Dennis Huo, Qiaoyan Yu, David Wolpert 0001, Paul Ampadu	A simulator for ballistic nanostructures in a 2-D electron gas.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	2DEG, Ballistic transport, nanoelectronic device, transistor
21	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
21	Suman Datta, Vijaykrishnan Narayanan	Green transistors to green architectures.	ISLPED	2009	DBLP DOI BibTeX RDF	performance, design, transistor
21	Lang Lin, Wayne P. Burleson	Analysis and mitigation of process variation impacts on Power-Attack Tolerance.	DAC	2009	DBLP DOI BibTeX RDF	process variation, differential power analysis, Monte Carlo simulation, transistor sizing
21	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
21	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
21	Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.	Encountering gate oxide breakdown with shadow transistors to increase reliability.	SBCCI	2008	DBLP DOI BibTeX RDF	gate oxide breakdown, modeling, redundancy, logic design, nanotechnology, organic computing, transistor
21	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
21	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
21	Hiroaki Yoshida, Kaushik De, Vamsi Boppana	Accurate pre-layout estimation of standard cell characteristics.	DAC	2004	DBLP DOI BibTeX RDF	cell characterization, transistor-level optimization, standard cell
21	Paul I. Pénzes, Alain J. Martin	Energy-delay efficiency of VLSI computations.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
21	Geun Rae Cho, Tom Chen 0001	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.	ISQED	2002	DBLP DOI BibTeX RDF	Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
21	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski	Uncertainty-aware circuit optimization.	DAC	2002	DBLP DOI BibTeX RDF	small uncertainty, optimization, process variation, nonlinear, performance optimization, transistor sizing, circuit tuning
21	Richard Martel, V. Derycke, Jörg Appenzeller, Shalom J. Wind, Phaedon Avouris	Carbon nanotube field-effect transistors and logic circuits.	DAC	2002	DBLP DOI BibTeX RDF	FET, SWNT, Schottky barrier, field-effect transistor, circuits, carbon nanotube, nanoelectronics, logic gate, inverter, semiconductor
21	Yuriy Makhlin, Gerd Schön, Alexander Shnirman	Josephson Junction based Quantum Computing.	Appl. Algebra Eng. Commun. Comput.	2000	DBLP DOI BibTeX RDF	Quantum bit, Josephson junction, Single-electron transistor, Quantum measurement
21	Avaneendra Gupta, John P. Hayes	CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation
21	Sachin S. Sapatnekar, Weitong Chuang	Power-delay optimizations in gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	optimization, power estimation, VLSI layout, transistor sizing
21	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
21	Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram	Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk.	ISQED	2000	DBLP DOI BibTeX RDF	simulation, VLSI, timing, Crosstalk, DSM, static, transistor
21	Sek M. Chai, Antonio Gentile, D. Scott Wills	Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.	ARVLSI	1999	DBLP DOI BibTeX RDF	billion-transistor, image processing, technology, SIMD, system modeling, parallel computer architecture, Power density, focal plane
21	Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija	CMOS Combinational Circuit Sizing by Stage-wise Tapering.	DATE	1998	DBLP DOI BibTeX RDF	tapering, Transistor sizing, resynthesis
21	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
21	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
21	Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien	A Method for Synthesizing Area Efficient Multilevel PTL Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	multilevel logic synthesis, logic synthesis, Pass transistor logic
21	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
21	S. K. Gupta, M. M. Hasan	KANSYS: a CAD tool for analog circuit synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications
21	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
21	Rik van de Wiel	High-level test evaluation of asynchronous circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes
21	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
21	Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models
21	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
21	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
21	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
21	Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli	A new switching-level approach to multiple-output functions synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit
18	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
18	Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías	Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies.	SBCCI	2009	DBLP DOI BibTeX RDF	design methodology, power consumption, VCO, radio-frequency
18	Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya	Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
18	Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	data transition detection, CLA, pipeline, power-aware, ANT
18	Munir Ahmad Tarar, Zhizhang (David) Chen	A Simple Low-Noise Subharmonically Injection-Locked Oscillator for Low-Cost RF Synthesizers and Front-Ends for Wireless Communications.	CNSR	2008	DBLP DOI BibTeX RDF	Injection locked oscillators, low phase noise, simple frequency synthesizers, wireless communication transceivers
18	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
18	Victoria Wang, Dejan Markovic	Linear analysis of random process variability.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
18	Nilesh Modi, Malgorzata Marek-Sadowska	ECO-Map: Technology remapping for post-mask ECO using simulated annealing.	ICCD	2008	DBLP DOI BibTeX RDF
18	Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel	Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
18	Yajie Chen, Liam McDaid, Steve Hall, Peter M. Kelly	A programmable facilitating synapse device.	IJCNN	2008	DBLP DOI BibTeX RDF
18	Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.	DATE	2007	DBLP DOI BibTeX RDF
18	Tarun Sairam, Wei Zhao, Yu Cao 0001	Optimizing finfet technology for high-speed and low-power design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power, energy, variations, speed, threshold voltage, FinFET, noise margin
18	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
18	Kaijian Shi, Zhian Lin, Yi-Min Jiang	A Power Network Synthesis Method for Industrial Power Gating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
18	Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Evaluation of granularity on threshold voltage control in flex power FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
18	Chunyan Wang 0004	Implementation of space-efficient voltage-insensitive capacitances in integrated circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Sergei P. Skorobogatov	Optically Enhanced Position-Locked Power Analysis.	CHES	2006	DBLP DOI BibTeX RDF	semi-invasive attacks, optical probing, side-channel attacks, power analysis
18	David Fitrio, Aleksandar Stojcevski, Jugdutt Singh	Ultra Low Power Weak Inversion Current Steered Digital to Analog Converter.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
18	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001	Low-power scan design using first-level supply gating.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Ilya Obridko, Ran Ginosar	Low energy asynchronous architectures.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Olivier Thomas, Amara Amara	Ultra low voltage design considerations of SOI SRAM memory cells.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
18	Di Long, Xianlong Hong, Sheqin Dong	Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
18	Sandrine Bernardini, Jean-Michel Portal, Pascal Masson	A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology.	DATE	2004	DBLP DOI BibTeX RDF
18	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast Comparisons of Circuit Implementations.	DATE	2004	DBLP DOI BibTeX RDF
18	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Enrico Macii	Leakage power optimization in standard-cell designs.	SBCCI	2004	DBLP DOI BibTeX RDF
18	Changbo Long, Jinjun Xiong, Lei He 0001	On optimal physical synthesis of sleep transistors.	ISPD	2004	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
18	Jörg Langeheine, Martin Trefzer, Daniel Brüderle, Karlheinz Meier, Johannes Schemmel	On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA.	GECCO (1)	2004	DBLP DOI BibTeX RDF
18	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy 0001	A Novel Low-Power Scan Design Technique Using Supply Gating.	ICCD	2004	DBLP DOI BibTeX RDF
18	A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky	A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.	IOLTS	2004	DBLP DOI BibTeX RDF
18	Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong	Low Power 260 k Color TFT LCD One-Chip Driver IC.	ISQED	2004	DBLP DOI BibTeX RDF
18	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Timing constraints for domino logic gates with timing-dependent keepers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Ricardo Augusto da Luz Reis	Power and Timing Driven Physical Design Automation.	PATMOS	2003	DBLP DOI BibTeX RDF
18	Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi	Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D Converters.	ISVLSI	2003	DBLP DOI BibTeX RDF
18	Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh	Precomputation-based Guarding for Dynamic and Leakage Power Reduction.	ICCD	2003	DBLP DOI BibTeX RDF
18	Rafik S. Guindi, Farid N. Najm	Design Techniques for Gate-Leakage Reduction in CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
18	Piotr R. Sidorowicz, Janusz A. Brzozowski	A framework for testing special-purpose memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
18	Hajime Shibata, Soji Mori, Nobuo Fujii	Automated Design of Analog Circuits Using Cell-Based Structure .	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
18	Felix Lustenberger, Hans-Andrea Loeliger	On mismatch errors in analog-VLSI error correcting decoders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF