Search results for "field-programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	David C. Blight, Robert D. McLeod	Self-Organizing Kohonen Maps for FPL Placement.	FPL	1992	DBLP DOI BibTeX RDF
27	Li-Fei Wu, Marek A. Perkowski	Minimization of Permuted Reed-Muller Trees for Cellular Logic.	FPL	1992	DBLP DOI BibTeX RDF
27	Arne Linde, Tomas Nordström, Mikael Taveniku	Using FPLs to Implement a Reconfigurable Highly Parallel Computer.	FPL	1992	DBLP DOI BibTeX RDF
27	Lennart Lindh, Klaus D. Müller-Glaser, Hans Rauch, Frank Stanischewski	A Real-Time Kernel - Rapid Prototyping with VHDL and FPLs.	FPL	1992	DBLP DOI BibTeX RDF
27	Günter Biehl	Overview of Complex Array-Based PLDs.	FPL	1992	DBLP DOI BibTeX RDF
27	Beat Heeb, Cuno Pfister	Chameleon: A Workstation of a Different Colour.	FPL	1992	DBLP DOI BibTeX RDF
27	Georg J. Kempa, Peter Jung	FPL Based Logic Synthesis of Squarers Using VHDL.	FPL	1992	DBLP DOI BibTeX RDF
27	Naohisa Ohta, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada	New Application of FPLs to Programmable Digital Communication Cirucits.	FPL	1992	DBLP DOI BibTeX RDF
27	Andreas Ast, Reiner W. Hartenstein, Rainer Kress 0002, Helmut Reinig, Karin Schmidt	Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods.	FPL	1992	DBLP DOI BibTeX RDF
27	Dave Allen	Automatic One-Hot Re-Encoding for FPLs.	FPL	1992	DBLP DOI BibTeX RDF
27	Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen	High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.	FPL	1992	DBLP DOI BibTeX RDF
27	Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling	MONTAGNE: An FPL for Synchronous and Asynchronous Circuits.	FPL	1992	DBLP DOI BibTeX RDF
27	Herbert Grünbacher, Alexander Jaud	JAPROC - An 8 bit Micro Controller Design and Its Test Environment.	FPL	1992	DBLP DOI BibTeX RDF
27	Arno Kunzmann	FPL Based Self-Test with Deterministic Test Patterns.	FPL	1992	DBLP DOI BibTeX RDF
27	Bradly K. Fawcett	SRAM-Based FPLs Ease System Verification.	FPL	1992	DBLP DOI BibTeX RDF
27	Dwight D. Hill, Barry K. Britton, William Oswald, Nam Sung Woo, Satwant Singh, Che-Tsung Chen, Bob Krambeck	ORCA: A New Architecture for High-Performance FPLs.	FPL	1992	DBLP DOI BibTeX RDF
27	Paul Shaw, George J. Milne	A Highly Parallel FPL-Based Machine and Its Formal Verification.	FPL	1992	DBLP DOI BibTeX RDF
27	Erik Brunvand	Using FPLs to Prototoype a Self-Timed Computer.	FPL	1992	DBLP DOI BibTeX RDF
27	Masahiro Fujita, Yuji Kukimoto	Patching Method for Lookup-Table Type FPLs.	FPL	1992	DBLP DOI BibTeX RDF
27	Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang	A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
27	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Evaluation of the field-programmable cache: performance and energy consumption.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	adaptive processors, reconfigurable cache memory, static and dynamic energy consumption, performance evaluation, run-time adaptation
27	Gail A. Walters	Innovative technologies I - Applying scalable acalis field programmable multi-cores to HPC.	SC	2006	DBLP DOI BibTeX RDF
27	Phillip H. Jones, John W. Lockwood, Young H. Cho	A Thermal Management and Profiling Method for Reconfigurable Hardware Applications.	FPL	2006	DBLP DOI BibTeX RDF
27	John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan	Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices.	FCCM	2006	DBLP DOI BibTeX RDF
27	Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin	A 2005 review of FPGA arithmetic (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
27	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
27	Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti 0001	A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF
27	James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos	Implementation of a Content-Scanning Module for an Internet Firewall.	FCCM	2003	DBLP DOI BibTeX RDF
27	Sree Ganesan, Ranga Vemuri	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
27	David Karchmer, Jonathan Rose	Definition and solution of the memory packing problem for field-programmable systems.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Robert J. Francis, Jonathan Rose, Kevin Chung	Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF
26	Tim Good, Mohammed Benaissa	AES on FPGA from the Fastest to the Smallest.	CHES	2005	DBLP DOI BibTeX RDF	low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
26	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures.	DFT	1999	DBLP DOI BibTeX RDF	fault-tolerance, Field programmable gate array (FPGA)
26	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
26	Juan Manuel Moreno, Jordi Madrenas, Julio Faura, E. Cantó, Joan Cabestany, Josep Maria Insenser	Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices.	ICES	1998	DBLP DOI BibTeX RDF
25	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
25	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Analog built-in self-test, Transient response analysis, FPAA
25	Scott Miller, Mihai Sima, Michael McGuire	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.	DSD	2007	DBLP DOI BibTeX RDF
25	Steve Trimberger	Redefining the FPGA for the Next Generation.	FPL	2007	DBLP DOI BibTeX RDF
25	Didier Keymeulen, Ricardo Salem Zebulum, Rajeshuni Ramesham, Adrian Stoica, Srinivas Katkoori, Sharon Graves, Frank Novak, Charles Antill	Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics.	AHS	2006	DBLP DOI BibTeX RDF
25	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
25	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
25	Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.	VTS	2005	DBLP DOI BibTeX RDF	FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
25	Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson	Developing Large-Scale Field-Programmable Analog Arrays.	IPDPS	2004	DBLP DOI BibTeX RDF
25	Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas	On-line Testing Field Programmable Analog Array Circuits.	ITC	2004	DBLP DOI BibTeX RDF
25	Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.	FPL	2004	DBLP DOI BibTeX RDF
25	Adam Donlin, Axel Braun, Adam Rose	SystemC for the Design and Modeling of Programmable Systems.	FPL	2004	DBLP DOI BibTeX RDF
25	Erik Schüler, Luigi Carro	A Low Power FPAA for Wide Band Applications.	FPL	2004	DBLP DOI BibTeX RDF
25	Young H. Cho, William H. Mangione-Smith	Deep Packet Filter with Dedicated Logic and Read Only Memories.	FCCM	2004	DBLP DOI BibTeX RDF
25	Abdel Ejnioui, N. Ranganathan	Routing on field-programmable switch matrices.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	John Teifel, Rajit Manohar	Programmable Asynchronous Pipeline Arrays.	FPL	2003	DBLP DOI BibTeX RDF
25	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
25	Javier Ramírez 0001, Antonio García 0001	U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation.	FPL	2002	DBLP DOI BibTeX RDF
25	Sylvain Poussier, Hassan Rabah, Serge Weber	SOPC-based Embedded Smart Strain Gage Sensor.	FPL	2002	DBLP DOI BibTeX RDF
25	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Raoul Tawel, Taher Daud, Anil Thakoor	Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
25	Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel	Initial Studies of a New VLSI Field Programmable Transistor Array.	ICES	2001	DBLP DOI BibTeX RDF
25	Gordon J. Brebner, Oliver Diessel	Chip-Based Reconfigurable Task Management.	FPL	2001	DBLP DOI BibTeX RDF
25	Hamish Fallside, Michael John Sebastian Smith	Internet Connected FPL.	FPL	2000	DBLP DOI BibTeX RDF
25	Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen	Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
25	Guy Lecurieux Lafayette	Programmable System Level Integration Brings System-on-Chip Design to the Desktop.	FPL	2000	DBLP DOI BibTeX RDF
25	Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja	The design of an SRAM-based field-programmable gate array. I. Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
25	Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
25	Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet	Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
25	Stephen Charlwood, Philip James-Roxby	Evaluation of the XC6200-series Architecture for Cryptographic Applications.	FPL	1998	DBLP DOI BibTeX RDF
25	Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser	A new field programmable system-on-a-chip for mixed signal integration.	ED&TC	1997	DBLP DOI BibTeX RDF
25	M. Agarwala, Poras T. Balsara	An architecture for a DSP field-programmable gate array.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
25	Russell D. Meier 0001	Rapid prototyping of a RISC architecture for implementation in FPGAs.	FCCM	1995	DBLP DOI BibTeX RDF
25	Michael Demjanenko, Shambhu J. Upadhyaya	Yield enhancement of field programmable logic arrays by inherent component redundancy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
25	Maxwell Walton, Gary Gréwal, Gerarda A. Darlington	Parallel FPGA-based implementation of scatter search.	GECCO	2010	DBLP DOI BibTeX RDF	0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search
25	Jin Hwan Park, H. K. Dai 0001	Reconfigurable hardware solution to parallel prefix computation.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
25	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
25	Adam Handzlik, Andrzej Jablonski	"Chameleon" Software Defined Control Platform.	EUROCAST	2007	DBLP DOI BibTeX RDF	Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core
25	Ali El Kateeb, Lubna Al Azzawi	Low Cost HIV Testing System for Tele-Health Applications.	AINA Workshops (2)	2007	DBLP DOI BibTeX RDF	HIV kits, HIV screening, Field programmable gate array (FPGA), System-on-chip (SOC)
25	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
25	Slawomir Cichon, Marek Gorgon, Miroslaw Pac	Handel-C Design Enhancement for FPGA-Based DV Decoder.	ARC	2006	DBLP DOI BibTeX RDF	video decompression, field programmable gate array, Parallel algorithm, high level languages
25	Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell	FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	EBCOT, JPEG 2000 image compression, arithmetic encoder, field programmable gate array
25	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	IEEE-Compliant IDCT on FPGA-Augmented TriMedia.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor
25	Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña	Power Consumption Management on FPGAs.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
25	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
25	Phillip A. Laplante, William Gilreath	One Instruction Set Computers for Image Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	OISC, one-instruction computing, FPGA, field programmable gate array, image processing, reconfigurable computing
25	Philip Brisk, Adam Kaplan, Majid Sarrafzadeh	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.	DAC	2004	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP)
25	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
25	Javier Ramírez 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García 0001, Antonio Lloris-Ruíz	Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	RNS arithmetic, custom integrated circuit, field-programmable logic devices, discrete wavelet transform
25	Byoungro So, Pedro C. Diniz, Mary W. Hall	Using estimates from behavioral synthesis tools in compiler-directed design space exploration.	DAC	2003	DBLP DOI BibTeX RDF	synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
25	Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang	Determining appropriate precisions for signals in fixed-point IIR filters.	DAC	2003	DBLP DOI BibTeX RDF	finite word length effects, infinite impulse response filter, field programmable gate array, design methodology
25	J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol	Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	quadrature demodulation, digital down conversion, polyphase filtering, field programmable gate arrays, digital filtering
25	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi	A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications.	DELTA	2002	DBLP DOI BibTeX RDF	Fault Tolerance, Field programmable Gate Arrays, Multistage Interconnection Network, Space Applications
25	Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey	Fast Run-Time Fault Location in Dependable FPGA-Based Applications.	DFT	2001	DBLP DOI BibTeX RDF	Run-time fault location, Field-Programmable Gate Array (FPGA), concurrent error detection, on-line testing
25	Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai	Efficient routability check algorithms for segmented channel routing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field programmable gate arryas (FPGAs), segmented channel, routing
25	Sree Ganesan, Ranga Vemuri	A Methodology for Rapid Prototyping of Analog Systems.	ICCD	1999	DBLP DOI BibTeX RDF	rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays
25	Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra	Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems.	DFT	1999	DBLP DOI BibTeX RDF	transient fault detection, Field Programmable Gate Array, TMR systems
25	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
25	Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
25	Donald L. Hung, Antonio Arsgao, Jorge L. Silva, Eduardo Marques, Karl Hillesland	UB1 - a recurrent neural network based parallel machine for solving simultaneous linear equations.	SBRN	1997	DBLP DOI BibTeX RDF	UB1 recurrent neural network, simultaneous linear equation solving, synchronous execution, field programmable gate arrays, real-time systems, parallel machine, systolic array, neural chips, ring topology, neural net architecture
25	Nalini K. Ratha, Kalle Karu, Shaoyun Chen, Anil K. Jain 0001	A Real-Time Matching System for Large Fingerprint Databases.	IEEE Trans. Pattern Anal. Mach. Intell.	1996	DBLP DOI BibTeX RDF	minutiae points, field programmable gate array, indexing, image registration, Image database, fingerprint matching
25	T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael	Faulty chip identification in a multi chip module system.	VTS	1996	DBLP DOI BibTeX RDF	faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
25	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
25	Tong Liu 0007, Fabrizio Lombardi, José Salinas	Diagnosis of interconnects and FPICs using a structured walking-1 approach.	VTS	1995	DBLP DOI BibTeX RDF	field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
25	Max Roger Pokam, Jean-Francois Guillaud, Gérard Michel	Integrated multimedia in manufacturing networks using ATM.	LCN	1995	DBLP DOI BibTeX RDF	manufacturing networks, continuous media data flows, process control plants, multimedia application service element, intelligent communication board, high level communication functions, multimedia load, field programmable gate array, multimedia, asynchronous transfer mode, ATM, local area networks, multimedia computing, manufacturing processes, real-time distributed systems, factory automation, TCP/IP protocol
24	Paul E. Hasler	Low-Power Programmable Signal Processing, invited.	IWSOC	2005	DBLP DOI BibTeX RDF