Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Sying-Jyan Wang, Tsi-Ming Tsai	Test and diagnosis of fault logic blocks in FPGAs.	ICCAD	1997	DBLP DOI BibTeX RDF	FPGA, Test, Diagnosis, BIST
21	James G. Eldredge, Brad L. Hutchings	Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
21	Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu 0001	A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
21	Fran Hancheck, Shantanu Dutt	Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.	ICCD	1996	DBLP DOI BibTeX RDF
21	Larry McMurchie, Carl Ebeling	PathFinder: A Negotiation-based Performance-driven Router for FPGAs.	FPGA	1995	DBLP DOI BibTeX RDF
21	Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001	Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.	FPGA	1995	DBLP DOI BibTeX RDF
21	Erik Brunvand	Using FPGAs to implement self-timed systems.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
21	Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen	DSP system integration and prototyping with FPGAS.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
21	Kenneth M. Zick, John P. Hayes	On-line sensing for healthier FPGA systems.	FPGA	2010	DBLP DOI BibTeX RDF	on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management
21	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
21	Pranav Vaidya, Jaehwan John Lee, Francis Bowen, Yingzi Du, Chandima H. Nadungodage, Yuni Xia	Symbiote: a reconfigurable logic assisted data streammanagement system (RLADSMS).	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	fpgas, hardware accelerator, data stream management systems
21	Walid A. Najjar, Jason R. Villarreal	Reconfigurable Computing in the New Age of Parallelism.	SAMOS	2009	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing
21	Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Renato V. B. Henriques, Marcelo Lubaszewski	Design of an embedded system for the proactive maintenance of electrical valves.	SBCCI	2009	DBLP DOI BibTeX RDF	electromechanical systems, novel applications of FPGAs, testability issues, embedded systems
21	Chen Huang 0005, Frank Vahid	Transmuting coprocessors: dynamic loading of FPGA coprocessors.	DAC	2009	DBLP DOI BibTeX RDF	coprocessing, FPGAs, online algorithms, dynamic optimization, acceleration, runtime configuration
21	Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood	Designing secure systems on reconfigurable hardware.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	controlled sharing, enforcement mechanisms, security primitives, Field programmable gate arrays (FPGAs), static analysis, advanced encryption standard (AES), security policies, systems-on-a-chip (SoCs), separation, isolation, memory protection, reference monitors, hardware security, execution monitors
21	Scott Davidson 0001	How to make your own processor architecture.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	system-on-chip computing, FPGAs, ASICs, processor architecture, processor design
21	Rui Marcelino, Horácio C. Neto, João M. P. Cardoso	Sorting Units for FPGA-Based Embedded Systems.	DIPES	2008	DBLP DOI BibTeX RDF	FPGAs, embedded systems, sorting, special-purpose architecture
21	Duncan A. Buell, Tarek A. El-Ghazawi, Kris Gaj, Volodymyr V. Kindratenko	Guest Editors' Introduction: High-Performance Reconfigurable Computing.	Computer	2007	DBLP DOI BibTeX RDF	HPRCs, FPGAs, reconfigurable computing
21	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
21	Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002	Hardware-based text-to-braille translator.	ASSETS	2006	DBLP DOI BibTeX RDF	braille translation, FPGAs, VHDL
21	David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
21	Padmini Gopalakrishnan, Xin Li 0001, Lawrence T. Pileggi	Architecture-aware FPGA placement using metric embedding.	DAC	2006	DBLP DOI BibTeX RDF	FPGAs, placement, metric embedding
21	Ana Toledo Moreo, Cristina Vicente-Chicote, Juan Suardíaz Muro, Sergio A. Cuenca	Xilinx System Generator Based HW Components for Rapid Prototyping of Computer Vision SW/HW Systems.	IbPRIA (1)	2005	DBLP DOI BibTeX RDF	FPGAs, prototyping, Simulink, co-simulation, image processing applications
21	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
21	Alberto Bertoni, Paola Campadelli, Giuliano Grossi	A Neural Algorithm for the Maximum Clique Problem: Analysis, Experiments, and Circuit Implementation.	Algorithmica	2002	DBLP DOI BibTeX RDF	FPGAs, Combinatorial Optimization, Hopfield networks, Maximum Clique
21	Narasimhan Ramasubramanian, Ram Subramanian, Santosh Pande	Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	operator parallelism, FPGAs, parallel computing, Compilers, loop transformation, reconfigurable systems
21	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri	Framework for Synthesis of Virtual Pipelines.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration
21	Peter Bellows, Brad L. Hutchings	Designing Run-Time Reconfigurable Systems with JHDL.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGAs, image processing, CAD, configurable computing
21	Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai	Efficient routability check algorithms for segmented channel routing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field programmable gate arryas (FPGAs), segmented channel, routing
21	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
21	Christian Kreiner, Christian Steger, Reinhold Weiss	A Hardware/Software Cosimulation Environment for DSP Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF	FPGAs, ADA, VHDL, digital signal processors, cosimulation
21	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
21	Carl Ebeling, Darren C. Cronquist, Paul Franklin	Configurable computing: the catalyst for high-performance architectures.	ASAP	1997	DBLP DOI BibTeX RDF	high-performance architectures, cost-performance, application-specific computation pipelines, static configuration, FPGAs, computational complexity, computer architectures, configurable computing, dynamic control, RaPiD, application-specific hardware
21	Vaughn Betz, Jonathan Rose	Directional bias and non-uniformity in FPGA global routing architectures.	ICCAD	1996	DBLP DOI BibTeX RDF	Field-Programmable Gate Arrays (FPGAs), Placement, Global Routing
21	Adam Postula, David Abramson 0001, Paul Logothetis	The Design of a Specialised Processor for the Simulation of Sintering A. Postula.	EUROMICRO	1996	DBLP DOI BibTeX RDF	specialised processor, sintering simulation, metallurgical sintering, commercially available gate array technology, Xilinx FPGA, Aptix FPIC switch technology, FPGAs, Monte-Carlo simulation, special purpose computers
21	Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
21	Shashidhar Thakur, D. F. Wong 0001	Simultaneous area and delay minimum K-LUT mapping for K-exact networks.	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
21	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
20	Michael Mattioli	FPGAs in Client Compute Hardware: Despite certain challenges, FPGAs provide security and performance benefits over ASICs.	ACM Queue	2021	DBLP DOI BibTeX RDF
20	Yue Zha, Jing Li 0073	When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs.	ASPLOS	2021	DBLP DOI BibTeX RDF
20	Matteo Bertolino	Efficient scheduling of applications onto cloud FPGAs. (Ordonnancement efficace des applications sur cloud FPGAs).		2021	RDF
20	Frank Bubenhagen	Analysis and Enhancement of a Fault-Tolerant NoC for SRAM-based FPGAs in Space Applications (Analyse und Erweiterung eines fehler-toleranten NoC für SRAM-basierte FPGAs in Weltraumapplikationen) (PDF / PS)		2020	DOI RDF
20	Georgios Christodoulis	Adapting a HPC runtime system to FPGAs. (Adaption d'un système HPC pour intégrer des FPGAs).		2019	RDF
20	Andrew E. Wilson, Michael J. Wirthlin	Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet-Moundi	High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Atiyehsadat Panahi, Keaten Stokke, David Andrews 0001	A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich	Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt	Volcan: System Integration of HLS and HMC on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin	Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Corbin Thurlow, Hayden Rowberry, Michael J. Wirthlin	TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Andrei Hagiescu, Martin Langhammer, Bogdan Pasca 0001, Philip Colangelo, Jason Thong, Niayesh Ilkhani	BFLOAT MLP Training Accelerator for FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Sina Boroumand, Philip Brisk	Approximate Adder Tree Synthesis for FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
20	Paul Sathre, Ahmed E. Helal, Wu-chun Feng	A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and Transformation.	ReConFig	2018	DBLP DOI BibTeX RDF
20	Daniel Ziener, Jutta Pirkl, Jürgen Teich	Configuration Tampering of BRAM-based AES Implementations on FPGAs.	ReConFig	2018	DBLP DOI BibTeX RDF
20	Vladimir Estivill-Castro, René Hexel, Morgan McColl	High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAs.	ReConFig	2018	DBLP DOI BibTeX RDF
20	Vincent Mirian, Paul Chow	Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs.	IWOCL	2017	DBLP DOI BibTeX RDF
20	Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck	Continuous live-tracing as debugging approach on FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic	Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Ian J. Barge, Cristinel Ababei	H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Andreas Engel 0003, Andreas Koch 0001	Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Pongstorn Maidee, Alireza Kaviani, Kevin Zeng	LinkBlaze: Efficient global data movement for FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Diogo Parrinha, Ricardo Chaves	Flexible and low-cost HSM based on non-volatile FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Tuncay Soylu, Oguzhan Erdem, Aydin Carus, Edip S. Güner	Simple CART based real-time traffic classification engine on FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Muhammad Usman Tariq, Umer I. Cheema, Fahad Saeed	Power-efficient and highly scalable parallel graph sampling using FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Girish Deshpande, Dinesh K. Bhatia	Microchannels for thermal management in FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	David C. Keezer, Jingchi Yang	Biologically inspired hierarchical structure for self-repairing FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Hanqing Zeng, Chi Zhang 0022, Viktor K. Prasanna	Fast generation of high throughput customized deep learning accelerators on FPGAs.	ReConFig	2017	DBLP DOI BibTeX RDF
20	Pankaj Shanker	Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs.	FPGA	2016	DBLP DOI BibTeX RDF
20	Farid Lahrach	Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM. (Fault tolerance of SRAM-based FPGAs circuits).		2016	RDF
20	Benjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert	1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Thomas B. Preußer, Markus Krause	Survey on and re-evaluation of wide adder architectures on FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Sen Ma, David Andrews 0001, Shanyuan Gao, Jaime Cummins	Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey	The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Lukas Johannes Jung, Christian Hochberger	Optimal processor interface for CGRA-based accelerators implemented on FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Jens Rettkowski, Konstantin Friesen, Diana Göhringer	RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Michail S. Vavouras, Christos-Savvas Bouganis	Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Wen Wang 0007, Jakub Szefer, Ruben Niederhagen	Solving large systems of linear equations over GF(2) on FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Skip Booth	Keynote 2 - FPGAs in the datacenter - A software view.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Florian Rittner, Robért Glein, Albert Heuberger	Detection and Isolation of permanent faults in FPGAs with remote access.	ReConFig	2016	DBLP DOI BibTeX RDF
20	Frederik Grüll	Acceleration of biomedical image processing and reconstruction with FPGAs (Beschleunigung biomedizinischer Bildverarbeitung und -rekonstruktion mit FPGAs) (PDF / PS)		2015	RDF
20	Vincent Mirian, Paul Chow	Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
20	Gordon Ghiu	Keynote 2 - Towards datacenter computing with FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
20	Alfonso Rodríguez 0002, Juan Valverde, Eduardo de la Torre	Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
20	Stefan Gehrer, Sebastien Leger, Georg Sigl	Aging effects on ring-oscillator-based physical unclonable functions on FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
20	Vincent Mirian, Paul Chow	UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
20	Karim Moussa Ali Abdellatif	Authenticated Encryption on FPGAs from the Reconfigurable Part to the Static Part. (Chiffrement authentifié sur FPGAs de la partie reconfigurable à la partie static).		2014	RDF
20	Pei Luo, Yunsi Fei, Xin Fang 0001, A. Adam Ding, Miriam Leeser, David R. Kaeli	Power analysis attack on hardware implementation of MAC-Keccak on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Sam Skalicky, Sonia López, Marcin Lukowiak, Christopher A. Wood	Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Rui Policarpo Duarte, Christos-Savvas Bouganis	Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Cristinel Ababei, Rajesh G. Kavasseri, Mohammad A. Zare	Net reordering and multicommodity flow based global routing for FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Rico Backasch, Gerald Hempel, Stefan Werner 0002, Sven Groppe, Thilo Pionteck	Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas	On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek	PoC-align: An open-source alignment accelerator using FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Lei Xu 0012, Pham Dang Khoa, Seung-Hun Kim, Won Woo Ro, Weidong Shi	LUT based secure cloud computing - An implementation using FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Hongyuan Ding, Miaoqing Huang	A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Bernhard Jungk, Leandro Rodrigues Lima, Matthias Hiller	A systematic study of lightweight hash functions on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
20	Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez	Lightweight and compact solutions for secure reconfiguration of FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
20	Matthias Hinkfoth, Ralf Joost, Ralf Salomon	Improving calibration precision of signal-delay-based time measurement systems in FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
20	Kiran Kumar Matam, Viktor K. Prasanna	Energy-efficient large-scale matrix multiplication on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
20	Ali Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong	A platform for secure IP integration in Xilinx Virtex FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF