Search results for "CMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Dominique Python, Manfred Punzenberger, Christian C. Enz	A 1-V CMOS log-domain integrator.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
18	O. Kibar, Philippe J. Marchand, Sadik C. Esener	High-speed CMOS switch designs for free-space optoelectronic MIN's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
18	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Power dissipated by CMOS gates driving lossless transmission lines.	ISLPED	1998	DBLP DOI BibTeX RDF
18	Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl	Minimum supply voltage for bulk Si CMOS GSI.	ISLPED	1998	DBLP DOI BibTeX RDF
18	Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser	CMOS front end components for micropower RF wireless systems.	ISLPED	1998	DBLP DOI BibTeX RDF
18	Emilio Benedetti, Luisa Consolini	CMOS - Change Management Of Software ESSI PIE nr. 23661.	EUROMICRO	1998	DBLP DOI BibTeX RDF
18	Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell	CMOS IC reliability indicators and burn-in economics.	ITC	1998	DBLP DOI BibTeX RDF
18	Hiok-Tiaq Ng, David J. Allstot	CMOS current steering logic for low-voltage mixed-signal integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
18	Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang	Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
18	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for low power CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian	Transistor Chaining in CMOS Leaf Cells of Planar Topology.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
18	Shih-Lien Lu	Implementation of micropipelines in enable/disable CMOS differential logic.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
18	Debabrata Ghosh, S. K. Nandy 0001	Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
18	Bradley S. Carlson, Suh-Juch Lee	Delay optimization of digital CMOS VLSI circuits by transistor reordering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
18	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
18	Abdolreza Nabavi-Lishi, Nicholas C. Rumin	Inverter models of CMOS gates for supply current and delay evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
18	S. Wayne Bollinger, Scott F. Midkiff	Test generation for IDDQ testing of bridging faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
18	Marcel Jacomet, Walter Guggenbühl	Layout-dependent fault analysis and test synthesis for CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
18	Francisco J. Pelayo, Begoña Pino, Alberto Prieto, Julio Ortega 0001, F. J. Fernández	CMOS Implementation of Synapse Matrices with Programmable Analog Weights.	IWANN	1991	DBLP DOI BibTeX RDF
18	Chung-Yu Wu, Ming-Chuen Shiau	Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
18	Gopal Gupta 0001, Niraj K. Jha	A universal test set for CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Ching-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni	A Rule-Based Circuit Representation for Automated CMOS Design and Verification.	DAC	1987	DBLP DOI BibTeX RDF
17	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
17	Yuan Cao 0003, Fang Tang, Amine Bermak, Thinh M. Le	A Smart CMOS Image Sensor with On-chip Hot Pixel Correcting Readout Circuit for Biomedical Applications.	DELTA	2010	DBLP DOI BibTeX RDF	hot pixel correction, biomedical applications, CMOS image sensor
17	Fang Tang, Amine Bermak	Read-out Circuit Analysis for High-speed Low-noise VCO Based APS CMOS Image Sensor.	DELTA	2010	DBLP DOI BibTeX RDF	APS imager, high speed, CMOS image sensor, low noise
17	Kalyan Bhattacharyya	23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently.	VLSI Design	2010	DBLP DOI BibTeX RDF	Distributed oscillator, CMOS RF IC, Monolithic Microwave Integrated Circuits, VCO
17	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.	VLSI Design	2010	DBLP DOI BibTeX RDF	Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin
17	Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao 0002, Eric A. M. Klumperink	Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.	VLSI Design	2010	DBLP DOI BibTeX RDF	tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit
17	Calvin Plett, Robson Nunes de Lima	Low-power CMOS transceivers with on-chip antennas for short-range radio-frequency communication.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS transceiver, injection locked, integrated antenna, medical sensor readout, PLL
17	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.	ISLPED	2009	DBLP DOI BibTeX RDF	bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
17	Roger Y. Chen, Ming-Jen Chang	A CMOS Variable-gain Fully-differential Transimpedance Amplifier for Multimedia Data Links.	IIH-MSP	2009	DBLP DOI BibTeX RDF	CMOS optical preamplifiers, current amplifiers, infrared wireless optical receivers, transimpedance amplifiers, TIA
17	Yangyuan Wang, Xing Zhang 0002, Xiaoyan Liu, Ru Huang	Novel devices and process for 32 nm CMOS technology and beyond.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	high-k, non-planar MOSFET, quasi-ballistic transport, CMOS technology, metal gate
17	Monica Figueiredo, Rui L. Aguiar	A Study on CMOS Time Uncertainty with Technology Scaling.	PATMOS	2008	DBLP DOI BibTeX RDF	Uncertainty, Noise, CMOS, Scaling, Jitter
17	Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto	An Experimental Study on Latch Up Failure of CMOS LSI.	SSIRI	2008	DBLP DOI BibTeX RDF	latch up, CMOS LSI
17	Laurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard	Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS Analog Integrated Circuits, Nonlinear Distortion, Predistorsion, Multi-Layer Perceptrons, Neural Network Architecture
17	Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	intermodulation compensation, reconfigurable CMOS low noise amplifier, variable bias circuit, self compensation, power reduction
17	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF	on-chip signaling circuit, impedance-unmatched CML driver, differential transmission-line, CML receiver, CML buffer, load resistance tuning, 10 Gbit/s, CMOS technology, power reduction, 90 nm
17	Cary Gunn	CMOS Photonics for High-Speed Interconnects.	IEEE Micro	2006	DBLP DOI BibTeX RDF	CMOS photonics, high-speed optical communications, Luxtera, 10-Gbps
17	Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock	40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	CMOS, DRAM, ultrasound, FIFO, embedded memory
17	Suchitav Khadanga	Synchronous programmable divider design for PLL Using 0.18 um cmos technology.	IWSOC	2003	DBLP DOI BibTeX RDF	programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
17	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
17	Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai	Variable threshold CMOS (VTCMOS) in series connected circuits.	ISLPED	2001	DBLP DOI BibTeX RDF	body effect factor, degradation factor, series connected circuits, substrate bias, variable threshold voltage CMOS, velocity saturation
17	Tirdad Sowlati, Vickram Vathulya, Domine Leenaerts	High density capacitance structures in submicron CMOS for low power RF application.	ISLPED	2001	DBLP DOI BibTeX RDF	HiPerLAN, RF passives, interconnect, Bluetooth, CMOS
17	Song Ye, Koji Yano, C. André T. Salama	1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS.	ISLPED	2001	DBLP DOI BibTeX RDF	lateral bipolar transistor, low power, CMOS, RF, mixer
17	Kwang-Bo Cho, Alexander Krymski, Eric R. Fossum	A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor.	ISLPED	2001	DBLP DOI BibTeX RDF	self-clocked, low-power, CMOS, image sensor, low-voltage, active pixel sensor
17	Jian Liu, Rafic Z. Makki, Ayman I. Kayssi	Dynamic Power Supply Current Testing of CMOS SRAMs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	transient power supply current (i DDT), transient current sensor, disturb fault, CMOS SRAM
17	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
17	Christer Svensson, Atila Alvandpour	Low power and low voltage CMOS digital circuit techniques.	ISLPED	1998	DBLP DOI BibTeX RDF	low power, CMOS, digital circuits, low voltage
16	Tien-Yu Lo, Chung-Chih Hung	1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
15	Sansiri Tanachutiwat, Ji Ung Lee, Wei Wang 0003, Chun Yung Sung	Reconfigurable multi-function logic based on graphene P-N junctions.	DAC	2010	DBLP DOI BibTeX RDF	graphene, p-n junction, logic gate, device, reconfigurable logic
15	Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam	Multiband RF-interconnect for reconfigurable network-on-chip communications.	SLIP	2009	DBLP DOI BibTeX RDF	fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor
15	Debasish Das, William Scott, Shahin Nazarian, Hai Zhou 0001	An efficient current-based logic cell model for crosstalk delay analysis.	ISQED	2009	DBLP DOI BibTeX RDF
15	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.	PATMOS	2008	DBLP DOI BibTeX RDF
15	Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija	Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.	PATMOS	2007	DBLP DOI BibTeX RDF
15	Kris Tiri, Ingrid Verbauwhede	A digital design flow for secure integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Feng Wang 0004, Yuan Xie 0001, Kerry Bernstein, Yan Luo	Dependability Analysis of Nano-scale FinFET circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
15	Jeffrey Bokor	Prospects for emerging nanoelectronics in mainstream information processing systems.	ICCAD	2006	DBLP DOI BibTeX RDF	nanoelectronics
15	Kornika Moolpho, Jitkasame Ngarmnil	Low Voltage High-Performance Class-AB FGMOS Buffer.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Junyoung Park, Sung Je Hong, Jong Kim 0001	Energy-saving design technique achieved by latched pass-transistor adiabatic logic.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio	A constant-gm rail-to-rail op amp input stage using dynamic current scaling technique.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Designing logic circuits for probabilistic computation in the presence of noise.	DAC	2005	DBLP DOI BibTeX RDF	nanodevices, reliability, Markov random fields, emerging technologies, noise immunity, probabilistic computing, subthreshold operation
15	T. J. Thorp, G. S. Yee, Carl M. Sechen	Design and synthesis of dynamic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
15	O. Milter, Avinoam Kolodny	Crosstalk noise reduction in synthesized digital logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
15	Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi	A Novel Technique for Noise-Tolerance in Dynamic Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
15	Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang	Reshaping EDA for power.	DAC	2003	DBLP DOI BibTeX RDF
15	Unni Narayanan, Ki-Seok Chung, Taewhan Kim	Enhanced bus invert encodings for low-power.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Geun Rae Cho, Tom Chen 0001	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.	ISQED	2002	DBLP DOI BibTeX RDF	Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
15	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Robust subthreshold logic for ultra-low power operation.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
15	Takahiro Saito, Takashi Komatsu	A high-resolution image acquisition method with defect-pixel recovery for solid-state image sensors.	ICIP (2)	2001	DBLP DOI BibTeX RDF
15	Cong-Kha Pham	A novel synapses circuit and its application to a neural-based A/D converter.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
15	Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang	Energy-efficient skewed static logic design with dual Vt.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung	A low-power high driving ability voltage control oscillator used in PLL.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Wen-Tsong Shiue	Leakage power estimation and minimization in VLSI circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
15	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
15	Ivo Bolsens, Wojtek Maly, Ludo Deferm, Jo Borel, Harry J. M. Veendrick	Single Chip or Hybrid System Integration.	DATE	1999	DBLP DOI BibTeX RDF
15	Mostafa I. H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman	Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF
15	Tyler Thorp, Gin Yee, Carl Sechen	Design and Synthesis of Monotonic Circuits.	ICCD	1999	DBLP DOI BibTeX RDF
15	Farid N. Najm, Ibrahim N. Hajj	The complexity of fault detection in MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	Veronika Eisele, Bernhard Hoppe, Oliver Kiehl	Transmission gate delay models for circuit optimization.	EURO-DAC	1990	DBLP DOI BibTeX RDF
14	Kevin J. Nowka	Technology variability and uncertainty implications for power- efficient VLSI systems.	ISLPED	2010	DBLP DOI BibTeX RDF	tools, technology, cmos, circuits
14	Melvin A. Breuer	Hardware that produces bounded rather than exact results.	DAC	2010	DBLP DOI BibTeX RDF	computational fabrics, CMOS, error-rate, performance degradation, error-tolerance
14	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
14	Juan José Carrillo, Elkim Roa, José Vieira, Wilhelmus A. M. Van Noije	A low-voltage bandgap reference source based on the current-mode technique.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS voltage reference, temperature coefficient, analog circuits, low voltage
14	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
14	Hiroki Sato, Sho Ogura, Tadaaki Hosaka, Takayuki Hamamoto, Akira Kubota, Ryutaro Oi, Kazuya Kodama	Arbitrary viewpoint image synthesis for real-time processing system using multiple image sensors.	VRCAI	2009	DBLP DOI BibTeX RDF	arbitrary viewpoint image, object shape estimation, real-time synthesis, FPGA, CMOS image sensor
14	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
14	Hua Wang, Francky Catthoor, Miguel Miranda, Wim Dehaene	Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CMOS buffer, Low power design, Trade-offs
14	Sachin S. Sapatnekar	Building your yield of dreams.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM
14	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.	PATMOS	2008	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response
14	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Analog hardware implementation of a vector quantizer for focal-plane image compression.	SBCCI	2008	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
14	Roman Ostroumov, Kang L. Wang	On Power Dissipation in Information Processing.	ITNG	2008	DBLP DOI BibTeX RDF	nanoscale architectures, CMOS, power dissipation
14	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
14	Shin-Yi Lin, Chih-Tsun Huang	A High-Throughput Low-Power AES Cipher for Network Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, low-power AES cipher, two-stage pipeline, CCM mode, design-for-test circuitry, 4.27 Gbits/s, 333 MHz, 40.9 mW, CMOS technology, network applications
14	Ivan Chee Hong Lai, Minoru Fujishima	Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems.	ASP-DAC	2007	DBLP DOI BibTeX RDF	1.2 V, pseudomillimeter-wave up-conversion mixer, vehicular radar systems, broadband up-conversion mixer, on-chip Marchand baluns, reduced substrate losses, integrated mixer, 20 to 26 GHz, 2 dB, 11.1 mW, CMOS technology, capacitive coupling, 90 nm
14	Noriyuki Miura, Tadahiro Kuroda	A 1Tb/s 3W Inductive-Coupling Transceiver Chip.	ASP-DAC	2007	DBLP DOI BibTeX RDF	150 ps, inductive-coupling transceiver chip, data transceivers, clock transceivers, biphase modulation, improved noise immunity, 1 Gbit/s, 1 Tbit/s, 1 GHz, 3 W, CMOS, BER, time division multiplexing
14	Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, standby-power-free CAM, complementary ferroelectric-capacitor logic, CFC logic circuit, nonvolatile storage, ferroelectric CMOS, content-addressable memory
14	Dalton M. Colombo, Gilson I. Wirth, Sergio Bampi	Trim range limited by noise in bandgap voltage references.	SBCCI	2007	DBLP DOI BibTeX RDF	bandgap, trim circuit, noise, CMOS, voltage reference
14	Hermann Eul	Complexity challenges towards 4th generation communication solutions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	4G, RF CMOS