Search results for "ISPD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
1	Patrick Groeneveld	Going with the flow: bridging the gap between theory and practice in physical design.	ISPD	2010	DBLP DOI BibTeX RDF	experimental evidence, design, algorithms, flow
1	Sachin S. Sapatnekar	Adding a new dimension to physical design.	ISPD	2010	DBLP DOI BibTeX RDF	3D circuits, physical design
1	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
1	Zongwu Tang	Efficient design practices for thermal management of a TSV based 3D IC system.	ISPD	2010	DBLP DOI BibTeX RDF	thermal gradient, placement, design rule, TSV
1	Gaurav Ajwani, Chris Chu, Wai-Kei Mak	FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction.	ISPD	2010	DBLP DOI BibTeX RDF	RSMT, spanning graph, routing, physical design
1	John Park	Thinking outside of the chip.	ISPD	2010	DBLP DOI BibTeX RDF	collaboration, co-design, package, ic, chip, pcb
1	Zigang Xiao, Evangeline F. Y. Young	Droplet-routing-aware module placement for cross-referencing biochips.	ISPD	2010	DBLP DOI BibTeX RDF	cross-referencing, dmfb, synthesis, placement, microfluidics, biochip
1	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Performance study of VeSFET-based, high-density regular circuits.	ISPD	2010	DBLP DOI BibTeX RDF	advanced technology., transistor layout, DFM, regular fabric
1	Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng	Physical synthesis of bus matrix for high bandwidth low power on-chip communications.	ISPD	2010	DBLP DOI BibTeX RDF	wire efficiency, bandwidth, power efficiency
1	Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang	Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.	ISPD	2010	DBLP DOI BibTeX RDF	routing, linear programming, network flow, electromigration
1	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
1	Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
1	Sani R. Nassif, Kevin J. Nowka	Physical design challenges beyond the 22nm node.	ISPD	2010	DBLP DOI BibTeX RDF	technology, scaling
1	Louis Scheffer	Physical design of biological systems.	ISPD	2010	DBLP DOI BibTeX RDF	biological design
1	Yongchan Ban, Savithri Sundareswaran, David Z. Pan	Total sensitivity based dfm optimization of standard library cells.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, VLSI, sensitivity, DFM, lithography
1	Serge Leef	Challenges and opportunities in optimization of automotive electronics.	ISPD	2010	DBLP DOI BibTeX RDF	automatic optimization, distributed systems, communication
1	Rob A. Rutenbar	Analog layout synthesis: what's missing?	ISPD	2010	DBLP DOI BibTeX RDF	synthesis, layout, analog
1	Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya	B-escape: a simultaneous escape routing algorithm based on boundary routing.	ISPD	2010	DBLP DOI BibTeX RDF	PCB routing, dense circuit boards, computer-aided design, escape routing
1	Mar Hershenson	Design platform for electrical and physical co-design of analog circuits.	ISPD	2010	DBLP DOI BibTeX RDF	design, analog, co-design
1	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
1	Charles J. Alpert, Zhuo Li 0001, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez	What makes a design difficult to route.	ISPD	2010	DBLP DOI BibTeX RDF	congestion driven physical synthesis, routing
1	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
1	Prashant Saxena, Yao-Wen Chang (eds.)	Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010	ISPD	2010	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
1	Neeraj Kaul	Design planning trends and challenges.	ISPD	2010	DBLP DOI BibTeX RDF	clock planning, feedthrough generation, macro placement, power domains, power planning, time budgeting, voltage areas, prototyping, partitioning, floorplanning, feasibility, hierarchical design, constraints generation, pin assignment
1	Robert C. Aitken	The challenges of correlating silicon and models in high variability CMOS processes.	ISPD	2009	DBLP DOI BibTeX RDF	design validation
1	Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
1	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
1	Eric Soenen	Physical design methodology for analog circuitsin a system-on-a-chip environment.	ISPD	2009	DBLP DOI BibTeX RDF	analog design automation
1	Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli	Graphene based transistors: physics, status and future perspectives.	ISPD	2009	DBLP DOI BibTeX RDF	cnfet, gnr-fet., graphene, carbon nanotubes
1	Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang	Redundant via insertion with wire bending.	ISPD	2009	DBLP DOI BibTeX RDF	redundant via, wire bending, integer linear program
1	Val Pevzner, Andrew A. Kennings, Andy Fox	Physical optimization for FPGAs using post-placement topology rewriting.	ISPD	2009	DBLP DOI BibTeX RDF	fpga, timing optimization, physical synthesis
1	Qunzeng Liu, Sachin S. Sapatnekar	Synthesizing a representative critical path for post-silicon delay prediction.	ISPD	2009	DBLP DOI BibTeX RDF	post-silicon optimization, representative critical path
1	Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li	Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization.	ISPD	2009	DBLP DOI BibTeX RDF	elmore delay model, obstacle-avoiding rectilinear steiner tree, performance-driven routing, worst negative slack, timing constraint
1	Hongbo Zhang 0001, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng	Wire shaping is practical.	ISPD	2009	DBLP DOI BibTeX RDF	manufacturing for design, wire tapering, interconnect, opc, power minimization
1	Kun Yuan, Jae-Seok Yang, David Z. Pan	Double patterning layout decomposition for simultaneous conflict and stitch minimization.	ISPD	2009	DBLP DOI BibTeX RDF	double patterning lithography, layout decomposition, integer linear programming
1	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
1	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Fast buffering for optimizing worst slack and resource consumption in repeater trees.	ISPD	2009	DBLP DOI BibTeX RDF	interconnect buffering, repeater tree, physical design, repeater insertion, timing closure
1	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Robi Dutta, Xianlong Hong	Diffusion-driven congestion reduction for substrate topological routing.	ISPD	2009	DBLP DOI BibTeX RDF	congestion reduction, ic package, substrate routing, diffusion, routability
1	Jifeng Chen, Jin Sun 0006, Janet Meiling Wang	Robust interconnect communication capacity algorithm by geometric programming.	ISPD	2009	DBLP DOI BibTeX RDF	communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid
1	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
1	Göran Jerke, Jens Lienig	Constraint-driven design: the next step towards analog design automation.	ISPD	2009	DBLP DOI BibTeX RDF	constraint-driven design, constraints, layout, physical design, analog design
1	Ruchir Puri	Will 22nm be our catch 22!: design and cad challenges.	ISPD	2009	DBLP DOI BibTeX RDF	22nm cmos, design productivity, vlsi cad challenges, vlsi design challenges, vlsi physical design, 3d ics, automated synthesis
1	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
1	Kai Wang, Aveek Sarkar, Norman Chang, Shen Lin	Early analysis for power distribution networks.	ISPD	2009	DBLP DOI BibTeX RDF	early analysis, power distribution network
1	Gi-Joon Nam, Prashant Saxena (eds.)	Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009	ISPD	2009	DBLP DOI BibTeX RDF
1	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
1	Yang-Shan Tong, Chia-Wei Lin, Sao-Jie Chen	An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization.	ISPD	2009	DBLP DOI BibTeX RDF	routing, opc, lithography, hotspot
1	Wojciech Maly	Vertical slit transistor based integrated circuits (VeSTICs) paradigm.	ISPD	2009	DBLP DOI BibTeX RDF	dual gate transistor, ic deign-manufacturing paradigm, vertical channel, vesfet, 3d integration, regular fabric, dfm
1	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Transistor-level layout of high-density regular circuits.	ISPD	2009	DBLP DOI BibTeX RDF	transistor layout, placement and routing, regular fabric, dfm
1	Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer	On improving optimization effectiveness in interconnect-driven physical synthesis.	ISPD	2009	DBLP DOI BibTeX RDF	routing, interconnect, physical synthesis, circuit optimization, vlsi
1	Zaichen Qian, Evangeline F. Y. Young	Multi-voltage floorplan design with optimal voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	multi-voltage assignment optimization branch-and-bound
1	Tsung-Hsien Lee, Ting-Chi Wang	Robust layer assignment for via optimization in multi-layer global routing.	ISPD	2009	DBLP DOI BibTeX RDF	optimization, computer-aided design, global routing, via, layer assignment
1	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A faster approximation scheme for timing driven minimum cost layer assignment.	ISPD	2009	DBLP DOI BibTeX RDF	dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment
1	Yifang Liu, Jiang Hu	A new algorithm for simultaneous gate sizing and threshold voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	threshold voltage assignment, gate sizing
1	Carl J. Anderson	One look into the future of CMOS chip design.	ISPD	2009	DBLP DOI BibTeX RDF	cmos design
1	Quang Dinh, Deming Chen, Martin D. F. Wong	A routing approach to reduce glitches in low power FPGAs.	ISPD	2009	DBLP DOI BibTeX RDF	glitch reduction, path balancing, fpgas, routing, low power
1	Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson	Accelerated design of analog, mixed-signal circuits in Titan.	ISPD	2009	DBLP DOI BibTeX RDF	analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits
1	Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.	ISPD	2009	DBLP DOI BibTeX RDF	multiple-supply voltage designs, physical design, floorplanning, vlsi
1	M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman	RF interconnects for communications on-chip.	ISPD	2008	DBLP DOI BibTeX RDF	RF-interconnect, network-on-chip, chip multiprocessors
1	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov	The coming of age of (academic) global routing.	ISPD	2008	DBLP DOI BibTeX RDF	optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength
1	Patrick McGuinness	Variations, margins, and statistics.	ISPD	2008	DBLP DOI BibTeX RDF	design margins, process variations, yield, SSTA
1	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
1	Chih-Hung Liu 0001, Yao-Hsin Chou, Shih-Yi Yuan, Sy-Yen Kuo	Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree.	ISPD	2008	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, steiner tree
1	Antun Domic	Design or manufacturing: which will be best for the future of the semiconductor roadmap?	ISPD	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
1	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
1	Tao Xu 0002, Krishnendu Chakrabarty	Automated design of digital microfluidic lab-on-chip under pin-count constraints.	ISPD	2008	DBLP DOI BibTeX RDF	array partition, cross-referencing, lab-on-chip, pin-count constraints, microfluidics
1	Herman Schmit, Amit Gupta, Radu Ciobanu	Placement challenges for structured ASICs.	ISPD	2008	DBLP DOI BibTeX RDF	field programmable gate arrays, placement, structured ASICs
1	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes	Abacus: fast legalization of standard cell circuits with minimal movement.	ISPD	2008	DBLP DOI BibTeX RDF	minimal movement, standard cell circuits, dynamic programming, legalization
1	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Stress aware layout optimization.	ISPD	2008	DBLP DOI BibTeX RDF
1	Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto	Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise.	ISPD	2008	DBLP DOI BibTeX RDF	principal component analysis, gaussianization, power supply noise, statistical timing analysis
1	Jieyi Long, Hai Zhou 0001, Seda Ogrenci Memik	An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.	ISPD	2008	DBLP DOI BibTeX RDF	minimum terminal spanning tree, spanning graph, routing, physical design, steiner tree
1	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Reap what you sow: spare cells for post-silicon metal fix.	ISPD	2008	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz	The ISPD global routing benchmark suite.	ISPD	2008	DBLP DOI BibTeX RDF	benchmarks, physical design, VLSI routing
1	Bruce Tseng, Hung-Ming Chen	Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.	ISPD	2008	DBLP DOI BibTeX RDF	voltage island architecture, low power, buffer insertion
1	Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao	Optimal post-routing redundant via insertion.	ISPD	2008	DBLP DOI BibTeX RDF	redundant via insertion, via density, integer linear program
1	Jason Cong, Guojie Luo	Highly efficient gradient computation for density-constrained analytical placement methods.	ISPD	2008	DBLP DOI BibTeX RDF	force-directed method, mixed-size placement
1	David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
1	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-density driven placement for cmp variation and routability.	ISPD	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, manufacturability
1	David Z. Pan, Gi-Joon Nam (eds.)	Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008	ISPD	2008	DBLP DOI BibTeX RDF
1	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing non-monotonic interconnect using functional simulation and logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF
1	Ed Grochowski, Murali Annavaram, Paul Reed	Implications of device timing variability on full chip timing.	ISPD	2008	DBLP DOI BibTeX RDF
1	Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng	Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.	ISPD	2008	DBLP DOI BibTeX RDF	crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing
1	Renshen Wang, Evangeline F. Y. Young, Yi Zhu 0002, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng	3-D floorplanning using labeled tree and dual sequences.	ISPD	2008	DBLP DOI BibTeX RDF	3-D packing, sequence, labeled tree
1	Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
1	Jason Cong, John Lee 0002, Lieven Vandenberghe	Robust gate sizing via mean excess delay minimization.	ISPD	2008	DBLP DOI BibTeX RDF	robust gate sizing, process variation, geometric programming, conditional value-at-risk
1	Minsik Cho, David Z. Pan	A high-performance droplet router for digital microfluidic biochips.	ISPD	2008	DBLP DOI BibTeX RDF	routing, synthesis, microfluidics, biochip
1	Phiroze N. Parakh, Shankar Krishnamoorthy	A robust approach to lithography friendly design implementation.	ISPD	2008	DBLP DOI BibTeX RDF
1	William Swartz	Issues in global routing.	ISPD	2008	DBLP DOI BibTeX RDF	constrained die, variable die, global routing
1	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
1	Yifang Liu, Jiang Hu, Weiping Shi	Multi-scenario buffer insertion in multi-core processor designs.	ISPD	2008	DBLP DOI BibTeX RDF	multi-core design, buffer insertion
1	Tamal Mukherjee, Anton J. Pfeiffer, Steinar Hauan	Physical design issues in biofluidic microchips.	ISPD	2008	DBLP DOI BibTeX RDF	micro total analysis system, microarrays, biochips, lab-on-a-chip, biomems
1	Fan Mo, Robert K. Brayton	Semi-detailed bus routing with variation reduction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, variation, bus
1	Azad Naeemi, James D. Meindl	Carbon nanotube interconnects.	ISPD	2007	DBLP DOI BibTeX RDF	quantum wires, crosstalk, inductance, repeaters, molecular electronics, system analysis and design, system optimization
1	Timothy Johnson, Umesh Nawathe	An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2).	ISPD	2007	DBLP DOI BibTeX RDF
1	Rupesh S. Shelar	An efficent clustering algorithm for low power clock tree synthesis.	ISPD	2007	DBLP DOI BibTeX RDF	clustering, low power, clock tree synthesis
1	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
1	Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis	Maze routing steiner trees with effective critical sink optimization.	ISPD	2007	DBLP DOI BibTeX RDF	timing driven synthesis, Steiner trees, maze routing

Publications at "ISPD"( http://dblp.L3S.de/Venues/ISPD )