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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6705 occurrences of 3042 keywords
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Results
Found 11076 publication records. Showing 11076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Xuan Zeng 0001, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou |
A constraint-based placement refinement method for CMOS analog cell layout. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Ophir Holder, Israel Ben-Shaul, Hovav Gazit |
System Support for Dynamic Layout of Distributed Applications. |
ICDCS |
1999 |
DBLP DOI BibTeX RDF |
Distributed Programming Models, Engineering Distributed Systems, Java, Mobile Objects, Distributed Components |
22 | Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee |
A Framework for Interprocedural Locality Optimization Using Both Loop and Data Layout Transformations. |
ICPP |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson |
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Ulrik Brandes, Dorothea Wagner |
Using Graph Layout to Visualize Train Interconnection Data. |
GD |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Ugur Dogrusöz, Konstantinos G. Kakoulis, Brendan Madden, Ioannis G. Tollis |
Edge Labeling in the Graph Layout Toolkit. |
GD |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Jaewon Kim, Sung-Mo Kang |
A timing-driven data path layout synthesis with integer programming. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
routing, integer programming, timing-driven placement, data path, bit-slice |
22 | Jack A. Feldman, Israel A. Wagner, Shmuel Wimer |
An efficient algorithm for some multirow layout problems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Uminder Singh, C. Y. Roger Chen |
From logic to symbolic layout for gate matrix. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
22 | Gerard A. Allan, Anthony J. Walton, Robert J. Holwill |
A yield improvement technique for IC layout using local design rules. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
22 | João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves |
A methodology for testability enhancement at layout level. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
physical design rules for testability, simulation, fault modeling, testability analysis |
22 | Yu Hen Hu, Sao-Jie Chen |
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu |
LiB: A Cell Layout Generator. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Charles J. Poirier |
Excellerator: custom CMOS leaf cell layout generator. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Hyunchul Shin, Chi-Yuan Lo |
An Efficient Two-Dimensional Layout Compaction Algorithm. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
22 | G. D. Adams, Carlo H. Séquin |
Template Style Considerations for Sea-of-Gates Layout Generation. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Wayne H. Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton |
Algorithms for optimizing, two-dimensional symbolic layout compaction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Wei Shu, Min-You Wu, S. M. Kang |
Improved net merging method for gate matrix layout. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Youn-Long Lin, Daniel D. Gajski |
LES: a layout expert system. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa |
Automatic Layout Procedures for Serial Routing Devices. |
DAC |
1988 |
DBLP BibTeX RDF |
|
22 | Xinghao Chen 0003, Michael L. Bushnell |
A Module Area Estimator for VLSI Layout. |
DAC |
1988 |
DBLP BibTeX RDF |
|
22 | David G. Boyer |
Symbolic Layout Compaction Review. |
DAC |
1988 |
DBLP BibTeX RDF |
|
22 | Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh |
A Dynamic and Efficient Representation of Building-Block Layout. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
22 | R. L. Maiasz, John P. Hayes |
Layout Optimization of CMOS Functional Cells. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Wen-Jeng Lue, Lawrence P. McNamee |
PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Jose M. Mata |
Design and Implementation for a Procedural VLSI Layout. |
FSTTCS |
1985 |
DBLP DOI BibTeX RDF |
|
22 | C. P. Hsu, B. N. Tien, K. Chow, R. A. Perry, J. Tang |
ALPS2: a standard cell layout system for double-layer metal technology. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Kung-Chao Chu, Y. Edmund Lien |
Technology tracking for VLSI layout design tools. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
22 | W. A. Dees, K. M. Parmar, A. Goyal, Raymond Y. Tsui, B. D. Rathi, Robert J. Smith 0001 |
A computer-aided VLSI layout system. |
AFIPS National Computer Conference |
1981 |
DBLP DOI BibTeX RDF |
|
21 | Andreas Girgensohn, Frank M. Shipman III, Thea Turner, Lynn Wilcox |
Flexible access to photo libraries via time, place, tags, and visual features. |
JCDL |
2010 |
DBLP DOI BibTeX RDF |
photo libraries, similarity criteria, tagged photos, visual similarity, geographic data, photo retrieval |
21 | Hector Ouilhet |
Google Sky Map: using your phone as an interface. |
Mobile HCI |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Yen-Hung Lin, Yih-Lang Li |
Double patterning lithography aware gridless detailed routing with innovative conflict graph. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
double patterning, gridless model, detailed routing |
21 | Yaniv Frishman, Ayellet Tal |
Uncluttering Graph Layouts Using Anisotropic Diffusion and Mass Transport. |
IEEE Trans. Vis. Comput. Graph. |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Tim Dwyer, Bongshin Lee, Danyel Fisher, Kori Inkpen Quinn, Petra Isenberg, George G. Robertson, Chris North 0001 |
A Comparison of User-Generated and Automatic Graph Layouts. |
IEEE Trans. Vis. Comput. Graph. |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Behzad Sajadi, Yan Huang 0003, Pablo Diaz-Gutierrez, Sung-Eui Yoon, M. Gopi 0001 |
A novel page-based data structure for interactive walkthroughs. |
SI3D |
2009 |
DBLP DOI BibTeX RDF |
walkthrough systems, spatial data structures, out-of-core algorithms, data layouts |
21 | Mukul S. Bansal, Wen-Chieh Chang 0002, Oliver Eulenstein, David Fernández-Baca |
Generalized Binary Tanglegrams: Algorithms and Applications. |
BICoB |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Jo Wood, Jason Dykes |
Spatially Ordered Treemaps. |
IEEE Trans. Vis. Comput. Graph. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tatsuhiko Kagehiro, Hiromichi Fujisawa |
Multiple Hypotheses Document Analysis. |
Machine Learning in Document Analysis and Recognition |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Marius Nita, Dan Grossman, Craig Chambers |
A theory of platform-dependent low-level software. |
POPL |
2008 |
DBLP DOI BibTeX RDF |
low-level software, portability, type safety, casts |
21 | Andrew B. Kahng |
How to get real mad. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability |
21 | Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu 0001, Alexander Zelikovsky |
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Abdoul Rjoub, M. Musameh, Odysseas G. Koufopavlou |
An optimal low-power/high performance DDP-based Cobra-H64 cipher. |
MobiMedia |
2007 |
DBLP DOI BibTeX RDF |
Cobra-H64, security, cryptography, encryption, decryption |
21 | Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim |
Placement and routing of RF embedded passive designs in LCP substrate. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Yokesh Kumar, Prosenjit Gupta |
Reducing EPL Alignment Errors for Large VLSI Layouts. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Brian Taylor, Larry T. Pileggi |
Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Joost van Beusekom, Daniel Keysers, Faisal Shafait, Thomas M. Breuel |
Example-Based Logical Labeling of Document Title Page Images. |
ICDAR |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Sumit Mehra, Peter J. Werkhoven, Marcel Worring |
Navigating on handheld displays: Dynamic versus static peephole navigation. |
ACM Trans. Comput. Hum. Interact. |
2006 |
DBLP DOI BibTeX RDF |
handheld displays, Human-computer interaction, navigation, visual perception |
21 | Timo Götzelmann, Knut Hartmann, Thomas Strothotte |
Agent-Based Annotation of Interactive 3D Visualizations. |
Smart Graphics |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Tae-Jung Lho, Dong Joong Kang, Am-suk Oh, Jang-Woo Kwon, Suk-Tae Bae, Kang-Hyuk Lee |
An Implementation of the Vectorizing-Based Automatic Nesting Software NST . |
ICCSA (2) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero |
Software Trace Cache. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch |
21 | Guido Reina, Sven Lange-Last, Klaus D. Engel, Thomas Ertl |
Guided Navigation in Task-Oriented 3D Graph Visualizations. |
TPCG |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Yu Chen 0005, Puneet Gupta 0001, Andrew B. Kahng |
Performance-impact limited area fill synthesis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method |
21 | Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001 |
Test structures for delay variability. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Martin R. Frerichs |
Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Sandro Bartolini, Cosimo Antonio Prete |
An Object Level Transformation Technique to Improve the Performance of Embedded Applications. |
SCAM |
2001 |
DBLP DOI BibTeX RDF |
procedure reordering, optimization, cache, program transformation, conflict misses |
21 | Thorsten Adler, Erich Barke |
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Panagiotis K. Linos, Esther T. Ososanya, Vijay Karunakaran |
Improving the Visibility of Graphical Program Displays: An Experimental Study. |
IWPC |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran |
On the intrinsic Rent parameter and spectra-based partitioning methodologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Hans-Rudolf Heeb, Wolfgang Fichtner |
A module generator based on the PQ-tree algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Pei-Yung Hsiao, Wu-Shiung Feng |
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Bernd Becker 0001, Hans-Georg Osthof |
Layouts with Wires of Balanced Length. |
STACS |
1985 |
DBLP DOI BibTeX RDF |
|
21 | Fillia Makedon, Christos H. Papadimitriou, Ivan Hal Sudborough |
Topological Bandwidth. |
CAAP |
1983 |
DBLP DOI BibTeX RDF |
|
20 | Chaomin Luo, Miguel F. Anjos, Anthony Vannelli |
A nonlinear optimization methodology for VLSI fixed-outline floorplanning. |
J. Comb. Optim. |
2008 |
DBLP DOI BibTeX RDF |
Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming |
20 | Clayton Brian Atkins |
Blocked recursive image composition. |
ACM Multimedia |
2008 |
DBLP DOI BibTeX RDF |
album, photo layout, composition, collage, automatic layout |
20 | Pat Washburn |
Extreme makeover: lab edition. |
SIGUCCS |
2006 |
DBLP DOI BibTeX RDF |
lab design, lab layout, design, projection, layout, lab |
20 | Massoud Pedram |
Power minimization in IC design: principles and applications. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product |
20 | John A. Chandy, Prithviraj Banerjee |
Parallel simulated annealing strategies for VLSI cell placement. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement |
20 | Sudip K. Nag, Rob A. Rutenbar |
Performance-driven simultaneous place and route for island-style FPGAs. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout |
20 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
20 | Anthony D. Johnson |
On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
locally optimal breaking strategy, nondisjoint cyclic vertical constraints, VLSI channel routing, vertical constraint graph, nondisjoint circuits, common vertex, common path, channel router heuristics, automatic routers, interactive routers, VLSI, graph theory, parallel architectures, network routing, circuit layout CAD, integrated circuit layout |
20 | Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten |
Performance driven standard-cell placement using the genetic algorithm. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement |
20 | Ines Peters, Paul Molitor |
Priority driven channel pin assignment. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
polynomial time improvement, linear channel pin assignment, LCPA algorithms, minimum channel density, vertical constraints, priority driven channel pin assignment, channel height, computational complexity, VLSI, VLSI, network routing, circuit layout CAD, running time, integrated circuit layout, priority schedule, channel routing |
20 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
20 | Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani |
Optimal algorithms for planar over-the-cell routing in the presence of obstacles. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout |
20 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
Combined optimization of area and testability during state assignment of PLA-based FSM's. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization |
20 | Manjit Borah, Mary Jane Irwin, Robert Michael Owens |
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing |
20 | Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli |
A new switching-level approach to multiple-output functions synthesis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit |
20 | Keumog Ahn, Sartaj Sahni |
NP-Hard Module Rotation Problems. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
NP-hard module rotation problems, circuit modules, performance, computational complexity, circuit layout CAD, circuit layout CAD, routability |
20 | Shantanu Dutt, John P. Hayes |
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
node-covering design, covering graphs, VLSI layout area minimization, distributed reconfiguration, software recovery, local spares, parallel algorithms, computational complexity, VLSI, graph theory, fault tolerant computing, multiprocessing systems, circuit layout CAD, incremental design, state information, fault-tolerant multiprocessors |
20 | Chung-Kuan Cheng, So-Zen Yao, T. C. Hu |
The Orientation of Modules Based on Graph Decomposition. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
layout stage, total net length, printed circuits, computational complexity, VLSI, VLSI, graph theory, NP-complete, modules, orientation, circuit layout CAD, routability, minimum cut, graph decomposition, printed circuit board, graph problem |
20 | Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa |
Crossing Minimization in Linear Embeddings of Graphs. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
crossing minimisation, linear embeddings of graphs, circuit layout problems, computational complexity, graph theory, NP-hard, circuit layout CAD, minimisation |
20 | Binay Sugla, David A. Carlson |
Extreme Area-Time Tradeoffs in VLSI. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder |
20 | Hee Yong Youn, Adit D. Singh |
On Implementing Large Binary Tree Architectures in VLSI and WSI. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
large binary tree architectures, maximum edge length, H-tree layouts, VLSI, VLSI, layout, trees (mathematics), circuit layout CAD, processing elements, propagation delay, fault-tolerant designs, WSI, two-dimensional array |
20 | Ruth Kuchem, Dorothea Wagner, Frank Wagner 0001 |
Area-Optimal Three-Layer Channel Routing |
FOCS |
1989 |
DBLP DOI BibTeX RDF |
area optimal routing algorithm, three-layer channel routing, knock-knee mode, three conducting layers, three-layer wirable layout, time complexity, vias, layer assignment, layout algorithms |
19 | Pengju Shang, Jun Wang 0001, Huijun Zhu, Peng Gu |
A New Placement-Ideal Layout for Multiway Replication Storage System. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
Multiway replication, parallel I/O, data layout |
19 | Radha Jagadeesan, Corin Pitcher, Julian Rathke, James Riely |
Local Memory via Layout Randomization. |
CSF |
2011 |
DBLP DOI BibTeX RDF |
memory layout randomization, deterministic allocation, probability, control, full abstraction, higher-order |
19 | Xi-Wei Lin, Victor Moroz |
Layout Proximity Effects and Modeling Alternatives for IC Designs. |
IEEE Des. Test Comput. |
2010 |
DBLP DOI BibTeX RDF |
mobility, CMOS, layout, variability, extraction, proximity, design and test, stress, lithography, threshold voltage, compact model |
19 | Liankui Qiu, Panlong He, Lei Luo |
The Strategy of Advancing Mobile Web Application's Layout and Drawing. |
CIT |
2010 |
DBLP DOI BibTeX RDF |
Mobile web application, layout and drawing, refresh interface, web technology |
19 | Rob A. Rutenbar |
Analog layout synthesis: what's missing? |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
synthesis, layout, analog |
19 | Jeehong Yang, Serap A. Savari |
A Lossless Circuit Layout Image Compression Algorithm for Maskless Lithography Systems. |
DCC |
2010 |
DBLP DOI BibTeX RDF |
Circuit Layout Image, Maskless Lithography System, C4, Block C4, Lossless image compression |
19 | Jiao-fang Shi, Jian Wang |
On Chip Temperature Sensors' Layout for Future Thermal Management. |
MVHI |
2010 |
DBLP DOI BibTeX RDF |
CPU chip, management, sensor, layout, temperature |
19 | Yong Chen 0001, Xian-He Sun, Rajeev Thakur, Huaiming Song, Hui Jin 0001 |
Improving Parallel I/O Performance with Data Layout Awareness. |
CLUSTER |
2010 |
DBLP DOI BibTeX RDF |
parallel I/O middleware, independent I/O, data access optimization, parallel I/O, parallel file systems, data layout, collective I/O, I/O performance |
19 | Les R. Foulds, Horst W. Hamacher |
Facilities Layout Problems. |
Encyclopedia of Optimization |
2009 |
DBLP DOI BibTeX RDF |
Multifacilities location, REL chart scores, Improved procedure, Construction procedures, Planar subgraph, Multicriteria objective function, Transportation cost, Layout manager, Genetic algorithms, Graph theory, Heuristics, Simulated annealing, Graph, Decision support system, Integer programming, Location, NP-hard, Branch and bound, Lagrangian relaxation, Bounds, Quadratic assignment problem, Adjacency graph |
19 | João Batista S. de Oliveira |
Two algorithms for automatic page layout and possible applications. |
Multim. Tools Appl. |
2009 |
DBLP DOI BibTeX RDF |
Automatic page layout, Packing, Placement algorithms |
19 | José-Francisco Herbert-Acero, Jorge-Rodolfo Franco-Acevedo, Manuel Valenzuela-Rendón, Oliver Probst-Oleszewski |
Linear Wind Farm Layout Optimization through Computational Intelligence. |
MICAI |
2009 |
DBLP DOI BibTeX RDF |
Sitting, Wind Farm Layout, Far Wake Effects, Turbulence and Roughness Length, Genetic Algorithms, Optimization, Simulated Annealing, Wind Turbines |
19 | Guijian Huang, Xuemei Li, Xiaoyu Wu, Jibin Li 0001 |
Optimized Design of Cavity Layout and Feed System of Multi-cavity Injection Mould. |
JCAI |
2009 |
DBLP DOI BibTeX RDF |
injection mould, cavity layout, feed system, optimized design |
19 | Ting Yang, Dinghua Zhang, Bing Chen, Shan Li |
Research on Plant Layout and Production Line Running Simulation in Digital Factory Environment. |
PACIIA (2) |
2008 |
DBLP DOI BibTeX RDF |
Digital factory, Manufacturing resource library, Plant layout, Production running simulation |
19 | Yuan-Qing He, Shi-Xin Sun |
A Data Layout and Access Control Strategies of the Video Storage Server Based Disk Array. |
IIH-MSP |
2008 |
DBLP DOI BibTeX RDF |
Multi-segment, Vdeo storage server, Architecture, MPEG, Disk array, Data layout |
19 | Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton |
Precise failure localization using automated layout analysis of diagnosis candidates. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
defect localization, physical failure analysis, diagnosis, layout analysis |
19 | João Batista S. de Oliveira |
Two algorithms for automatic document page layout. |
ACM Symposium on Document Engineering |
2008 |
DBLP DOI BibTeX RDF |
automatic page layout, packing, placement algorithms |
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