Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Hai Zhou 0001	Timing analysis with crosstalk is a fixpoint on a complete lattice.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
23	Iain Bate, Peter Nightingale, Anton Cervin	Establishing Timing Requirements and Control Attributes for Control Loops in Real-Time Systems.	ECRTS	2003	DBLP DOI BibTeX RDF
23	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical Timing Analysis Using Bounds.	DATE	2003	DBLP DOI BibTeX RDF
23	Chi-Sheng Shih 0001, Jane W.-S. Liu	Acquiring and Incorporating State-Dependent Timing Requirements.	RE	2003	DBLP DOI BibTeX RDF
23	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent Waveform Propagation for Static Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
23	Wonjoon Choi, Kia Bazargan	Incremental Placement for Timing Optimization.	ICCAD	2003	DBLP DOI BibTeX RDF
23	Kiran Seth, Aravindh Anantaraman, Frank Mueller 0001, Eric Rotenberg	FAST: Frequency-Aware Static Timing Analysis.	RTSS	2003	DBLP DOI BibTeX RDF
23	Doron Drusinsky, Man-tak Shing	Verification of Timing Properties in Rapid System Prototyping.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
23	PariVallal Kannan, Dinesh Bhatia	Interconnect Estimation for FPGAs under Timing Driven Domains.	ICCD	2003	DBLP DOI BibTeX RDF
23	Wei-Ping Zhu 0001, Yupeng Yan, M. Omair Ahmad, M. N. S. Swamy	A feedforward timing recovery scheme using two samples per symbol: algorithm, performance and implementation issues.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
23	Jiang Hu, Sachin S. Sapatnekar	A timing-constrained simultaneous global routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
23	Colin J. Fidge	Timing Analysis of Assembler Code Control-Flow Paths.	FME	2002	DBLP DOI BibTeX RDF
23	Andrew B. Kahng, Stefanus Mantik, Igor L. Markov	Min-max placement for large-scale timing optimization.	ISPD	2002	DBLP DOI BibTeX RDF
23	Abhik Roychoudhury, Xianfeng Li, Tulika Mitra	Timing Analysis of Embedded Software for Speculative Processors.	ISSS	2002	DBLP DOI BibTeX RDF	worst case execution time, branch prediction
23	Pau Martí, Josep M. Fuertes, Gerhard Fohler, Krithi Ramamritham	Improving Quality-of-Control Using Flexible Timing Constraints: Metric and Scheduling Issues.	RTSS	2002	DBLP DOI BibTeX RDF
23	Erik Yu-Shing Hu, Guillem Bernat, Andy J. Wellings	A Static Timing Analysis Environment Using Java Architecture for Safety Critical Real-Time Systems.	WORDS	2002	DBLP DOI BibTeX RDF	Portable WCET Analysis, Java, Hard Real-Time Systems, Real-Time Java, Worst-Case Execution Time Analysis
23	Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto	CMOS Circuit Technology for Precise GHz Timing Generator.	ITC	2002	DBLP DOI BibTeX RDF
23	Xiaobo Sharon Hu, Tao Zhou, Edwin Hsing-Mean Sha	Estimating probabilistic timing performance for real-time embedded systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
23	Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng	Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
23	Sudha Krishnamurthy, William H. Sanders, Michel Cukier	A Dynamic Replica Selection Algorithm for Tolerating Timing Faults.	DSN	2001	DBLP DOI BibTeX RDF
23	Youngtae Kim, Taewhan Kim	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.	ASP-DAC	2001	DBLP DOI BibTeX RDF
23	Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu	The hierarchical timing pair model.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
23	Yao-Wen Chang, Kai Zhu 0001, D. F. Wong 0001	Timing-driven routing for symmetrical array-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field-programmable gate array, synthesis, layout, computer-aided design of VLSI
23	Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi	Model Checking Synchronous Timing Diagrams.	FMCAD	2000	DBLP DOI BibTeX RDF
23	David T. Blaauw, Rajendran Panda, Abhijit Das	Removing user specified false paths from timing graphs.	DAC	2000	DBLP DOI BibTeX RDF
23	Supratik Chakraborty, Kenneth Y. Yun, David L. Dill	Timing analysis of asynchronous systems using time separation of events.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
23	Shihliang Ou, Massoud Pedram	Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming.	ASP-DAC	1999	DBLP DOI BibTeX RDF
23	Navin Kashyap, David L. Neuhoff	Codes for Data Synchronization with Timing.	Data Compression Conference	1999	DBLP DOI BibTeX RDF
23	Nina Amla, E. Allen Emerson, Kedar S. Namjoshi	Efficient Decompositional Model Checking for Regular Timing Diagrams.	CHARME	1999	DBLP DOI BibTeX RDF
23	Jing Chen, Alan Burns 0001	Loop-Free Asynchronous Data Sharing in Multiprocessor Real-Time Systems Based on Timing Properties.	RTCSA	1999	DBLP DOI BibTeX RDF	Data sharing mechanism, Asynchronous data sharing, Wait-free, Lock-free, Loop-free
23	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens	Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.	ICCAD	1999	DBLP DOI BibTeX RDF
23	Christopher A. Healy, David B. Whalley	Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints.	IEEE Real Time Technology and Applications Symposium	1999	DBLP DOI BibTeX RDF
23	Abdelhalim El-Aboudi, El Mostapha Aboulhamid	An algorithm for the verification of timing diagrams realizability.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
23	Iain Bate, Alan Burns 0001	Investigation of the pessimism in distributed systems timing analysis.	ECRTS	1998	DBLP DOI BibTeX RDF
23	Sung-Soo Lim, Jihong Kim 0001, Sang Lyul Min	A Worst Case Timing Analysis Technique for Optimized Programs.	RTCSA	1998	DBLP DOI BibTeX RDF	real-time systems, compiler optimization, worst case execution time
23	Eduard Cerny, Fen Jin	Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming.	EUROMICRO	1998	DBLP DOI BibTeX RDF
23	Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen	Timing and Crosstalk Driven Area Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
23	R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi	Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
23	Chen-Liang Fang, Wen-Ben Jone	Timing optimization by gate resizing and critical path identification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
23	Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang	Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu	Timed Boolean calculus and its applications in timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Dave Filo, David C. Ku, Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Interface optimization for concurrent systems under timing constraints.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
23	John A. Nestor, Ganesh Krishnamoorthy	SALSA: a new approach to scheduling with timing constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	H. Warmers, D. Sass, Ernst-Helmut Horneber	Switch-level timing models in the MOS simulator BRASIL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
23	Wilm E. Donath, Reini J. Norman, Bhuwan K. Agrawal, Stephen E. Bello, Sang-Yong Han, Jerome M. Kurtzberg, Paul Lowy, Roger I. McMillan	Timing Driven Placement Using Complete Path Delays.	DAC	1990	DBLP DOI BibTeX RDF
23	Kaushik Roy 0001, Jacob A. Abraham	A Novel Approach to Accurate Timing Verification Using RTL Descriptions.	DAC	1989	DBLP DOI BibTeX RDF
23	Bogong Su, Jian Wang 0046, Jinshi Xia	Global microcode compaction under timing constraints.	MICRO	1988	DBLP BibTeX RDF
23	George Varghese, Anthony Lauck	Hashed and Hierarchical Timing Wheels: Data Structures for the Efficient Implementation of a Timer Facility.	SOSP	1987	DBLP DOI BibTeX RDF
23	Seung Ho Hwang, Young Hwan Kim, A. Richard Newton	An accuration delay modeling technique for switch-level timing verification.	DAC	1986	DBLP DOI BibTeX RDF
22	Tomohito Takubo, Yoshinori Imada, Kenichi Ohara, Yasushi Mae, Tatsuo Arai	Rough terrain walking for bipedal robot by using ZMP criteria map.	ICRA	2009	DBLP DOI BibTeX RDF
22	Khaled R. Heloue, Farid N. Najm	Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
22	Pouria Bastani, Li-C. Wang, Magdy S. Abadir	Linking Statistical Learning to Diagnosis.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
22	Joseph Keshet, Shai Shalev-Shwartz, Yoram Singer, Dan Chazan	A Large Margin Algorithm for Speech-to-Phoneme and Music-to-Score Alignment.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
22	Jan Gustafsson, Andreas Ermedahl	Experiences from Applying WCET Analysis in Industrial Settings.	ISORC	2007	DBLP DOI BibTeX RDF
22	Eugene Hsu, Marco da Silva, Jovan Popovic	Guided time warping for motion editing.	Symposium on Computer Animation	2007	DBLP DOI BibTeX RDF
22	Navin Kashyap, David L. Neuhoff	Periodic prefix-synchronized codes: A generating function approach.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
22	Jinfeng Huang, Jeroen Voeten, Henk Corporaal	Correctness-preserving synthesis for real-time control software.	QSIC	2006	DBLP DOI BibTeX RDF
22	Haoxing Ren, David Zhigang Pan, David S. Kung 0001	Sensitivity guided net weighting for placement-driven synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Skew-programmable clock design for FPGA and skew-aware placement.	FPGA	2005	DBLP DOI BibTeX RDF	clock architecture, skew optimization, placement
22	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	False Path and Clock Scheduling Based Yield-Aware Gate Sizing.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	Cristina P. Santos 0001	Generating timed Trajectories for an Autonomous Vehicle: a Non-linear Dynamical Systems Approach.	ICRA	2004	DBLP DOI BibTeX RDF
22	Andrew B. Kahng, Bao Liu 0001	Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.	ISVLSI	2003	DBLP DOI BibTeX RDF
22	Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller 0001	Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.	ISCA	2003	DBLP DOI BibTeX RDF
22	Wen-Tsong Shiue	Low Power Memory Design.	ASAP	2002	DBLP DOI BibTeX RDF
22	Karl-Heinz Zimmermann	Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
22	Mukund Sivaraman, Shail Aditya	Cycle-time aware architecture synthesis of custom hardware accelerators.	CASES	2002	DBLP DOI BibTeX RDF	embedded hardware architecture synthesis, operator chaining, target clock period, timing during scheduling, high-level synthesis, timing analysis, delay analysis, clock frequency
22	Jan Lindström, Kimmo E. E. Raatikainen	Using importance of transactions and optimistic concurrency control in firm real-time databases.	RTCSA	2000	DBLP DOI BibTeX RDF	optimistic concurrency control protocol, transaction importance, hard real-time databases, database consistency requirements, heterogeneous transactions, OCC-PDATI, serialization order dynamic adjustment, prototype database system, performance, real-time systems, concurrency control, timing, database management systems, transaction processing, timing constraints, conflict resolution, access protocols
22	Iain Bate, Guillem Bernat, G. Murphy, Peter P. Puschner	Low-level analysis of a portable Java byte code WCET analysis framework.	RTCSA	2000	DBLP DOI BibTeX RDF	low-level analysis, portable Java byte code, machine-independent program flow analysis, machine-dependent timing analysis, worst-case execution frequencies, platform-dependent information, processor pipeline, platform-independent approach, Java, timing, software performance evaluation, pipeline processing, software portability, program diagnostics, worst-case execution time analysis, program constructs
22	Yutaka Ishibashi, Shuji Tasaka, Hiromasa Miyamoto	Joint Synchronization between Live and Stored Media in Multicast Communications.	LCN	2000	DBLP DOI BibTeX RDF	joint synchronization, live media, stored media, networked multimedia applications, stored video stream, live voice streams, buffering time, retransmission control, group synchronization control, output timing, timing, distance learning, distance learning, synchronisation, multimedia communication, multicast communication, multicast communications, visual communication, voice communication, multicast group, live video streams
22	K. H. Kim, Cuong Nguyen, Chan-Mo Park	Real-Time Simulation Techniques Based on the RTO.k Object Modeling.	COMPSAC	1996	DBLP DOI BibTeX RDF	RTO.k object modeling, real-time simulation techniques, simulation objects, real-time embedded computer systems, real-time systems, adaptability, parallel processing, parallel processing, virtual machines, timing, object-oriented methods, expandability, modifiability, timing behavior, object structure, application environments
22	Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham	A robotic assembly application on the Spring real-time system.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools
22	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	Boolean process-an analytical approach to circuit representation (II).	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	waveform analysis, circuit representation, logical behavior, waveform functions, mathematical tools, waveform polynomials, input transitions, VLSI, Boolean functions, timing, design for testability, logic design, logical design, polynomials, integrated circuit design, VLSI circuits, performance enhancement, timing behavior, Boolean process, circuit delay
22	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
22	Martin Adelantado, Frédéric Boniol, D. Pinault	A simulation environment for designing distributed reactive/deliberative time-constrained applications.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	distributed reactive/deliberative time-constrained applications design, deliberative systems, terminal state, logical time notion, man-machine interface handlers, time critical applications, Sun4 IPX workstation, X-Window graphical interface, French Ministry of Defense, simulator, real-time systems, graphical user interfaces, distributed processing, requirements, programming, programming environments, timing, computer games, program compilers, digital simulation, reactive systems, timing constraints, distributed real-time systems, simulation environment, application generators, reactive programming, Unix operating system, initial state
22	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
22	Claudio Truzzi, Eric Beyne, Edwin Ringoot, J. Peeters	Signal propagation in high-speed MCM circuits.	ICCD	1995	DBLP DOI BibTeX RDF	thin film circuits, signal propagation, high-speed MCM circuits, thin-film multichip module substrate, timing analyses, lossy interconnection lines, timing, circuit analysis computing, circuit simulations, CMOS integrated circuits, CMOS integrated circuits, multichip modules, receivers, drivers, microsystems, substrates
22	Ashish Mehra, Jennifer Rexford, Hock-Siong Ang, Farnam Jahanian	Design and evaluation of a window-consistent replication service.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	back-up procedures, window-consistent primary-backup replication service, data replication protocols, bounded overhead, repository availability, consistency relaxation, controlled inconsistency, update transmission scheduling, client applications, failed primary, client loads, temporal inconsistency bounds, scheduling, fault tolerance, real-time systems, data integrity, distributed databases, timing, redundancy, redundancy, database theory, timing constraints, software fault tolerance, real-time applications, replicated databases, service guarantees, dependability constraints
22	Arkady Kanevsky, Peter C. Krupp, Paul J. Wallace	Paradigm for building robust real-time distributed mission-critical systems.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	search radar, military systems, radar tracking, robust real-time distributed mission-critical systems building, long life-cycle defense system, stringent safety requirements, stringent timing requirements, stringent dependability requirements, multiple target tracking, surveillance radar system, system upgrade support, system hardware, baseline performance, SEI/CMU Simplex Architecture, prototypical industrial feedback control application, integrated standard technologies, real-time systems, reliability, fault tolerant computing, distributed processing, timing, software fault tolerance, target tracking, safety-critical software, system software, military computing, application software, computing paradigm
22	Clifford W. Mercer, Ragunathan Rajkumar	An interactive interface and RT-Mach support for monitoring and controlling resource management.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	RT-Mach, Real-Time Mach, resource management monitoring, resource management control, timing characteristics, a priori resource allocation decisions, changing user needs, operating system resource reserves, resource reservation abstraction, processor capacity reserves, rmon, processor usage display, processor reservation, reservation change requests, policy decisions, real-time systems, user interfaces, resource allocation, timing, multimedia systems, dynamic systems, interactive systems, operating systems (computers), multimedia computing, system monitoring, quality of service manager, interactive interface
22	Yoshitaka Shibata, Naoya Seta, Shogo Shimizu	Media synchronization protocols for packet audio-video system on multimedia information networks.	HICSS (2)	1995	DBLP DOI BibTeX RDF	audio-visual systems, media synchronization protocols, packet audio-video system, multimedia information networks, distributed multimedia information services, semantically synchronized multimedia objects, distributed workstation environment, data output timing, packet stream regulation, audio/video transmission system architecture, strict synchronization, relaxed synchronization, silence-detected synchronization, operating system environments, interprocess communication functions, tasks/threads, synchronization accuracy evaluation, performance evaluation, performance evaluation, timing, UNIX, packet switching, synchronisation, multimedia communication, rate control, network operating systems, access protocols, information networks, continuous media, Mach, load conditions
22	Angela Krstic, Kwang-Ting Cheng	Generation of high quality tests for functional sensitizable paths.	VTS	1995	DBLP DOI BibTeX RDF	high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information
22	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
22	John W. Daly, Andrew Brooks, James Miller 0001, Marc Roper, Murray Wood	The effect of inheritance on the maintainability of object-oriented software: an empirical study.	ICSM	1995	DBLP DOI BibTeX RDF	object-oriented software modification, inheritance depth, timing data, inductive analysis, data structures, object-oriented programming, empirical study, software maintenance, timing, inheritance, inheritance, maintainability, object-oriented software
22	Kevin Lano, Stephen J. Goldsack	Discrete event process controller synthesis using VDM++.	ICECCS	1995	DBLP DOI BibTeX RDF	ignition, control system synthesis, heat systems, discrete event process controller synthesis, VDM/sup ++/, controller specification, gas burner system, systematic method, declarative requirement statements, abstract VDM/sup ++/ specifications, concrete VDM/sup ++/ specifications, formalised requirements, refinement process, real-time systems, formal specification, temporal logic, timing, specification languages, timing analysis, object-oriented languages, process control, parallel languages, discrete event systems, programmable controllers, controller design, Vienna development method, control system CAD, Ada95, real-time temporal logic, combustion
22	William S. Hiles, David T. Marlow	Approximation of FDDI minimum reconfiguration time.	LCN	1995	DBLP DOI BibTeX RDF	military communication, FDDI minimum reconfiguration time approximation, military platforms, reconfiguration timing, FDDI product testing, timing, data transfer, FDDI, military computing, LAN interconnection, mission critical systems, interconnection topologies
22	Farnam Jahanian, Aloysius K. Mok	Modechart: A Specification Language for Real-Time Systems.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	Modechart, absolute timing, real-time clock, RTL formulas, RTL assertions, graphical implementation, SARTOR, real-time systems, real-time systems, semantics, specification languages, specification language, rapid prototyping, timing constraints, abstraction levels, logic programming languages, hierarchical organization, real-time logic
21	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
21	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
21	Joshua Wall, Jamil Y. Khan	Dynamic protocol timing adaptation for improved efficiency in IEEE 802.11 wireless LANs.	IWCMC	2009	DBLP DOI BibTeX RDF	MAC efficiency, dynamic protocol timing, 802.11, CSMA/CA
21	Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama	A Gaussian mixture model for statistical timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	slew distribution, variability, Gaussian mixture model, statistical timing analysis, delay distribution
21	Zhonglei Wang, Andreas Herkersdorf	An efficient approach for system-level timing simulation of compiler-optimized embedded software.	DAC	2009	DBLP DOI BibTeX RDF	iSciSim, software timing simulation, system level design
21	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
21	Sachin S. Talathi, Dong-Uk Hwang, William L. Ditto	Spike timing dependent plasticity promotes synchrony of inhibitory networks in the presence of heterogeneity.	J. Comput. Neurosci.	2008	DBLP DOI BibTeX RDF	Inhibitory synapses, Networks, Synchronization, Heterogeneity, Spike timing dependent plasticity
21	Yue Yu 0002, Shangping Ren, Ophir Frieder	Interval-Based Timing Constraints Their Satisfactions and Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	interval based timing constraints, satisfaction probability, event occurrence, normal distribution, exponential distribution
21	Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang	A noniterative equivalent waveform model for timing analysis in presence of crosstalk.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	equivalent waveform, delay, noise, timing analysis, Deep sub micron
21	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
21	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
21	Lin Xie, Azadeh Davoodi	Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation.	ISQED	2008	DBLP DOI BibTeX RDF	Skew-Normal, process variation, Gaussian, statistical static timing analysis
21	Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey	Inconsistent Fail due to Limited Tester Timing Accuracy.	VTS	2008	DBLP DOI BibTeX RDF	inconsistent fail, tester timing accuracy, tester EPA, delay test, inconsistency
21	Qingqi Dou, Jacob A. Abraham	Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.	VTS	2008	DBLP DOI BibTeX RDF	Time-Interleaved ADC, Timing Mismatch, Mixed-signal testing, Low-cost test, High speed testing