Search results for "Arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Yuri I. Abramovich, Douglas A. Gray 0001, Alexei Y. Gorokhov, Nicholas K. Spencer	Positive-definite Toeplitz completion in DOA estimation for nonuniform linear antenna arrays. I. Fully augmentable arrays.	IEEE Trans. Signal Process.	1998	DBLP DOI BibTeX RDF
16	John R. Koza, Forrest H. Bennett III, Jeffrey L. Hutchings, Stephen L. Bade, Martin A. Keane, David Andre	Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic Programming.	FPGA	1998	DBLP DOI BibTeX RDF
16	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic	Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.	FPGA	1997	DBLP DOI BibTeX RDF
16	Francis Maurin	Incomplete orthogonal arrays and idempotent orthogonal arrays.	Graphs Comb.	1996	DBLP DOI BibTeX RDF
16	Vi Cuong Chan, David M. Lewis	Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays.	FPGA	1996	DBLP DOI BibTeX RDF
16	Chris Dick	Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays.	FPGA	1996	DBLP DOI BibTeX RDF
16	Karl-Heinz Zimmermann, Wolfgang Achtziger	Synthesizing Regular Arrays from Single Affine Recurrences via Quadratic and Branching Parametric Linear Programming.	Parcella	1996	DBLP BibTeX RDF
16	Juri Kanevski, Oleg Maslennikov, Roman Wyrzykowski	Algorithm-Based Fault Tolerant Solution of Linear Systems on Processor Arrays.	Parcella	1996	DBLP BibTeX RDF
16	Alf-Christian Achilles, Martin Kutrib, Thomas Worsch	On Relations between Arrays of Processing Elements of Different Dimensionality.	Parcella	1996	DBLP BibTeX RDF
16	Vassil N. Alexandrov, Graham M. Megson	Solving System of Linear Algebraic Equations by Monte Carlo Method on Regular Arrays.	Parcella	1996	DBLP BibTeX RDF
16	Peter De Dobbelaere, Frank Vermaerke, Gerrit Vermeire, Piet Demeester, Peter Van Daele, Gustaaf R. Möhlmann, Jean-Luc Heidemann, Winfried H. G. Horsthuis	Integration Technology for Light Source Arrays with Polymetric Optical Waveguide Arrays.	EUROSIM	1994	DBLP BibTeX RDF
16	Octav Brudaru, Graham M. Megson	Systolic Arrays for Accelerating Iteration Processes.	Parcella	1994	DBLP BibTeX RDF
16	A. Schubert, Renate Merker, H. Schreiber	Systematic Generation of a Variety of Processor Arrays.	Parcella	1994	DBLP BibTeX RDF
16	Philippe Clauss	An Efficient Allocation Strategy for Mapping Affine Recurrences into Space and Time Optimal Regular Processor Arrays.	Parcella	1994	DBLP BibTeX RDF
16	Patrice Quinton	Systolic Arrays: Why and How?	Parcella	1994	DBLP BibTeX RDF
16	Vassil Aleksandrov, Graham M. Megson, Stefka Fidanova	Mapping Knapsack Type Problems on 2D Regular Arrays: Two Case Studies.	Parcella	1994	DBLP BibTeX RDF
16	Jouni Isoaho, Arto Nummela, Hannu Tenhunen	Technologies and Utilization fo Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
16	Hartmut Surmann, Ansgar Ungering, Karl Goser	Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
16	Alberto L. Sangiovanni-Vincentelli	Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design.	FPL	1992	DBLP DOI BibTeX RDF
16	Hussein M. Alnuweiri, Viktor K. Prasanna	Optimal Geometric Algorithms for Digitized Images on Fixed-Size Linear Arrays and Scan-Line Arrays.	Distributed Comput.	1991	DBLP DOI BibTeX RDF
16	Chung J. Kuo, Harriett B. Rigas	2-D quasi m -arrays and Gold code arrays.	IEEE Trans. Inf. Theory	1991	DBLP DOI BibTeX RDF
16	Oscar H. Ibarra, Tao Jiang 0001	Optimal Simulation of Tree Arrays by Linear Arrays.	Inf. Process. Lett.	1989	DBLP DOI BibTeX RDF
16	Hussein M. Alnuweiri, V. K. Prasanna Kumar	Optimal geometric algorithms on fixed-size linear arrays and scan line arrays.	CVPR	1988	DBLP DOI BibTeX RDF
16	Viktor K. Prasanna, Yu-Chen Tsai	Mapping Two Dimensional Systolic Arrays to One Dimensional Arrays and Applications.	ICPP (1)	1988	DBLP BibTeX RDF
16	Lenore M. Restifo Mullin, Ashok Krishnamurthi, Deepa Iyengar	The Design And Development of a Basis alphaL, for Formal Functional Programming Languages with Arrays Based on a Mathematics of Arrays.	ICPP (2)	1988	DBLP BibTeX RDF
16	Thomas Tensi	Worst case analysis for reducing algorithms on instruction systolic arrays with simple instruction sets.	Parcella	1988	DBLP DOI BibTeX RDF
16	Wolfgang Händler	Multiprocessor arrays: Topology, efficiency and fault-tolerance.	Parcella	1988	DBLP DOI BibTeX RDF
16	Nandor Toth	Self-checking processing elements in cellular arrays.	Parcella	1988	DBLP DOI BibTeX RDF
16	Valeriu Beiu	VLSI arrays implementing parallel line-drawing algorithms.	Parcella	1988	DBLP DOI BibTeX RDF
16	Arnold L. Rosenberg, Larry J. Stockmeyer	Hashing Schemes for Extendible Arrays (Extended Arrays)	STOC	1975	DBLP DOI BibTeX RDF
15	Vinod Tipparaju, Edoardo Aprà, Weikuan Yu, Jeffrey S. Vetter	Enabling a highly-scalable global address space model for petascale computing.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	armci, nwchem, xt5, ga, gas, flow control, pgas, global address space, global arrays
15	Michael Eagle, Tiffany Barnes	Experimental evaluation of an educational game for improved learning in introductory computing.	SIGCSE	2009	DBLP DOI BibTeX RDF	cs1-2 education, iteration, retention, educational games, arrays
15	Mario I. Romero-Ortega, Ali Raza Butt, Samir M. Iqbal	Carbon nanotube coated high-throughput neurointerfaces in assistive environments.	PETRA	2009	DBLP DOI BibTeX RDF	super high-density microelectrode arrays (SD-MEA), nanotechnology, carbon nanotubes, reliable computing
15	Michael Eagle, Tiffany Barnes	Evaluation of a game-based lab assignment.	FDG	2009	DBLP DOI BibTeX RDF	CS1-2 education, iteration, retention, educational games, arrays
15	Jin Hwan Park, H. K. Dai 0001	Reconfigurable hardware solution to parallel prefix computation.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
15	Jérémy Barbay, Claire Kenyon	Alternation and redundancy analysis of the intersection problem.	ACM Trans. Algorithms	2008	DBLP DOI BibTeX RDF	Adaptive analysis, alternation analysis, intersection of sorted arrays, randomized algorithm, intersection, redundancy analysis
15	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
15	Rajeev Raman, David S. Wise	Converting to and from Dilated Integers.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Data Structures: Arrays, Programming Techniques: General, Memory Structures: Design Styles, Analysis of Algorithms and Problem Complexity: Numerical algorithms, problems: computations on matrices
15	Ming Liu, Hua Yu, Wei Wang 0003	FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications.	NanoNet	2008	DBLP DOI BibTeX RDF	Field programmable analog arrays (FPAA), Nanojunction devices, Operational amplifier (Op-amp)
15	Simon R. Blackburn, Tuvi Etzion, Keith M. Martin, Maura B. Paterson	Efficient Key Predistribution for Grid-Based Wireless Sensor Networks.	ICITS	2008	DBLP DOI BibTeX RDF	costas arrays, wireless sensor networks, key predistribution
15	Veli Mäkinen, Gonzalo Navarro 0001	On Self-Indexing Images - Image Compression with Added Value.	DCC	2008	DBLP DOI BibTeX RDF	image compression and indexing, self-indexing, suffix arrays, Burrows-Wheeler transform
15	Francesco Simonetti, Lianjie Huang, Neb Duric	Transmission and Reflection Diffraction Tomography in Breast Imaging.	BMEI (2)	2008	DBLP DOI BibTeX RDF	arrays, Tomography, Breast Imaging
15	J. C. Mundarath, Parameswaran Ramanathan, Barry D. Van Veen	A cross layer scheme for adaptive antenna array based wireless ad hoc networks in multipath environments.	Wirel. Networks	2007	DBLP DOI BibTeX RDF	Adaptive Antenna Arrays, MIMO channels, Ad hoc networks, MAC protocol, Cross-Layer design
15	Hans G. Kerkhoff	Testing Microelectronic Biofluidic Systems.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	microelectronic fluidic arrays, flowFET, defect-oriented testing, analog microfluidics, digital microfluidics
15	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient event-driven simulation of parallel processor architectures.	SCOPES	2007	DBLP DOI BibTeX RDF	embedded tools, simulation, modeling, processor arrays
15	Adam Handzlik, Andrzej Jablonski	"Chameleon" Software Defined Control Platform.	EUROCAST	2007	DBLP DOI BibTeX RDF	Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core
15	Alessandro Armando, Massimo Benerecetti, Dario Carotenuto, Jacopo Mantovani, Pasquale Spica	The eureka tool for software model checking.	ASE	2007	DBLP DOI BibTeX RDF	model checking, linear programs, refinement, abstraction, arrays, arithmetic
15	Xun Yuan, Myra B. Cohen, Atif M. Memon	Covering array sampling of input event sequences for automated gui testing.	ASE	2007	DBLP DOI BibTeX RDF	event driven software, GUI testing, covering arrays
15	Fei Su, Sule Ozev, Krishnendu Chakrabarty	Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	droplet-based microfluidic systems, microfluidic arrays, test resource optimization, concurrent testing, test planning
15	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
15	Young-Koo Lee, Woong-Kee Loh, Yang-Sae Moon, Kyu-Young Whang, Il-Yeol Song	An Efficient Algorithm for Computing Range-Groupby Queries.	DASFAA	2006	DBLP DOI BibTeX RDF	range-groupby queries, prefix-sum arrays, data cubes, aggregation queries
15	Manojkumar Krishnan, Jarek Nieplocha	Memory efficient parallel matrix multiplication operation for irregular problems.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	SRUMMA, irregular distribution, parallel programming, parallel matrix multiplication, global arrays, remote memory access, parallel linear algebra
15	César San Martín, Sergio N. Torres	Statistical Recursive Filtering Estimation of Detector Offset Nonuniformity in Infrared Imaging Systems.	CIARP	2006	DBLP DOI BibTeX RDF	Recursive Filtering, Image Sequence Processing, Infrared Focal Plane Arrays
15	Eva Cheng, Ian S. Burnett, Christian H. Ritz	Varying Microphone Patterns for Meeting Speech Segmentation Using Spatial Audio Cues.	PCM	2006	DBLP DOI BibTeX RDF	spatial audio cues, meeting audio analysis, microphone arrays
15	Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk	Optimizing Hardware Function Evaluation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, optimization, Computer arithmetic, gate arrays
15	André DeHon	Nanowire-based programmable architectures.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Manhattan mesh, stochastic construction, sublithographic architecture, programmable logic arrays, Defect tolerance, nanowires, programmable interconnect
15	Kairui Chen, Hui-Chuan Chen, Richard B. Borie, Jonathan C. L. Liu	File replication in video on demand services.	ACM Southeast Regional Conference (1)	2005	DBLP DOI BibTeX RDF	northwest corner rule, transportation model, video on demand, disk arrays, storage capacity, file replication, concurrent accesses, I/O bandwidth
15	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
15	Mehrdad Panahpour Tehrani, Yasushi Hirano, Toshiaki Fujii, Shoji Kajita, Kazuya Takeda, Masayuki Tanimoto, Kenji Mase	The sound wave ray-space.	ICME	2005	DBLP DOI BibTeX RDF	listening-point sound, 3D sound representation, ray-space representation, light ray, beam-formed microphone-arrays, sound-image generation, virtual SImage, geometry compensation, camera
15	Sergio K. Sobarzo, Sergio N. Torres	Real-Time Kalman Filtering for Nonuniformity Correction on Infrared Image Sequences: Performance and Analysis.	CIARP	2005	DBLP DOI BibTeX RDF	Infrared Sensor-Imaging, Processing and Analysis, Image Coding, Kalman Filtering, Signal Processing, Infrared Focal Plane Arrays
15	Inbok Lee, Yoan José Pinzón Ardila	Linear Time Algorithm for the Generalised Longest Common Repeat Problem.	SPIRE	2005	DBLP DOI BibTeX RDF	inverted repeats, DNA repeats, DNA Satellites, pattern discovery, suffix arrays
15	Sergio N. Torres, César San Martín, Daniel Sbarbaro, Jorge E. Pezoa	A Neural Network for Nonuniformity and Ghosting Correction of Infrared Image Sequences.	ICIAR	2005	DBLP DOI BibTeX RDF	Neural Network, Image Sequence Processing, Infrared Focal Plane Arrays
15	Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama	FPGA Implementation of Fast Radix 4 Division Algorithm.	IWSOC	2004	DBLP DOI BibTeX RDF	fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs)
15	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
15	Yun He 0002, Chris H. Q. Ding	An Evaluation of MPI and OpenMP Paradigms for Multi-Dimensional Data Remapping.	WOMPAT	2002	DBLP DOI BibTeX RDF	Dynamical data remapping, index reshuffle, vacancy tracking cycles, global exchange, hybrid MPI/OpenMP, MPI, OpenMP, SMP cluster, multidimensional arrays
15	Yun He 0002, Chris H. Q. Ding	MPI and OpenMP paradigms on cluster of SMP architectures: the vacancy tracking algorithm for multi-dimensional array transposition.	SC	2002	DBLP DOI BibTeX RDF	dynamical remapping, global exchange, hybrid MPI/OpenMP, index reshuffle, vacancy tracking cycles, MPI, OpenMP, SMP, SMP cluster, multidimensional arrays
15	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi	A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications.	DELTA	2002	DBLP DOI BibTeX RDF	Fault Tolerance, Field programmable Gate Arrays, Multistage Interconnection Network, Space Applications
15	Kai-Hau Yeung, Tak-Shing Yum	Dynamic Multiple Parity (DMP) Disk Array for Serial Transaction Processing.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	I/O systems, transaction processing, database systems, RAID, disk arrays
15	Ariel Cohen 0003, Walter A. Burkhard	Segmented Information Dispersal (SID) Data Layouts for Digital Video Servers.	IEEE Trans. Knowl. Data Eng.	2001	DBLP DOI BibTeX RDF	separated difference sets, Algorithms, data structures, video servers, disk arrays, declustering
15	Christoph W. Keßler	NestStep: Nested Parallelism and Virtual Shared Memory for the BSP Model.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	BSP model of parallel computation, message combining, parallel Java extension, nested parallelism, virtual shared memory, distributed arrays
15	Der-Cheng Huang, Wen-Ben Jone	An efficient parallel transparent diagnostic BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
15	Eric Hung-Yu Tseng, Jean-Luc Gaudiot	Communication Generation for Aligned and Cyclic(K) Distributions Using Integer Lattice.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	message passing, HPF, communication optimizations, Distributed arrays, Smith-Normal-Form
15	Sree Ganesan, Ranga Vemuri	A Methodology for Rapid Prototyping of Analog Systems.	ICCD	1999	DBLP DOI BibTeX RDF	rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays
15	Colin D. Walter	Montgomery's Multiplication Technique: How to Make It Smaller and Faster.	CHES	1999	DBLP DOI BibTeX RDF	higher radix methods, checker function, fault tolerance, testing, cryptography, RSA, Computer arithmetic, systolic arrays, error correction, differential power analysis, DPA, Montgomery modular multiplication
15	Frederic Desprez, Jack J. Dongarra, Antoine Petitet, Cyril Randriamaro, Yves Robert	Scheduling Block-Cyclic Array Redistribution.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	block-cyclic distribution, scheduling, MPI, HPF, redistribution, Distributed arrays
15	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
15	Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
15	Steven T. Hackstadt, Christopher W. Harrop, Allen D. Malony	A Framework for Interacting with Distributed Programs and Data.	HPDC	1998	DBLP DOI BibTeX RDF	model coupling, runtime interaction, visualization, Fortran 90, computational steering, distributed arrays, parallel tools
15	Alexander Thomasian, Jai Menon 0001	RAID5 Performance with Distributed Sparing.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	RAID5 disk arrays, dedicated sparing, distributed sparing, operation in degraded mode, rebuild processing, striping unit, small-write syndrome, nonvolatile storage, fast writes, disk zoning, fork-join synchronization, vacationing server model, disk response time, rebuild time, nonpreemptive and preemptive priority queuing, fault-tolerance, performance analysis, queuing theory, M/G/1 queues, disk cache, disk failures
15	Rumen Andonov, Sanjay V. Rajopadhye	Knapsack on VLSI: from Algorithm to Optimal Circuit.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays
15	R. D. (Shawn) Blanton, John P. Hayes	Testability Properties of Divergent Trees.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	regular circuits, interactive logic arrays, structured circuits, test generation, fault detection, fault modeling
15	Yeong-Kang Lai, Liang-Gee Chen, Tsung-Han Tsai 0001, Po-Cheng Wu	A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.	ICIP (2)	1997	DBLP DOI BibTeX RDF	flexible high-throughput VLSI architecture, 2D data-reuse, full-search motion estimation, data-interlacing architecture, one-dimensional processing element array, data-interlacing shift-register arrays, external memory accesses, pin counts, search ranges, pixel rates, VLSI, block sizes, full-search block-matching algorithm
15	Shunichiro Nakamura, Harumi Minemura, Tomohisa Yamaguchi, Hiroshi Shimizu, Takashi Watanabe 0001, Tadanori Mizuno	Poster on A Distributed RAID VOD System.	CoopIS	1997	DBLP DOI BibTeX RDF	distributed RAID, VOD system, video stream transfer, distributed RAID4, Redundant Arrays of Inexpensive Disks, performance, reliability, video on demand, Ethernet, video server, CPU, bottlenecks, magnetic disc storage, diffusion model
15	Fausto Distante, Mariagiovanna Sami, Renato Stefanelli	Array partitioning to achieve defect tolerance.	EUROMICRO	1997	DBLP DOI BibTeX RDF	array partitioning, processing arrays, run time faults, reconfiguration techniques, architectural regularity, interconnection channel width, reconfiguration efficiency, partitioning approach, critical fault patterns, fault tolerance, redundancy, reconfigurable architectures, survival, defect tolerance, path length
15	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
15	Donald L. Hung, Antonio Arsgao, Jorge L. Silva, Eduardo Marques, Karl Hillesland	UB1 - a recurrent neural network based parallel machine for solving simultaneous linear equations.	SBRN	1997	DBLP DOI BibTeX RDF	UB1 recurrent neural network, simultaneous linear equation solving, synchronous execution, field programmable gate arrays, real-time systems, parallel machine, systolic array, neural chips, ring topology, neural net architecture
15	Tadayoshi Horita, Itsuo Takanami	A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.	ISPAN	1997	DBLP DOI BibTeX RDF	mesh arrays, the 1frac{1}{2} track-switch model, fault-tolerance, polynomial time algorithm, wafer scale integration
15	Tsunehiko Kamachi, Kazuhiro Kusano, Kenji Suehiro, Yoshiki Seo	Generating Realignment-Based Communication for HPF Programs.	IPPS	1996	DBLP DOI BibTeX RDF	realignment-based communication, HPF programs, iteration template, loop iteration mapping, two-level mapping, user-declared alignment, optimal alignment, NEC Cenju-3, compiler-generated program, hand-parallelized program, parallel programming, compiler, FORTRAN, distributed memory systems, software performance evaluation, parallel languages, parallel language, execution time, arrays, software portability, software portability, loops, High Performance Fortran, distributed-memory machines, distributed-memory machine, data mapping, program control structures, parallelising compilers, iteration space
15	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses.	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
15	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation.	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
15	István Forgács	An Exact Array Reference Analysis for Data Flow Testing.	ICSE	1996	DBLP BibTeX RDF	approximate information, definition-use pairs, exact array reference analysis, formulae negation avoidance, precise method, program path execution, program testing, data flow analysis, arrays, program optimization, data flow testing, program parallelization
15	Paul Camion, Anne Canteaut	Generalization of Siegenthaler Inequality and Schnorr-Vaudenay Multipermutations.	CRYPTO	1996	DBLP DOI BibTeX RDF	Correlation-immune functions, cryptanalysis, stream ciphers, hash functions, orthogonal arrays
15	Fauzia Ahmad, Saleem A. Kassam	A new approach to aperture synthesis using frequency diversity imaging.	ICIP	1995	DBLP DOI BibTeX RDF	aperture synthesis, frequency diversity imaging, imaging arrays, spatially incoherent source distributions, coarray concept, coherent distribution of reflectors, simulation, performance, synthetic aperture radar, array signal processing, optical transfer function
15	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
15	Guillermo A. Alvarez, Marcelo O. Fernández, Ragelio A. Alvez, Sylvia Rodriguez, Julio A. Sánchez Avalos, Jorge L. C. Sanz	Run-time support for asynchronous parallel computations.	IPPS	1995	DBLP DOI BibTeX RDF	asynchronous parallel computations, DREAM, asynchronous multiprocessors, global distributed arrays, dynamic communication patterns, performance evaluation, scalability, parallel computations, programming environments, multiprocessing systems, network latency, run-time support, performance results, distributed programming environment
15	Martin C. Herbordt, Charles C. Weems	An empirical study of datapath, memory hierarchy, and network in SIMD array architectures.	ICCD	1995	DBLP DOI BibTeX RDF	SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
15	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
15	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
15	Sushil K. Prasad, Sajal K. Das 0001, Calvin Ching-Yuen Chen	Efficient EREW PRAM Algorithms for Parentheses-Matching.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	EREW PRAM algorithms, parentheses-matching, polylog-time parallel algorithms, exclusive-read and exclusive-write, parallelrandom-access machine, input string, working space, time-optimal algorithms, pattern recognition, parallel algorithms, computational complexity, data structures, data structures, parallel machines, time complexity, arrays, space complexity, random-access storage, PRAM model
15	Hervé Le Verge	Reduction Operators in ALPHA.	PARLE	1992	DBLP DOI BibTeX RDF	Parallel Languages extensions, Programming environments for parallel languages, Systolic arrays and regular computation