Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel	Logic BIST Using Constrained Scan Cells.	VTS	2004	DBLP DOI BibTeX RDF
9	Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski	Realizing High Test Quality Goals with Smart Test Resource Usage.	ITC	2004	DBLP DOI BibTeX RDF
9	David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher	An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor.	ITC	2004	DBLP DOI BibTeX RDF
9	C. P. Ravikumar, Graham Hetherington	A Holistic Parallel and Hierarchical Approach towards Design-For-Test.	ITC	2004	DBLP DOI BibTeX RDF	Experiments and Case Studies, Practical Test Engineering
9	Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski	Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.	ITC	2004	DBLP DOI BibTeX RDF
9	Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington	Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.	ITC	2004	DBLP DOI BibTeX RDF
9	Aman Kokrady, C. P. Ravikumar	Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.	VLSI Design	2004	DBLP DOI BibTeX RDF	Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop
9	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
9	Yu Zheng, Kenneth L. Shepard	On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
9	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
9	Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker	A circuit level fault model for resistive bridges.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	fault models, bridge faults, delay faults
9	Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli	High-Frequency, At-Speed Scan Testing.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
9	Wangqi Qiu, D. M. H. Walker	Testing the Path Delay Faults of ISCAS85 Circuit c6288.	MTV	2003	DBLP DOI BibTeX RDF
9	Mahesh A. Iyer	A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification.	MTV	2003	DBLP DOI BibTeX RDF
9	Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji	Design Retargetable Platform System for Microprocessor Functional Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
9	Guanghui Li 0001, Ming Shao, Xiaowei Li 0001	Design Error Diagnosis Based on Verification Techniques.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
9	Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu	Automated Test Model Generation from Switch Level Custom Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
9	Elizabeth Broering, Satyanarayana V. Lokam	Width-Based Algorithms for SAT and CIRCUIT-SAT: (Extended Abstract).	SAT	2003	DBLP DOI BibTeX RDF
9	Aman Kokrady, C. P. Ravikumar	Static Verification of Test Vectors for IR Drop Failure.	ICCAD	2003	DBLP DOI BibTeX RDF
9	C. V. Krishna, Nur A. Touba	Adjustable Width Linear Combinational Scan Vector Decompression.	ICCAD	2003	DBLP DOI BibTeX RDF
9	Subhasish Mitra, Kee Sup Kim	XMAX: X-Tolerant Architecture for MAXimal Test Compression.	ICCD	2003	DBLP DOI BibTeX RDF
9	Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies	Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.	ICCD	2003	DBLP DOI BibTeX RDF
9	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz	A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
9	Chunsheng Liu, Krishnendu Chakrabarty	Compact Dictionaries for Fault Diagnosis in BIST.	ISQED	2003	DBLP DOI BibTeX RDF
9	Manish Sharma, Janak H. Patel, Jeff Rearick	Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture.	VTS	2003	DBLP DOI BibTeX RDF
9	Wangqi Qiu, D. M. H. Walker	An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit.	ITC	2003	DBLP DOI BibTeX RDF
9	David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish	H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.	ITC	2003	DBLP DOI BibTeX RDF
9	Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja	Exclusive Test and its Applications to Fault Diagnosis.	VLSI Design	2003	DBLP DOI BibTeX RDF
9	Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF
9	Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu	Test application time and volume compression through seed overlapping.	DAC	2003	DBLP DOI BibTeX RDF	XOR Network, scan chain concealment, test compression, SOC Test, deterministic test
9	Antoni Ferré, Joan Figueras	Leakage power bounds in CMOS digital technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton	Test vector generation for charge sharing failures in dynamic logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Ki-Wook Kim, Taewhan Kim, C. L. Liu 0001, Sung-Mo Kang	Domino logic synthesis based on implication graph.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera	Extending OPMISR beyond 10x Scan Test Efficiency.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
9	Jason Cong, Yizhou Lin, Wangning Long	SPFD-based global rewiring.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis
9	André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová	Internet-Based Collaborative Test Generation with MOSCITO.	DATE	2002	DBLP DOI BibTeX RDF
9	Soumitra Bose	Automated Modeling of Custom Digital Circuits for Test.	DATE	2002	DBLP DOI BibTeX RDF
9	Irith Pomeranz, Sudhakar M. Reddy	Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults.	DATE	2002	DBLP DOI BibTeX RDF
9	Saravanan Padmanaban, Spyros Tragoudas	Exact Grading of Multiple Path Delay Faults.	DATE	2002	DBLP DOI BibTeX RDF
9	André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng	Integrated Design and Test Generation Under Internet Based Environment MOSCITO.	DSD	2002	DBLP DOI BibTeX RDF
9	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu	A Method to Reduce Power Dissipation during Test for Sequential Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
9	Irith Pomeranz, Sudhakar M. Reddy	Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
9	Mandana Amiri, Andreas G. Veneris, Ivor Ting	Design rewiring for power minimization [logic design].	ISCAS (4)	2002	DBLP DOI BibTeX RDF
9	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Program Generation from RT-Level Microprocessor Descriptions.	ISQED	2002	DBLP DOI BibTeX RDF
9	Dave Stang, Ramaswami Dandapani	An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.	ITC	2002	DBLP DOI BibTeX RDF
9	Francis G. Wolff, Christos A. Papachristou	Multiscan-Based Test Compression and Hardware Decompression Using LZ77.	ITC	2002	DBLP DOI BibTeX RDF
9	Manish Sharma, Janak H. Patel	Finding a Small Set of Longest Testable Paths that Cover Every Gate.	ITC	2002	DBLP DOI BibTeX RDF
9	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Techniques to Reduce Data Volume and Application Time for Transition Test.	ITC	2002	DBLP DOI BibTeX RDF
9	Vishal Jain, John A. Waicukauski	Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.	ITC	2002	DBLP DOI BibTeX RDF
9	Bipul Chandra Paul, Kaushik Roy 0001	Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.	ITC	2002	DBLP DOI BibTeX RDF
9	Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston	Effective diagnostics through interval unloads in a BIST environment.	DAC	2002	DBLP DOI BibTeX RDF	fault diagnosis, built-in self-test (BIST)
9	Demos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion	A practical and efficient method for compare-point matching.	DAC	2002	DBLP DOI BibTeX RDF	combinational verification, latch mapping, equivalence checking
9	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.	DAC	2002	DBLP DOI BibTeX RDF	boolean constraint propagation (BCP), bounded model checking (BMC), conjunctive normal form (CNF), boolean satisfiability (SAT)
9	Antoni Ferré, Joan Figueras	LEAP: An Accurate Defect-Free IDDQ Estimator.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	leakage current, I DDQ
9	Shivakumar Swaminathan, Krishnendu Chakrabarty	On Using Twisted-Ring Counters for Test Set Embedding in BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
9	Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal	SIVA: A System for Coverage-Directed State Space Search.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	formal methods, coverage, functional verification, guided search
9	Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng	Fast Test Cost Calculation for Hybrid BIST in Digital Systems.	DSD	2001	DBLP DOI BibTeX RDF
9	Chin Ngai Sze, Yu-Liang Wu	Improved alternative wiring scheme applying dominator relationship.	ASP-DAC	2001	DBLP DOI BibTeX RDF
9	Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura	Dynamic Test Compression Using Statistical Coding.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
9	Ofer Strichman	Pruning Techniques for the SAT-Based Bounded Model Checking Problem.	CHARME	2001	DBLP DOI BibTeX RDF
9	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain.	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
9	Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton	Testing of Dynamic Logic Circuits Based on Charge Sharing.	VTS	2001	DBLP DOI BibTeX RDF
9	Magdy S. Abadir, Juhong Zhu, Li-C. Wang	Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.	VTS	2001	DBLP DOI BibTeX RDF
9	Sitaram Yadavalli, Sandip Kundu	On Fault-Simulation Through Embedded Memories On Large Industrial Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
9	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Estimation for maximum instantaneous current through supply lines for CMOS circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
9	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer	AQUILA: An Equivalence Checking System for Large Sequential Designs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	state exploration, formal verification, Design verification, equivalence checking
9	Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara	LFSR-Based Deterministic TPG for Two-Pattern Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	configurable LFSR, built-in self-test, path delay faults, two-pattern test
9	Rohit Kapur, Cy Hay, Thomas W. Williams	The Mutating Metric for Benchmarking Test.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
9	Lijian Li, Yinghua Min	An efficient BIST design using LFSR-ROM architecture.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	read-only storage, BIST design, LFSR-ROM architecture, built-in self test, logic design, automatic test pattern generation, test pattern generation, integrated circuit design, shift registers, hardware overhead, ROM, integrated circuit economics
9	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
9	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
9	Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara	Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.	VLSI Design	2000	DBLP DOI BibTeX RDF	Complete fault efficiency, Design for testability, Data path, Hierarchical test
9	Yu-Liang Wu, Wangning Long, Hongbing Fan	A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.	VLSI Design	2000	DBLP DOI BibTeX RDF	Alternative wiring, Graph-based pattern matching, Logic synthesis
9	Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab	Hierarchical Test Generation for Systems On a Chip.	VLSI Design	2000	DBLP DOI BibTeX RDF
9	Dinos Moundanos, Jacob A. Abraham	On Design Validation Using Verification Technology.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	extracted control flow machine, verification, abstraction, test generation, coverage analysis, OBDDs
9	Ilker Hamzaoglu, Janak H. Patel	New Techniques for Deterministic Test Pattern Generation.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	redundancy, stuck-at fault, Boolean satisfiability, automatic test generation, scan design, logic implications
9	Ghassan Al Hayek, Chantal Robach	From Design Validation to Hardware Testing: A Unified Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	VHDL, mutation testing, design validation
9	Harry Hengster, Bernd Becker 0001	Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.	FTCS	1999	DBLP DOI BibTeX RDF	EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits
9	Toshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi	Estimation of Peak Current through CMOS VLSI Circuit Supply Lines.	ASP-DAC	1999	DBLP DOI BibTeX RDF
9	Martin Keim, Nicole Drechsler, Bernd Becker 0001	Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
9	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
9	Fatih Kocan, Daniel G. Saab	Concurrent D-algorithm on reconfigurable hardware.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Ki-Wook Kim, C. L. Liu 0001, Sung-Mo Kang	Implication graph based domino logic synthesis.	ICCAD	1999	DBLP DOI BibTeX RDF
9	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías	Logic Restructuring for MUX-Based FPGAs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Paul Chang, Brion L. Keller, Sarala Paliwal	Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm.	ICCD	1999	DBLP DOI BibTeX RDF	LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation
9	Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001	Test pattern generation for width compression in BIST.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
9	Josef Schmid, Joachim Knäblein	Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.	VTS	1999	DBLP DOI BibTeX RDF
9	HyungWon Kim 0001, John P. Hayes	Delay Fault Testing of Designs with Embedded IP Cores.	VTS	1999	DBLP DOI BibTeX RDF
9	Michael A. Margolese, F. Joel Ferguson	Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test.	VTS	1999	DBLP DOI BibTeX RDF
9	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	RT-level TPG Exploiting High-Level Synthesis Information.	VTS	1999	DBLP DOI BibTeX RDF
9	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	Superscalar Processor Validation at the Microarchitecture Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
9	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller redesign technique to enhance testability of controller-data path circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Frank F. Hsu, Janak H. Patel	High-Level Controllability and Observability Analysis for Test Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controllability, observability, high-level test synthesis, behavioral modification
9	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante	Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.	DATE	1998	DBLP DOI BibTeX RDF
9	Zhongcheng Li, Yinghua Min, Robert K. Brayton	A New Low-Cost Method for Identifying Untestable Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	non-robustly untestable, Delay testing, path delay fault, implication
9	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
9	Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth	Synthesis of Sequential Circuits with Clock Control to Improve Testability.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
9	Ilker Hamzaoglu, Janak H. Patel	Compact two-pattern test set generation for combinational and full scan circuits.	ITC	1998	DBLP DOI BibTeX RDF
9	Yiorgos Makris, Alex Orailoglu	DFT guidance through RTL test justification and propagation analysis.	ITC	1998	DBLP DOI BibTeX RDF
9	Young-Jun Kwon, Ben Mathew, Hong Hao	FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.	ITC	1998	DBLP DOI BibTeX RDF