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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1073 occurrences of 407 keywords
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Results
Found 939 publication records. Showing 939 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
9 | Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel |
Logic BIST Using Constrained Scan Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 199-205, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski |
Realizing High Test Quality Goals with Smart Test Resource Usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 525-533, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher |
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 38-47, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | C. P. Ravikumar, Graham Hetherington |
A Holistic Parallel and Hierarchical Approach towards Design-For-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 345-354, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Experiments and Case Studies, Practical Test Engineering |
9 | Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski |
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1285-1294, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington |
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 355-364, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Aman Kokrady, C. P. Ravikumar |
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 597-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop |
9 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 487-492, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Yu Zheng, Kenneth L. Shepard |
On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 336-344, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 223-231, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
pseudo-random testing, deterministic BIST, logic BIST |
9 | Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
A circuit level fault model for resistive bridges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 546-559, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault models, bridge faults, delay faults |
9 | Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli |
High-Frequency, At-Speed Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 17-25, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Wangqi Qiu, D. M. H. Walker |
Testing the Path Delay Faults of ISCAS85 Circuit c6288. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 19-, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Mahesh A. Iyer |
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 95-, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji |
Design Retargetable Platform System for Microprocessor Functional Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 458-461, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Guanghui Li 0001, Ming Shao, Xiaowei Li 0001 |
Design Error Diagnosis Based on Verification Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 474-477, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu |
Automated Test Model Generation from Switch Level Custom Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 184-189, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Elizabeth Broering, Satyanarayana V. Lokam |
Width-Based Algorithms for SAT and CIRCUIT-SAT: (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers, pp. 162-171, 2003, Springer, 3-540-20851-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Aman Kokrady, C. P. Ravikumar |
Static Verification of Test Vectors for IR Drop Failure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 760-764, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | C. V. Krishna, Nur A. Touba |
Adjustable Width Linear Combinational Scan Vector Decompression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 863-866, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Subhasish Mitra, Kee Sup Kim |
XMAX: X-Tolerant Architecture for MAXimal Test Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 326-330, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies |
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 180-186, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz |
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 397-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Chunsheng Liu, Krishnendu Chakrabarty |
Compact Dictionaries for Fault Diagnosis in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 105-110, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Manish Sharma, Janak H. Patel, Jeff Rearick |
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 15-21, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Wangqi Qiu, D. M. H. Walker |
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 592-601, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish |
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1229-1238, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja |
Exclusive Test and its Applications to Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 143-148, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 149-154, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu |
Test application time and volume compression through seed overlapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 732-737, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
XOR Network, scan chain concealment, test compression, SOC Test, deterministic test |
9 | Antoni Ferré, Joan Figueras |
Leakage power bounds in CMOS digital technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6), pp. 731-738, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton |
Test vector generation for charge sharing failures in dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1502-1508, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Ki-Wook Kim, Taewhan Kim, C. L. Liu 0001, Sung-Mo Kang |
Domino logic synthesis based on implication graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2), pp. 232-240, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera |
Extending OPMISR beyond 10x Scan Test Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(5), pp. 65-72, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Jason Cong, Yizhou Lin, Wangning Long |
SPFD-based global rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 77-84, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis |
9 | André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová |
Internet-Based Collaborative Test Generation with MOSCITO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 221-226, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Soumitra Bose |
Automated Modeling of Custom Digital Circuits for Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 954-961, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Irith Pomeranz, Sudhakar M. Reddy |
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 722-729, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Saravanan Padmanaban, Spyros Tragoudas |
Exact Grading of Multiple Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 84-88, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng |
Integrated Design and Test Generation Under Internet Based Environment MOSCITO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 187-195, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu |
A Method to Reduce Power Dissipation during Test for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 326-331, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 61-66, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Mandana Amiri, Andreas G. Veneris, Ivor Ting |
Design rewiring for power minimization [logic design]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 305-308, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero |
Automatic Test Program Generation from RT-Level Microprocessor Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 120-125, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Dave Stang, Ramaswami Dandapani |
An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 746-754, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Francis G. Wolff, Christos A. Papachristou |
Multiscan-Based Test Compression and Hardware Decompression Using LZ77. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 331-339, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Manish Sharma, Janak H. Patel |
Finding a Small Set of Longest Testable Paths that Cover Every Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 974-982, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Techniques to Reduce Data Volume and Application Time for Transition Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 983-992, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Vishal Jain, John A. Waicukauski |
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 148-153, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Bipul Chandra Paul, Kaushik Roy 0001 |
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 384-390, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston |
Effective diagnostics through interval unloads in a BIST environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 249-254, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault diagnosis, built-in self-test (BIST) |
9 | Demos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion |
A practical and efficient method for compare-point matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 305-310, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
combinational verification, latch mapping, equivalence checking |
9 | Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik |
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 747-750, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
boolean constraint propagation (BCP), bounded model checking (BMC), conjunctive normal form (CNF), boolean satisfiability (SAT) |
9 | Antoni Ferré, Joan Figueras |
LEAP: An Accurate Defect-Free IDDQ Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 267-274, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
leakage current, I DDQ |
9 | Shivakumar Swaminathan, Krishnendu Chakrabarty |
On Using Twisted-Ring Counters for Test Set Embedding in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(6), pp. 529-542, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST |
9 | Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal |
SIVA: A System for Coverage-Directed State Space Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(1), pp. 11-27, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
formal methods, coverage, functional verification, guided search |
9 | Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng |
Fast Test Cost Calculation for Hybrid BIST in Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 318-325, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Chin Ngai Sze, Yu-Liang Wu |
Improved alternative wiring scheme applying dominator relationship. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 473-478, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura |
Dynamic Test Compression Using Statistical Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 143-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Ofer Strichman |
Pruning Techniques for the SAT-Based Bounded Model Checking Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001, Proceedings, pp. 58-70, 2001, Springer, 3-540-42541-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Ondrej Novák, Jiri Nosek |
Test Pattern Decompression Using a Scan Chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 110-115, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
hardware test pattern generators, BIST, test pattern generation, scan design |
9 | Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton |
Testing of Dynamic Logic Circuits Based on Charge Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 396-403, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Magdy S. Abadir, Juhong Zhu, Li-C. Wang |
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 252-259, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Sitaram Yadavalli, Sandip Kundu |
On Fault-Simulation Through Embedded Memories On Large Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 117-121, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng |
Estimation for maximum instantaneous current through supply lines for CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 61-73, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer |
AQUILA: An Equivalence Checking System for Large Sequential Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(5), pp. 443-464, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
state exploration, formal verification, Design verification, equivalence checking |
9 | Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara |
LFSR-Based Deterministic TPG for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 419-426, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable LFSR, built-in self-test, path delay faults, two-pattern test |
9 | Rohit Kapur, Cy Hay, Thomas W. Williams |
The Mutating Metric for Benchmarking Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 17(3), pp. 18-21, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Lijian Li, Yinghua Min |
An efficient BIST design using LFSR-ROM architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 386-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
read-only storage, BIST design, LFSR-ROM architecture, built-in self test, logic design, automatic test pattern generation, test pattern generation, integrated circuit design, shift registers, hardware overhead, ROM, integrated circuit economics |
9 | Ameet Bagwe, Rubin A. Parekhji |
Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 260-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis |
9 | Ilker Hamzaoglu, Janak H. Patel |
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 369-376, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model |
9 | Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara |
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 300-305, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Complete fault efficiency, Design for testability, Data path, Hierarchical test |
9 | Yu-Liang Wu, Wangning Long, Hongbing Fan |
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 268-273, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Alternative wiring, Graph-based pattern matching, Logic synthesis |
9 | Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab |
Hierarchical Test Generation for Systems On a Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 198-, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Dinos Moundanos, Jacob A. Abraham |
On Design Validation Using Verification Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 173-189, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
extracted control flow machine, verification, abstraction, test generation, coverage analysis, OBDDs |
9 | Ilker Hamzaoglu, Janak H. Patel |
New Techniques for Deterministic Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 63-73, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
redundancy, stuck-at fault, Boolean satisfiability, automatic test generation, scan design, logic implications |
9 | Ghassan Al Hayek, Chantal Robach |
From Design Validation to Hardware Testing: A Unified Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 133-140, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
VHDL, mutation testing, design validation |
9 | Harry Hengster, Bernd Becker 0001 |
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 268-275, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits |
9 | Toshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi |
Estimation of Peak Current through CMOS VLSI Circuit Supply Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 295-298, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Martin Keim, Nicole Drechsler, Bernd Becker 0001 |
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 315-318, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara |
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 263-268, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Fatih Kocan, Daniel G. Saab |
Concurrent D-algorithm on reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 152-156, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Ki-Wook Kim, C. L. Liu 0001, Sung-Mo Kang |
Implication graph based domino logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 111-114, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías |
Logic Restructuring for MUX-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1161-, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 175-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation |
9 | Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001 |
Test pattern generation for width compression in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 114-118, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Josef Schmid, Joachim Knäblein |
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 106-113, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | HyungWon Kim 0001, John P. Hayes |
Delay Fault Testing of Designs with Embedded IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 160-167, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Michael A. Margolese, F. Joel Ferguson |
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 80-85, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto |
RT-level TPG Exploiting High-Level Synthesis Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 341-353, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
Superscalar Processor Validation at the Microarchitecture Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 300-305, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
A controller redesign technique to enhance testability of controller-data path circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 157-168, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Frank F. Hsu, Janak H. Patel |
High-Level Controllability and Observability Analysis for Test Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 93-103, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
controllability, observability, high-level test synthesis, behavioral modification |
9 | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante |
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 670-677, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Zhongcheng Li, Yinghua Min, Robert K. Brayton |
A New Low-Cost Method for Identifying Untestable Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 76-81, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
non-robustly untestable, Delay testing, path delay fault, implication |
9 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 418-423, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth |
Synthesis of Sequential Circuits with Clock Control to Improve Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 472-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Ilker Hamzaoglu, Janak H. Patel |
Compact two-pattern test set generation for combinational and full scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 944-953, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Yiorgos Makris, Alex Orailoglu |
DFT guidance through RTL test justification and propagation analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 668-677, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Young-Jun Kwon, Ben Mathew, Hong Hao |
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 727-732, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
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